CN113869477B - RFID (radio frequency identification) tag chip and chip power consumption control method - Google Patents
RFID (radio frequency identification) tag chip and chip power consumption control method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/0701—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/072—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising a plurality of integrated circuit chips
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Abstract
The invention provides an RFID label chip and a chip power consumption control method, comprising the following steps: the frequency division module is used for receiving a clock signal with a preset frequency and outputting the frequency division clock signal to the clock gating module; the clock gating module is used for receiving a module gating enabling signal sent by the power consumption control module and controlling the on or off of a clock signal of the functional module; the controller is used for controlling the opening or closing of the functional module based on the functional module enabling signal; the power consumption control module is used for logically combining the function module enabling signal, the internal signal and the internal state of the function module to output a module gating enabling signal, restricting the working time of the frequency division clock signal and controlling the working power consumption of the function module; the function module executes a preset function based on the signal. According to the invention, the power consumption control module is arranged in the RFID tag chip, the clock frequency of the operation of the control function module, the operation performance of the control function module and the demodulation power consumption are controlled, and the whole power consumption control of the chip is realized.
Description
Technical Field
The invention relates to the technical field of radio frequency identification, in particular to an RFID (radio frequency identification) tag chip and a chip power consumption control method.
Background
An RFID (Radio Frequency Identification) tag is classified into a passive tag and an active tag as a non-contact tag chip. The passive tag extracts energy required by the interior by means of radio frequency energy emitted by the reader, and the energy is used by an internal analog circuit and a digital circuit.
In a long distance or in an environment where multiple tags are present, the energy that can be acquired by the tags is small, and since the energy consumed inside the tag chip is insufficient to supply the energy to the inside, the tags cannot realize the required functions, and the tags will fail. At present, there is no effective method to solve the above problems.
Disclosure of Invention
The invention provides an RFID (radio frequency identification) tag chip and a chip power consumption control method, which are used for solving the defect that the internal power consumption of the RFID tag chip in the prior art cannot be effectively controlled.
In a first aspect, the present invention provides an RFID tag chip, comprising:
frequency division module, clock gate control module, controller, power consumption control module and functional module, wherein:
the frequency division module is used for receiving a clock signal with a preset frequency and outputting the frequency division clock signal to the clock gating module;
the clock gating module is used for receiving a module gating enabling signal sent by the power consumption control module and controlling the clock signal of the functional module to be turned on or turned off;
the controller is used for controlling the opening or closing of the functional module based on the functional module enabling signal;
the power consumption control module is used for logically combining the functional module enabling signal, the internal signal of the functional module and the internal state to output the module gating enabling signal, restricting the working time of the frequency division clock signal and controlling the working power consumption of the functional module;
the function module is used for executing a preset function based on the module gating enable signal, the frequency division clock signal and the function module enable signal.
According to the RFID tag chip provided by the invention, the functional module comprises a plurality of functional units, the functional units are clocked by different frequency division clock signals, and the different frequency division clock signals are obtained by equally dividing the preset frequency clock signal.
In a second aspect, the present invention further provides a method for controlling chip power consumption, including:
the frequency division module receives a clock signal with a preset frequency and outputs the frequency division clock signal to the clock gating module;
the clock gating module receives the frequency division clock signal and a module gating enabling signal sent by the power consumption control module, and sends a control instruction of the clock signal to the function module;
the controller receives an enabling signal sent by the clock gating module and sends a functional module enabling signal to the functional module through the clock gating module;
and the functional module receives the module gating enable signal, the frequency division clock signal and the functional module enable signal and executes a preset function.
According to the power consumption control method of the RFID tag chip, the module gating enabling signal is obtained by logically combining the functional module enabling signal, the internal signal of the functional module and the internal state through the power consumption control module.
According to the power consumption control method of the RFID label chip provided by the invention, the frequency division module receives a clock signal with a preset frequency and outputs the frequency division clock signal to the clock gating module, and the method comprises the following steps:
and equally dividing the preset frequency clock signal into a plurality of frequency division clock signals, and sending one of the frequency division clock signals to the clock gating module.
According to the power consumption control method of the RFID tag chip provided by the invention, the controller receives the enabling signal sent by the clock gating module and sends the enabling signal of the functional module to the functional module through the clock gating module, and the method comprises the following steps:
and starting the functional unit in the functional module based on the functional module enabling signal to enable the functional unit to execute a preset function.
According to the power consumption control method of the RFID tag chip provided by the invention, the controller receives the enabling signal sent by the clock gating module and sends the enabling signal of the functional module to the functional module through the clock gating module, and the method further comprises the following steps:
and closing the functional unit in the functional module based on the functional module enabling signal to enable the functional unit not to execute a preset function.
According to the power consumption control method of the RFID tag chip provided by the present invention, the functional module receives the module gating enable signal, the frequency division clock signal, and the functional module enable signal, and executes a preset function, which previously includes:
the power consumption control module generates a clock signal based on the effective signal and sends the clock signal to a corresponding functional unit in the functional module;
and the corresponding functional unit loads data for processing based on the clock signal, closes the clock signal, and loads and processes the data when the next effective signal is received.
According to the power consumption control method of the RFID tag chip provided by the present invention, the functional module receives the module gating enable signal, the frequency division clock signal, and the functional module enable signal, and executes a preset function, and the method further includes:
the power consumption control module generates a clock signal based on the start effective signal and sends the clock signal to a corresponding functional unit in the functional module;
and the corresponding functional unit loads data for processing based on the clock signal enabling working state signal, closes the clock signal, and loads and processes the data when a next effective starting signal is started.
According to the power consumption control method of the RFID label chip provided by the invention, the method further comprises the following steps:
and the controller controls all demodulation enabling and/or preset proportion demodulation enabling to turn on or turn off the demodulation power consumption enabling of the corresponding functional unit in the functional module.
According to the RFID tag chip and the chip power consumption control method provided by the invention, the power consumption control module is arranged in the RFID tag chip, the clock frequency of the operation of the function module is controlled, the operation performance of the function module is controlled, and the demodulation power consumption is controlled, so that the overall power consumption control of the chip is realized.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a system block diagram of an RFID tag chip provided by the present invention;
FIG. 2 is a schematic diagram illustrating the operation of a power consumption control module according to the present invention;
FIG. 3 is a flow chart of a power consumption control method for an RFID tag chip according to the present invention;
FIG. 4 illustrates one of the power consumption control modes provided by the present invention;
fig. 5 shows a second power consumption control method provided by the present invention.
Reference numerals:
1: a frequency division module; 2: a clock gating module; 3: a controller; 4: a power consumption control module;
5: a functional module; 6: decoding the gating enable; 7: data parsing gating enable;
8: shaping gating enable; 9: anti-collision gating enabling; 10: EEPROM gate control is enabled;
11: enabling the timer gating; 12: random number gating is enabled; 13: encoding a gating enable;
14: stctrl gating enables; 15: CRC gating enable; 16: the demodulation is enabled.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to avoid the failure of partial module functions caused by the energy loss of the RFID tag chip in the prior art, the invention provides a novel low-power-consumption RFID tag chip and a corresponding chip power consumption control method.
Fig. 1 is a system block diagram of an RFID tag chip provided in the present invention, as shown in fig. 1, including:
frequency division module, clock gate control module, controller, power consumption control module and functional module, wherein:
the frequency division module is used for receiving a clock signal with a preset frequency and outputting the frequency division clock signal to the clock gating module;
the clock gating module is used for receiving a module gating enabling signal sent by the power consumption control module and controlling the clock signal of the functional module to be turned on or turned off;
the controller is used for controlling the opening or closing of the functional module based on the functional module enabling signal;
the power consumption control module is used for logically combining the functional module enabling signal, the internal signal of the functional module and the internal state to output the module gating enabling signal, restricting the working time of the frequency division clock signal and controlling the working power consumption of the functional module;
the function module is used for executing a preset function based on the module gating enable signal, the frequency division clock signal and the function module enable signal.
The new low-power consumption RFID chip provided by the invention mainly comprises 5 parts, as shown in figure 1, including: the device comprises a frequency division module 1, a clock gating module 2, a controller 3, a power consumption control module 4 and a functional module 5.
First, the input signal includes a clock signal having a frequency of 13.56MHz/s, a Power-On Reset (Power-On Reset), a 100% demodulation signal, and a 10% demodulation signal, and the output signal includes an encoding signal, a 10% demodulation enable signal, a 100% demodulation enable signal, and a 10% demodulation sensitivity signal.
The frequency division module 1 divides the frequency of the system according to the clock requirement of each functional module and sends the frequency to each functional module, and in order to reduce the overall power consumption, the frequency of the system clock needs to be reduced, and the clock frequency is reduced under the condition that the module function is not influenced and the speed is greatly influenced, so that the power consumption is reduced. For example, the decoding module of function module 5 uses clk8 (division 8 of 13.56 MHz/s) to reduce the clock frequency and reduce the dynamic power consumption without responding to the decoding function.
The clock gating module 2 is used for closing or opening the clock of the functional module 5 according to the module gating enabling signal provided by the power consumption control module 4, and closing the corresponding clock signal under the condition of not needing to work, so that unnecessary clock turnover is reduced, and the overall power consumption of the module is reduced.
The controller 3 is a control end for coordinating the operation of each module and controlling the operation of the whole system. The controller 3 can control the operation of a certain functional module to execute a specific functional requirement, and when the operation of the functional module is not required, the module is enabled to be closed, the operation of the functional module is closed, and the clock gating module 2 closes the clock signal to the module according to the enable signal, so that the power consumption when the module is not operated is reduced.
The power consumption control module 4 controls power consumption of each functional module of the system, as shown in fig. 1, and includes shaping, decoding, data parsing, CRC (Cyclic Redundancy Check), encoding, RNG (Random number Generator), stctrl, timer, anti-collision and EEPROM (Electrically Erasable Programmable read only memory) interface control. Each module divides the clock signal according to the corresponding unused frequency shown in FIG. 1, clk2 is a divide-by-two of the clock with frequency of 13.56MHz/s, clk4 is a divide-by-four of the clock with frequency of 13.56MHz/s, and clk8 is a divide-by-eight of the clock with frequency of 13.56 MHz/s. The clk8 clock used for shaping, decoding and data analysis is determined by protocol requirements and error tolerance, and the eight-frequency-division clock is used for reducing the running power consumption of the whole decoding without affecting the decoding correctness; the EEPROM interface control, the timer and the RNG also adopt an eight-frequency dividing clk8 clock, and when the modules do not need high frequency in operation, the clk8 clock is enough to complete the function, so that the clock frequency is reduced, and the operation power consumption is reduced; the CRC module, the anti-collision module and the stctrl module adopt clock signals of four frequency division, so that the clock frequencies are kept consistent with the clock frequency of the controller, the signal detection between the modules is more convenient, and the speed can be reduced, but because the modules perform more detailed clock control subsequently, the clock use frequency is very low, the proportion of the clock use frequency to the clock length is very small, so that the large power consumption difference cannot be generated by adopting the clock of four frequency division or eight frequency division, and the clock of four frequency division is uniformly adopted for operation portability; only the coding module adopts the frequency division by two, because the ISO 15693 protocol limits the lowest frequency, and because in the case of double subcarriers, there are subcarriers with frequency division of 14 and 16, the smallest common divisor of 2, namely the frequency division clock, is taken as the clock of the coding module.
The function module 5 is a specific function implementation module, for example, CRC, encoding, decoding and calculation are all executed in this part, the controller 3 enables the power consumption control module 4, the power consumption control module 4 generates a gating enable signal according to logic judgment, the clock gating module 2 provides a corresponding clock signal to the function module 5 according to the gating enable signal, so that the function module 5 executes a corresponding specific function under the control of the clock signal.
According to the invention, the frequency division module, the clock gating module, the controller, the power consumption control module and the function module are arranged in the RFID tag chip, and the whole power consumption control of the chip is realized by controlling the clock frequency of the function module, controlling the function of the function module and controlling the demodulation power consumption.
Based on the above embodiment, the functional module includes a plurality of functional units, and the functional units are clocked by different frequency division clock signals, and the different frequency division clock signals are obtained by performing a plurality of equal divisions on the preset frequency clock signal.
Specifically, as shown in fig. 1, the functional module 5 includes a plurality of functional units, each of which implements its own function, and the present invention includes 10 kinds of functional units, which are: shaping, decoding, data parsing, CRC, encoding, RNG, stctrl, timers, anti-collision, and EEPROM.
According to the invention, through power consumption control and function module enabling between the power consumption control module and the function module, flexible control of each function unit in the function module is realized, intelligent switching-off is carried out according to actual use requirements, and the whole power consumption of chip operation is effectively reduced.
Fig. 3 is a schematic flow chart of a power consumption control method for an RFID tag chip provided by the present invention, as shown in fig. 3, including:
step S1, the frequency dividing module receives a clock signal with a preset frequency and outputs the frequency dividing clock signal to the clock gating module;
step S2, the clock gating module receives the frequency division clock signal and the module gating enable signal sent by the power consumption control module, and sends a control instruction of the clock signal to the function module;
step S3, the controller receives the enabling signal sent by the clock gating module, and sends a function module enabling signal to the function module through the clock gating module;
in step S4, the functional module receives the module gating enable signal, the frequency-divided clock signal, and the functional module enable signal, and executes a preset function.
Specifically, as shown in fig. 1, the frequency dividing module 1 receives an input signal, which includes a clock signal with a frequency of 13.56MHz/s, performs frequency division processing on the clock signal, and outputs the clock signal to the clock gating module 2; the clock gating module 2 simultaneously receives the frequency division clock signal subjected to frequency division processing and the module gating enable signal sent by the power consumption control module 4, and then sends a corresponding control instruction for controlling the clock signal to the function module 5; meanwhile, the controller 3 receives the enable signal sent by the clock gating module 2 and returns a function module enable signal for controlling the function module 5 to the clock gating module 2; finally, the function module 5 receives the module gating enable signal, the frequency division clock signal and the function module enable signal, starts a corresponding function unit, and executes a corresponding function.
According to the invention, the power consumption control module is arranged in the RFID tag chip, the clock frequency of the operation of the control function module, the operation performance of the control function module and the demodulation power consumption are controlled, and the whole power consumption control of the chip is realized.
Based on the above embodiment, the module gating enable signal is obtained by logically combining the functional module enable signal, the internal signal of the functional module, and the internal state by the power consumption control module.
Specifically, the power consumption control module combines the function module enable output by the controller and the signal and state inside the function module, and adds combinational logic to generate a module gating enable signal, so as to control the clock of the function module, restrict the working time of the clock signal and reduce the running power consumption of the whole time of the module. Shaping, timer, EEPROM interface controller, random number and stctrl module are opened according to the enable control of controller, and the module clock is opened, and enable control closes, and the module clock is closed, realizes power consumption control, as shown in FIG. 2, includes:
the decoding gating enable 6 is controlled by the decoding enable, idle and decoding signals through combinational logic;
the data analysis gating enable 7 is controlled by a data valid signal and other signals through combinational logic;
the shaping gating enable 8 is controlled by the decoding enable;
the anti-collision gating enable 9 is effectively controlled by the anti-collision enable and an EOF (End Of Frame);
the EEPROM gate enable 10 is controlled by read-write enable;
the timer gating enable 11 is effectively controlled by a timer enable and SOF (Start OF Frame, beginning OF a file stream);
the random number gating enable 12 is controlled by a random number enable;
the encoding gating enable 13 is controlled by the encoding enable;
stctrl gating enable 14 is controlled by the stctrl _ go instruction;
the CRC gating enable 15 is controlled by the combination logic of the CRC enable signal and the data valid signal;
the demodulation enable 16 is controlled by the EEPROM configuration and the decode enable in combinational logic.
According to the invention, the enabling control logics of the plurality of functional units are arranged in the power consumption control module, so that the working states of different functional units are flexibly controlled, and further the power consumption is controlled.
Based on any of the above embodiments, the frequency dividing module receives a clock signal with a preset frequency and outputs the frequency divided clock signal to the clock gating module, including:
and equally dividing the preset frequency clock signal into a plurality of frequency division clock signals, and sending one of the frequency division clock signals to the clock gating module.
In particular, as shown in fig. 1, different functional units in the functional module 5 are controlled with different frequency-divided clock signals.
clk2 is a divide-by-two of the clock at 13.56MHz/s, clk4 is a divide-by-four of the clock at 13.56MHz/s, and clk8 is a divide-by-eight of the clock at 13.56 MHz/s. The clk8 clock used for shaping, decoding and data analysis is determined by protocol requirements and error tolerance, and the eight-frequency-division clock is used for reducing the running power consumption of the whole decoding without affecting the decoding correctness; the EEPROM interface control, the timer and the RNG also adopt an eight-frequency dividing clk8 clock, and when the modules do not need high frequency in operation, the clk8 clock is enough to complete the function, so that the clock frequency is reduced, and the operation power consumption is reduced; the CRC module, the anti-collision module and the stctrl module adopt clock signals of four frequency division, so that the clock frequencies are kept consistent with the clock frequency of the controller, the signal detection between the modules is more convenient, and the speed can be reduced, but because the modules perform more detailed clock control subsequently, the clock use frequency is very low, the proportion of the clock use frequency to the clock length is very small, so that the large power consumption difference cannot be generated by adopting the clock of four frequency division or eight frequency division, and the clock of four frequency division is uniformly adopted for operation portability; only the coding module adopts the frequency division by two, because the ISO 15693 protocol limits the lowest frequency, and because in the case of double subcarriers, there are subcarriers with frequency division of 14 and 16, the smallest common divisor of 2, namely the frequency division clock, is taken as the clock of the coding module.
The invention inputs different frequency division clock signals to different functional units by carrying out various frequency division processing on the input clock signals, operates and controls at lower clock frequency, and can effectively reduce the integral operation power consumption of the functional module.
Based on any of the above embodiments, the controller receiving an enable signal sent by the clock gating module, and sending a function module enable signal to the function module through the clock gating module includes:
and starting the functional unit in the functional module based on the functional module enabling signal to enable the functional unit to execute a preset function.
And closing the functional unit in the functional module based on the functional module enabling signal to enable the functional unit not to execute a preset function.
Optionally, since the controller is a control end of the whole system operation, the controller can control the operation of a certain function module to execute a specific function requirement, and when the function module is not required to operate, the module enable is turned off, the function module is turned off to operate, the clock gating module 2 turns off the clock signal to the module according to the enable signal, and power consumption when the module is not operated is reduced.
According to the invention, the controller controls the operation of the related modules according to the current functional requirements of the tag chip, and when the rest modules do not operate, the current power consumption is reduced by closing the rest modules without generating dynamic power consumption.
Based on any of the above embodiments, the function module receives the module gating enable signal, the frequency division clock signal, and the function module enable signal, and executes a preset function, which previously includes:
the power consumption control module generates a clock signal based on the effective signal and sends the clock signal to a corresponding functional unit in the functional module;
and the corresponding functional unit loads data for processing based on the clock signal, closes the clock signal, and loads and processes the data when the next effective signal is received.
Optionally, the data parsing in the functional module 5 of the present invention and the data clock processing of the CRC are processed according to fig. 4, when a valid signal arrives, a clock is generated, and the clock signal is turned off at the rest of the time; when the corresponding clock signal arrives, the inside of the functional module 5 loads data, generally 1 to 2 clock signals are needed, then the clock is closed to wait for the next valid signal with a valid flag, and the control of power consumption is realized through the more detailed control.
The power consumption control module controls the running functional module more carefully, so that the clock is started when the data is valid, the valid power consumption operation is achieved, the running functional module does not run in the rest time, and most of invalid time power consumption is reduced.
Based on any of the above embodiments, the function module receives the module gating enable signal, the frequency-divided clock signal, and the function module enable signal, and executes a preset function, and before that, the method further includes:
the power consumption control module generates a clock signal based on the start effective signal and sends the clock signal to a corresponding functional unit in the functional module;
and the corresponding functional unit loads data for processing based on the clock signal enabling working state signal, closes the clock signal, and loads and processes the data when a next effective starting signal is started.
Optionally, the decoding and timer in the functional module 5 of the present invention adopts a clock processing method as shown in fig. 5, and when detecting a start valid signal, a clock signal is given, and a module circuit can enable a valid state at this time to indicate that the module is working, the clock signal is running at this time, the state signal is turned off after the completion of the processing, the clock is stopped, a next valid start signal is waited for, and a next functional flow is performed, and the power consumption is also greatly reduced when the clock signal is only present when the module needs to work.
According to the invention, the power consumption control module is used for more finely controlling the running functional module, so that the clock is started when the power consumption control module is in a working state, thus the effective power consumption operation is achieved, the power consumption control module does not run in the rest time, and most of ineffective time power consumption is reduced.
Based on any embodiment above, still include:
and the controller controls all demodulation enabling and/or preset proportion demodulation enabling to turn on or turn off the demodulation power consumption enabling of the corresponding functional unit in the functional module.
Optionally, the invention also provides demodulation enable control so as to reduce the demodulation power consumption of the analog front end, wherein the related 100% demodulation enable and 10% demodulation enable are controlled by the decoding module or the EEPROM, and one of the 100% demodulation and the 10% demodulation can be controlled to be turned off through the modifiable EEPROM configuration, so that the analog front end can only work in one of the demodulation modes, and the other demodulation mode is turned off, thereby reducing the demodulation power consumption of the analog front end.
Here, if the EEPROM simultaneously turns on 100% demodulation and 10% demodulation, the controller 3 turns off 100% demodulation enable and 10% demodulation enable to reduce demodulation power consumption of the analog front end when turning off the decoding enable; when the controller 3 starts the decoding enable, the 100% demodulation enable and the 10% demodulation enable are firstly started, and when one of the 100% demodulation enable and the 10% demodulation enable decodes to a complete command, the other demodulation enable is closed, so that the power consumption consumed by the other demodulation is reduced until the next power-on reset.
The invention reduces the demodulation power consumption of the analog front end by controlling the demodulation enable, and reduces the whole power consumption of the chip.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (7)
1. A power consumption control method for an RFID tag chip is characterized by comprising the following steps:
the frequency division module receives a clock signal with a preset frequency and outputs the frequency division clock signal to the clock gating module;
the clock gating module receives the frequency division clock signal and a module gating enabling signal sent by the power consumption control module, and sends a control instruction of the clock signal to the function module;
the controller receives an enabling signal sent by the clock gating module and sends a functional module enabling signal to the functional module through the clock gating module;
the functional module receives the module gating enable signal, the frequency division clock signal and the functional module enable signal and executes a preset function;
the module gating enabling signal is obtained by logically combining the functional module enabling signal, the internal signal of the functional module and the internal state through the power consumption control module;
the controller receives an enable signal sent by the clock gating module, and sends a function module enable signal to the function module through the clock gating module, and the method comprises the following steps:
starting a functional unit in the functional module based on the functional module enabling signal to enable the functional unit to execute a preset function;
and closing the functional unit in the functional module based on the functional module enabling signal to enable the functional unit not to execute a preset function.
2. The power consumption control method of the RFID tag chip as claimed in claim 1, wherein the frequency dividing module receives a clock signal with a preset frequency and outputs the clock signal to the clock gating module, comprising:
and equally dividing the preset frequency clock signal into a plurality of frequency division clock signals, and sending one of the frequency division clock signals to the clock gating module.
3. The power consumption control method of the RFID tag chip according to claim 1, wherein the function module receives the module gating enable signal, the frequency division clock signal, and the function module enable signal, and performs a preset function, which previously includes:
the power consumption control module generates a clock signal based on the effective signal and sends the clock signal to a corresponding functional unit in the functional module;
and the corresponding functional unit loads data for processing based on the clock signal, closes the clock signal, and loads and processes the data when the next effective signal is received.
4. The power consumption control method of the RFID tag chip as claimed in claim 3, wherein the function module receives the module gating enable signal, the frequency-divided clock signal and the function module enable signal, and performs a preset function, and before further comprising:
the power consumption control module generates a clock signal based on the start effective signal and sends the clock signal to a corresponding functional unit in the functional module;
and the corresponding functional unit loads data for processing based on the clock signal enabling working state signal, closes the clock signal, and loads and processes the data when a next effective starting signal is started.
5. The power consumption control method of the RFID tag chip according to claim 1, further comprising:
and the controller controls all demodulation enabling and/or preset proportion demodulation enabling to turn on or turn off the demodulation power consumption enabling of the corresponding functional unit in the functional module.
6. An RFID tag chip for executing the RFID tag chip power consumption control method according to any one of claims 1 to 5, characterized by comprising: frequency division module, clock gate control module, controller, power consumption control module and functional module, wherein:
the frequency division module is used for receiving a clock signal with a preset frequency and outputting the frequency division clock signal to the clock gating module;
the clock gating module is used for receiving a module gating enabling signal sent by the power consumption control module and controlling the clock signal of the functional module to be turned on or turned off;
the controller is used for controlling the opening or closing of the functional module based on the functional module enabling signal;
the power consumption control module is used for logically combining the functional module enabling signal, the internal signal of the functional module and the internal state to output the module gating enabling signal, restricting the working time of the frequency division clock signal and controlling the working power consumption of the functional module;
the function module is used for executing a preset function based on the module gating enable signal, the frequency division clock signal and the function module enable signal.
7. The RFID tag chip of claim 6, wherein the functional module comprises a plurality of functional units clocked by different divided clock signals, the different divided clock signals being a plurality of equal divisions of the predetermined frequency clock signal.
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| US9397668B2 (en) * | 2014-12-18 | 2016-07-19 | Linear Technology Corporation | System and method for providing programmable synchronous output delay in a clock generation or distribution device |
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