CN102831092A

CN102831092A - Data signal synchronization circuit of universal serial bus (USB) full-speed device

Info

Publication number: CN102831092A
Application number: CN2011101591715A
Authority: CN
Inventors: 叶国平
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd
Priority date: 2011-06-14
Filing date: 2011-06-14
Publication date: 2012-12-19
Anticipated expiration: 2031-06-14
Also published as: CN102831092B

Abstract

The invention discloses a data signal synchronization circuit of a universal serial bus (USB) full-speed device and is characterized in that a high-frequency clock is used for synchronizing indicating signals in a K state and a search engine optimization (SEO) state; a two-stage D latch is adopted by a synchronization logic to eliminate the metastability problem of data signals; then, another D latch and a two-input AND gate are further used by the synchronization logic to eliminate error pulse signals which are sampled by the high-frequency clock falsely due to burrs on the indicating signals in the SEO state; and after the signals are synchronized, and the error pulses are eliminated, the indicating signals which are in the K state, the J state and the SEO state and are used by an internal logic for generating USB bus data signals are combined again. By adopting the data signal synchronization circuit of the USB full-speed device, the asynchronous data signals of the USB device suitable for a USB full-speed protocol can be synchronized, and the correctness of the signals after synchronization can be ensured.

Description

USB is the device data signal synchronization circuit at full speed

Technical field

The present invention relates to the interface field of PC (PC), particularly relate to a kind of USB device data signal synchronization circuit at full speed.

Background technology

USB (USB Universal Serial BUS) interface is to unite proposition by many companies such as Intel, Compaq, IBM, Microsoft the end of the year 1994, is an external bus standard with communication that is connected that is used for standard computer and external unit.

After delivering the USB initial version in 1994, USB interface has become the standard extension interface in the present computer.The USB interface transmission speed is fast, full speed equipment 12Mbps (12 megabit per second), low-speed device 1.5Mbps; Easy to use, the plug and play of support equipment and hot plug; In addition, also have and connect flexibly, advantage such as independently-powered.USB interface can connect nearly all external units such as mouse, keyboard, printer, scanner, camera, flash disk, MP3 machine, mobile phone, digital camera, portable hard drive, external smooth floppy drive, USB network interface card, ADSL Modem, Cable Modem.

USB full speed equipment adopts the interface of four lines, except two power leads with the ground wire, has only two single data signal wires to be used for the transmission of usb bus data.What therefore whole USB system adopted is asynchronous transmission mode, does not have the transmission of clock signal.This just requires when using the usb bus data, earlier it to be synchronized in the work clock territory of chip internal.Simultaneously since USB at full speed the sequential on the two single data signal wires of equipment is inconsistent, when usb bus data-signal synchronously, the signal distortion to some extent after can making synchronously, thereby insert some error pulse signals.For this reason, behind synchronous logic, also to add the circuit of removing error pulse signal.

Summary of the invention

The technical matters that the present invention will solve provides a kind of USB device data signal synchronization circuit at full speed, synchronously the correctness of the data signal bus of USB full speed equipment and assurance data signal bus.

For solving the problems of the technologies described above, USB of the present invention is the device data signal synchronization circuit at full speed, comprising:

SE0 condition indicative signal synchronizing circuit; Comprise first D-latch, second D-latch and the 3rd D-latch of serial connection successively; The synchronizing clock signals of the input end of clock input chip operation clock zone of said three D-latchs; The data output end of second D-latch and the 3rd D-latch is connected with the input end of door with one two input respectively; SE0 condition indicative signal synchronously inputs to the data input pin of first D-latch, the SE0 condition indicative signal after the output terminal output synchronously of two inputs and door;

K state or J condition indicative signal synchronizing circuit; Comprise 4 d latch, the 5th D-latch and the 6th D-latch of serial connection successively; The synchronizing clock signals of the input end of clock input chip operation clock zone of said three D-latchs; The data input pin that K state synchronously or J condition indicative signal input to 4 d latch, K state or J condition indicative signal after the data output end output synchronously of the 6th D-latch.

Adopt synchronizing circuit of the present invention, can eliminate the metastable state problem of usb bus data-signal, filter out error pulse signal; Guarantee K condition indicative signal or J condition indicative signal, consistent with SE0 condition indicative signal sequential; Therefore, the present invention can either make meet USB at full speed the asynchronous data signal of the USB device of agreement be synchronized the correctness of the usb bus data-signal after can guaranteeing synchronously again.

Description of drawings

Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:

Fig. 1 is USB four data signal bus oscillograms of device transmission at full speed;

Fig. 2 is a SE0 condition indicative signal synchronizing circuit schematic diagram;

Fig. 3 is a K condition indicative signal synchronizing circuit schematic diagram.

Embodiment

USB two single data signal wires of equipment at full speed is used to transmit four data signal bus, and is as shown in Figure 1, and the value of D+ and D-is 10 expression J states, 01 expression K state, 00 expression SE0 state, 11 expression SE1 states.Wherein, the J STA representation be data 1, the K STA representation be data 0; And the SE0 STA representation is the end signal of a usb data bag, and the SE1 state is a disarmed state, and does not allow in the usb data transmission, to use.

USB equipment is at full speed always begun by the K state, and constantly sends the bit stream of K STA representation data 0 or J STA representation data 1 when usb data bag of transmission, until data-signal finishes, sends the current usb data end-of-packet of SE0 STA representation.Therefore, only synchronously K state and SE0 condition indicative signal in an embodiment of the present invention, synchronous after, if the data signal bus state not at K state and SE0 state, that just can think to be in the J state.

SE0 condition indicative signal synchronizing circuit is as shown in Figure 2; Constitute with door by three D-latchs and one two input; D-latch D1 and D-latch D2 are used for synchronous SE0 condition indicative signal, and the serial connection of two-stage D-latch latchs and guaranteed that signal does not have the metastable state problem.But during owing to transmission usb data bag, data-signal is K state or J state always; And two single data signal wire D+ of USB full speed equipment and the sequential of D-are not in full accord; The time of signal upset can not keep at one time, and jagged existence certainly on the SE0 condition indicative signal before synchronously like this is after this burr is input to synchronizing circuit; Might be sampled by D-latch D1 and D-latch D2, thereby produce an error pulse signal.D-latch D3 in the synchronizing circuit and two inputs are used to remove this error pulse signal with a door AND1 exactly, see from circuit, and only under the output of D-latch D2 and D3 all was 1 situation, final SE0 condition indicative signal just was 1.Such circuit has guaranteed that in the output of D-latch D2 only the SE0 condition indicative signal greater than a synchronous clock clk cycle just can be considered to real effectively SE0 condition indicative signal, thereby has filtered the error pulse signal that is caused by burr.

Referring to shown in Figure 3; Owing to can jaggedly not occur on the K condition indicative signal; K condition indicative signal synchronizing circuit is made up of three D-latchs; D-latch D4 and D5 are used for the metastable state problem on synchronous K condition indicative signal and the clear signal, and after D-latch D6 was used for guaranteeing synchronously simultaneously, the K condition indicative signal was consistent with the sequential of SE0 condition indicative signal.

Can see that from above analysis owing to will remove error pulse signal, synchronizing circuit can filter out the deration of signal in a synchronous clock cycle; The problem of bringing is, even for normal SE0 condition indicative signal, and through after the processing of synchronizing circuit, also can be littler than original data-signal width.The width that this reduces is about a synchronous clock clk cycle of synchronizing circuit.The frequency of therefore said synchronizing circuit requirement synchronous clock CLK will be at more than four times of frequency data signal; So synchronous back SE0 condition indicative signal only can be lost 1/4th of a data signal bus bit wide; Therefore guarantee synchronizing circuit can normally sample K state and SE0 condition indicative signal, also can guarantee to pass through the not serious distortion of data-signal behind the whole synchronizing circuit.

Said synchronous clock CLK is high frequency clock, i.e. the chip operation clock zone.

Through behind the synchronizing circuit, obtained at the SE0 of chip operation clock zone condition indicative signal and K condition indicative signal, and under SE0 state and K condition indicative signal all were zero situation, the J condition indicative signal was " 1 " at this moment.Like this, the chip internal circuits needed has just produced at the state of all usb bus data-signals in inside chip work clock territory.

More than through embodiment the present invention has been carried out detailed explanation; But in practical implementation; Those skilled in the art can do suitable adjustment and variation under principle of the present invention; Such as the frequency of synchronizing circuit synchronous clock, the number of D-latch, the K state still is synchronous J state or the like synchronously.These adjustment also should be regarded as protection scope of the present invention.

Claims

1. a USB full speed device data signal synchronization circuit is characterized in that, comprising:

2. USB as claimed in claim 1 is the device data signal synchronization circuit at full speed, and it is characterized in that: the frequency of said synchronizing clock signals is more than four times of usb bus frequency data signal.

3. USB as claimed in claim 1 is the device data signal synchronization circuit at full speed, it is characterized in that: through after the synchronous processing, and the K state of combination results usb bus data-signal, J state and SE0 state again.