CN202533933U - I2C interface configuration circuit of programmable logic gate array and programmable logic gate array - Google Patents
I2C interface configuration circuit of programmable logic gate array and programmable logic gate array Download PDFInfo
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- CN202533933U CN202533933U CN201120455574XU CN201120455574U CN202533933U CN 202533933 U CN202533933 U CN 202533933U CN 201120455574X U CN201120455574X U CN 201120455574XU CN 201120455574 U CN201120455574 U CN 201120455574U CN 202533933 U CN202533933 U CN 202533933U
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Abstract
The utility model relates to an I2C interface configuration circuit of a programmable logic gate array comprising a slave computer, which can be used to convert a serial signal sent by an I2C master computer to a parallel signal, convert the parallel signal to the I2C bus serial signal, and then send the I2C bus serial signal to the I2C master computer; an I2C read-back unit, which can be used to convert the parallel signal converted by the I2C slave computer unit into an I2C configuration unit of configuration data flow, and convert the read-back data flow to the parallel data, and then send the parallel data to the slave computer unit. The I2C configuration unit and the I2C read-back unit are respectively connected between the slave computer unit and an FPGA configuration interface circuit. The parallel signal is an 8-bit parallel signal. The utility model also relates to a programmable logic gate array. The I2C interface configuration circuit of the programmable logic gate array and the programmable logic gate array provided in the utility model have advantages of low costs, easy integration, and no requirement of special configuration interfaces.
Description
Technical field
The utility model relates to programmable gate array, and (Field Programmable Gate Array FPGA), more particularly, relates to a kind of I of programmable gate array
2C interface configuration circuit and programmable gate array.
Background technology
The configuration mode of the FPGA device in field programmable gate array (FPGA) field mainly contains 5 kinds of patterns at present, i.e. serial interface mode, parallel interface pattern, boundary scan interface pattern, SPI interface modes, BPI interface modes etc.In consumer electronics, telecommunication and industrial electronic, often there are a lot of similar places most design the inside, and for example almost each system all comprises; Some intelligent controllers, the normally microcontroller of a monolithic; Universal circuit, for example lcd driver, remote I/O mouth, RAM, EEPROM or data converter or the like; Application oriented circuit, the for example digital tuning of radio and video system and signal processing circuit, or the DTMF generator of voice-frequency dialing phone etc.And these devices all have I usually
2The C communication interface.Simultaneously, generally also have programming device such as FPGA to participate in realizing the partial function in the electronic system.When other core component in the electronic system is configured the FPGA device or during the special control operation of system; Core component just must carry out the custom interface circuit module according to specialized configuration interface (general non-standard interface) sequential of FPGA, so that realize core component and the operation of FPGA aspect the configuration data communication.This interface caused problem that need to increase special-purpose configuration interface that do not match has increased device cost, gives that the device of electronic system is integrated to bring big difficulty, simultaneously also may consume electrons system board area.
The utility model content
The technical matters that the utility model will solve is; Occur when being used to above-mentioned FPGA device and other electronic systems or device because the cost that the configuration interface coupling causes increases, the integrated problem of difficulty; Propose that a kind of need not increase special-purpose configuration interface, cost low, more easy of integration, thereby eliminated the configuration circuit and the programmable gate array of the programmable gate array of configuration interface matching problem.
The utility model solves the technical scheme that its technical matters adopted: the I that constructs a kind of programmable gate array
2The C interface configuration circuit comprises the FPGA configuration interface circuit that is used to dispose said programmable gate array, also comprises appendent computer system, I
2C dispensing unit and I
2C retaking of a year or grade unit; Said configuration interface circuit comprises I
2C bus and with I
2The serial signal that the C bus is input to appendent computer system converts parallel signal into and is input to programmable gate array; Said appendent computer system is used for converting the parallel signal of the inner output of said programmable gate array into I
2C bus serial signal outputs to said I
2The C bus; Said I
2The C dispensing unit is used for the parallel signal that said appendent computer system is sent here is converted into data stream and is sent to said FPGA configuration interface circuit; Said I
2C retaking of a year or grade unit is used for the data stream of said FPGA configuration interface circuit output is converted into parallel data and outputs to said appendent computer system; Said I
2C dispensing unit and said I
2C retaking of a year or grade unit is connected between said appendent computer system and the said FPGA configuration interface circuit.
I at the described a kind of programmable gate array of the utility model
2In the C interface configuration circuit, said parallel signal is 8 bit parallel signals.
I at the described a kind of programmable gate array of the utility model
2In the C interface configuration circuit, said appendent computer system comprises 8 bit shift register, data receiver circuit, first shake hands generator, 8 word counters, state machine control circuit, data transmit circuit, second shake hands generator and clock generator; Said I
2The serial data of the data line of C bus input is successively through the generator output of shaking hands of said 8 bit shift register, said data receiver circuit and said first; Said 8 word counters are connected with said 8 bit shift register, and said state machine control circuit is connected with said clock generator with said first the shake hands generator, said 8 bit shift register respectively; Said I
2The data stream of C retaking of a year or grade unit output is successively through said second shake hands generator, said data transmit circuit and said 8 bit shift register and the said I
2The data line of C bus connects; Said clock generator also with said I
2The clock line of C bus connects.
I at the described a kind of programmable gate array of the utility model
2In the C interface configuration circuit, said I
2The C dispensing unit comprises the one 32 bit shift register, MUX, frame counter, synchronization character detecting device, I
2C data stream output circuit and handshake circuit; Wherein, said first shake hands the parallel signal of generator output successively through said the one 32 bit shift register, said MUX and said I
2C data stream output circuit outputs to the said configuration interface circuit of FPGA; Said I
2The output of C data stream output circuit also feeds back to an input end of said MUX; Said the one 32 bit shift register is also exported parallel data to said synchronization character detecting device, and said synchronization character detecting device output outputs to the control end of said MUX through said frame counter; Said handshake circuit outputs a control signal to said synchronization character detecting device and said I respectively
2C data stream output circuit.
I at the described a kind of programmable gate array of the utility model
2In the C interface configuration circuit, said I
2C retaking of a year or grade unit comprises 32 extracting registers, the 2 32 bit shift register, counter and synchronizers; The data stream of the said configuration interface circuit output of FPGA outputs to said second generator circuit of shaking hands through said 32 extracting registers and said the 2 32 bit shift register successively, and said counter outputs a control signal to said the 2 32 bit shift register; Said synchronizer is used to produce the retaking of a year or grade enable signal that makes said FPGA configuration interface circuit output stream.
The utility model also relates to a kind of programmable gate array, comprises configuration mode selection circuit and interface configuration circuit, and said configuration mode selection circuit comprises that being used for selection utilizes I
2The selecting side of the said programmable gate array of C bus configuration; Said interface configuration circuit is above-mentioned any described I
2The C interface configuration circuit.
Implement the I of the programmable gate array of the utility model
2C interface configuration circuit and programmable gate array have following beneficial effect: since increased in the interface configuration circuit of FPGA to FPGA be configured, the appendent computer system of retaking of a year or grade, I
2C dispensing unit and I
2C retaking of a year or grade unit makes FPGA can use I
2The C bus is carried out data configuration and data readback; And I
2The C bus all has existence at numerous microprocessor devices (CPU) and on-chip system device (SoC); Therefore; When FPGA and other electronic systems or device are used, just no longer have the problem of configuration interface coupling, it does not need special-purpose configuration interface, cost low, more easy of integration.
Description of drawings
Fig. 1 is the I of the utility model programmable gate array
2I among C interface configuration circuit and the programmable gate array embodiment
2The structural representation of C interface configuration circuit;
Fig. 2 is an appendent computer system structural representation among the said embodiment;
Fig. 3 is I among the said embodiment
2The structural representation of C dispensing unit;
Fig. 4 is I among the said embodiment
2The structural representation of C retaking of a year or grade unit;
Fig. 5 is the process flow diagram of collocation method among the said embodiment;
Fig. 6 is the process flow diagram of read-back approach among the said embodiment;
Fig. 7 is the constitutional diagram of state machine control circuit among Fig. 2.
Embodiment
To combine accompanying drawing that the utility model embodiment is described further below.
Fig. 1 is the I of programmable gate array in the present embodiment
2C interface configuration circuit structural representation, in Fig. 1, I
2The C interface configuration circuit comprises FPGA configuration interface circuit 4, appendent computer system 1, I
2 C dispensing unit 2 and I
2C retaking of a year or grade unit 3; Wherein, FPGA configuration interface circuit 4 is used to dispose this programmable gate array, and this FPGA configuration interface circuit 4 is identical with general, existing FPGA configuration interface circuit; Appendent computer system 1 is used for by programmable gate array and the outside I that is connected
2The serial signal of importing on the C bus converts parallel signal output into or converts the inner parallel signal of exporting of programmable gate array into I
2C bus serial signal outputs to said I
2On the C bus; I
2 C dispensing unit 2 is used for the parallel signal that appendent computer system 1 is sent here is converted into data stream and is sent to FPGA configuration interface circuit 4; I
2C retaking of a year or grade unit 3 converts the data stream of FPGA configuration interface circuit 4 outputs parallel data into and outputs to appendent computer system 1; In the present embodiment, above-mentioned I
2 C dispensing unit 2 and I
2C retaking of a year or grade unit 3 is connected between appendent computer system 1 and the FPGA configuration interface circuit 4; Simultaneously, in the present embodiment, above-mentioned parallel signal is 8 parallel signals that word is wide.
Fig. 2 is the I of programmable gate array in the present embodiment
2The structural representation of appendent computer system 1 in the C interface configuration circuit.In Fig. 2, appendent computer system 1 comprises 8 bit shift register, data receiver circuit, first shake hands generator, 8 word counters, state machine control circuit, data transmit circuit, second shake hands generator and clock generator; In the present embodiment, by above-mentioned I
2The serial data of the data line of C bus input is successively through the generator output of shaking hands of above-mentioned 8 bit shift register, data receiver circuit and first; 8 word counters are connected with 8 bit shift register, and the state machine control circuit is connected with clock generator with first the shake hands generator, 8 bit shift register respectively; I
2The data stream of C retaking of a year or grade unit 3 output is successively through second shake hands generator, data transmit circuit and 8 bit shift register and the said I
2The data line of C bus connects; Clock generator also with said I
2The clock line of C bus connects.
In the present embodiment, when above-mentioned appendent computer system 1 is handled the FPGA external data (normally when FPGA is configured), its signal flow is: external circuit sends serial data sda_i (see figure 2) to slave; Slave receives data and is saved in 8 bit shift register (shift_reg); 8 word counters are counted the data in the above-mentioned register, and the data with 8 bit shift register after every meter eight numbers send to data receiver circuit (rxr); The Gao Qiwei that data receiver circuit (rxr) detects first byte of data is local address (whether the transmission address of detecting main frame is consistent with the address of this machine); Then produce response bit in this way and give main frame (external circuit); Continue to send data, otherwise do not produce response bit; After the matching addresses, main frame continues to send data; Simultaneously, export eight bit parallel data through first generator of shaking hands through the RAM_DI port; State machine control circuit (FSM controller) control first receives shakes hands generator (Hand_Shacker_Generator), 8 bit shift register (shift_reg) according to I
2C communication protocol, the control each several part is by the agreement co-ordination.
When above-mentioned appendent computer system 1 is handled FPGA inside output data (normally when FPGA is carried out data readback), its signal flow is: receive data readback circuit 3 (I
2C_RB) the eight bit parallel data DATA_I that send are input to second generator of shaking hands by the RAM_DO port; After data transmit circuit (txr) receives first byte of RAM_DO, the high seven bit data RAM_DO [7:1] that detect RAM_DO whether with this machine matching addresses, then continue to receive the data that RAM_DO sends like coupling; When slave addresses position that data transmit circuit detects effectively after, data that generator begins to send RAM_DO that second shakes hands are in 8 bit shift register (shift_reg), 8 digit counters begin counting; Every meter one number of counter, port sda_o (referring to Fig. 2) then exports the one digit number certificate of a serial, when the RAM_DO data sent out after eight numbers more next by 8 digit counter meters; State machine control circuit (FSM controller) control second handshake circuit (Hand_Shacker_Generator), 8 bit shift register circuit (shift_reg) co-ordinations also make clock generator generation slave clock signal output to the scl_o port.
Fig. 3 is I in the present embodiment
2The structural representation of C dispensing unit 2.Said I
2The C dispensing unit comprises the one 32 bit shift register, MUX, frame counter, synchronization character detecting device, I
2C data stream output circuit and handshake circuit; Wherein, first shake hands the parallel signal of generator output successively through the one 32 bit shift register, MUX and I
2C data stream output circuit outputs to FPGA configuration interface circuit 4; I
2The output of C data stream output circuit also feeds back to an input end of MUX; The one 32 bit shift register is also exported parallel data to the synchronization character detecting device, and the output of synchronization character detecting device outputs a control signal to the control end of MUX through frame counter; Handshake circuit outputs a control signal to synchronization character detecting device and I respectively
2C data stream output circuit.
In the present embodiment, above-mentioned I
2Signal flow in the C dispensing unit 2 is following: receive eight bit parallel data to DATA_O port (referring to Fig. 3); Eight bit parallel data are moved into (shift_reg [31:0]) in the one 32 bit shift register; Synchronization character testing circuit (synchronize words detect) detects the one 32 bit shift register and writes full back (sending four parallel datas of eight knows for writing full scale) startup frame counter (frame_counter), and this frame counter is used for counting has sent out for how many frame data; Behind the frame counter counting, be that 32 frame data stream sends to I with data
2C frame data stream output circuit (I
2C_bitstream out); I
2C frame data stream output circuit sends to 32 frame data stream in the FPGA configuration interface circuit 4 (CCS) after receiving handshake circuit (HandShake) enable signal load_i2cbit.
Fig. 4 is I in the present embodiment
2The structural representation of C retaking of a year or grade unit 3.I
2C retaking of a year or grade unit 3 comprises 32 extracting registers, the 2 32 bit shift register, counter and synchronizers; The data stream of FPGA configuration interface circuit 4 output outputs to second generator of shaking hands through 32 extracting registers and the 2 32 bit shift register successively, and counter outputs a control signal to the 2 32 bit shift register; Synchronizer is used to produce the retaking of a year or grade enable signal of the data stream that makes 4 outputs of FPGA configuration interface circuit.
In the present embodiment, above-mentioned I
2Signal flow in the C retaking of a year or grade unit 3 is following: I
2C retaking of a year or grade circuit sends it back read signal (rb_idt is sent by main frame) and gives FPGA configuration interface circuit 4 (CCS shows like Fig. 4); Synchronizer (synchronizer) sends I after receiving read back waveform
2C retaking of a year or grade enable signal (I
2C_fb); FPGA configuration interface circuit 4 receives I
2C retaking of a year or grade enable signal is after data bus (data line of DATABUS FPGA internal configuration circuitry) sends configuration data stream; 32 extracting registers (capture_reg) send to the 2 32 bit shift register (shift_reg [31:0]) after grasping 32 configuration data streams on the bus; Send Data Update signal (update) after every meter eight numbers of counter (counter) and give the 2 32 bit shift register 3shift_reg [31:0]); It is that a byte is by its DATA_I port output by eight that the 2 32 bit shift register receives after data (being produced by the counter circuit) update signal 32 configuration data flow datas.
In the present embodiment, appendent computer system is mainly carried out FPGA and data transfer is carried out in the outside.Its internal state machine such as Fig. 7 show; Receive reset signal rst slave is placed dummy status slave_idle; The commencing signal start_s that receives the main frame transmission starts slave initial state slave_start and judges: not matching as if the addressing address with main frame does not then get into next state; If then get into slave responsive state slave_ack with the addressing matching addresses of main frame; If writing that receive this moment enables w_r for high, then slave continues to send data when the outside is sent Data Receiving to the external echo position, otherwise jumps to state sky and initial state.It is low enabling w_r as if writing of reception, and then slave receives external data and when receiving the external echo position, continues the reception data, otherwise jumps to state sky and initial state.
Present embodiment also relates to a kind of collocation method of programmable gate array.In the present embodiment, this collocation method comprises collocation method and read-back approach.Its flow process is as shown in Figure 5, comprises the steps:
Step S11 selects to use I
2C bus configuration pattern: in the present embodiment,, that is to say because FPGA also kept existing data configuration mode, this FPGA and existing FPGA comparatively speaking, many a kind of configuration modes.So, in this step, need select configuration mode, make this FPGA adopt I
2C bus configuration pattern.Since have five kinds of main configuration modes of FPGA now by three configured port M2, M1, and M0 is configured.Therefore, in the present embodiment, newly-increased configured port M3 selects I
2C bus configuration pattern, can set M3M2M1M0=1000 is FPGA configuration I
2The configuration mode of C.
Step S12 works as I
2After C bus configuration pattern is selected, appendent computer system will be enabled, and slave is in the Idle state and prepares receiver address.
Step S13 receives serial data and is stored in 8 bit shift register: in this step, external circuit (main frame) passes through I
2The C bus is sent configuration data, and slave is stored in the data of above-mentioned serial in 8 bit shift register successively.
Step S14 slave addresses coupling; In this step, whether mate with this slave addresses the address of detecting the external circuit transmission, then produces response bit like coupling and give main frame; Main frame continues to send serial data, and programmable gate array configuration (retaking of a year or grade) circuit then continues to carry out next step; Otherwise, jump to step S12.
Step S15 receives 8 bit parallel signals and is stored in 32 bit shift register: the matching addresses aft engine can continue to send data to slave among the S14, and slave receives serial data, and converts 8 bit parallel data into, sends to I to parallel data
2The C dispensing unit, I
2The 8 bit parallel signals that the C dispensing unit will receive are written in 32 bit shift register successively.
Whether step S16 32 bit shift register are full, judge that above-mentioned 32 bit shift register write full? In this way, carry out next step, otherwise, return S15 and continue to accept 8 bit parallel data, wait for that this 32 bit shift register writes full.
Step S17 output frame is to programmable gate array configuration interface circuit: in this step, with writing data in the 32 full bit shift register as a frame, output to programmable gate array configuration interface circuit.Frame is the least unit of FPGA data stream, generally comprises several words (word), and its length depends on the size of configuration frame length register data.Above-mentioned frame is transferred to the processing mode behind the programmable gate array configuration interface circuit, and is just similar or identical with existing FPGA configuration.
Step S18 withdraws from
In the present embodiment; Above-mentioned steps S12-S14 has accomplished the process that serial data is converted into 8 bit parallel data; It is the process of FPGA configuration data stream commonly used that step S15-S17 has then accomplished above-mentioned 8 bit parallel data-switching, makes configuration be able on existing basis, carry out.
In the present embodiment, as shown in Figure 6 by the method flow of programmable gate array retaking of a year or grade data, comprise the steps:
Step S21 produces and sends I after receiving read back waveform
2C retaking of a year or grade enable signal: in this step; External circuit (main frame) sends it back read signal (rb_idt) to programmable gate array configuration (retaking of a year or grade) circuit, and programmable gate array configuration (retaking of a year or grade) circuit produces and send I after receiving read back waveform through a synchronizer (synchronizer)
2C retaking of a year or grade enable signal.
Step S22 sends it back read data, and is stored in 32 bit shift register: FPGA configuration interface circuit receives above-mentioned I
2C retaking of a year or grade enable signal is after data bus (data line of DATABUS FPGA internal configuration circuitry) sends it back time data stream; This step is exactly after grasping 32 configuration data streams on the above-mentioned bus, to send it to the storage of 32 bit shift register.
Per 8 of the data of step S23 32 bit shift register send to I
2The C appendent computer system: in this step, counter (counter) sends Data Update signal (update) and gives above-mentioned 32 bit shift register circuit the above-mentioned data counts that is input in 32 bit shift register after every meter eight numbers; It is that a byte is exported to I by 8 that above-mentioned 32 bit shift register receive behind the Data Update signal (being produced by counter circuit) 32 retaking of a year or grade data flow data
2The C appendent computer system.
Step S24 appendent computer system receives 8 bit parallel signals and is stored in 8 bit shift register: in this step, begin 8 bit data among the S23 are sent in the wide shift register (shift_reg) of 8 words, unison counter begins counting.
Step S25 is output as serial data by turn with rolling counters forward: in this step, every meter one number of counter is then exported the one digit number certificate of a serial.When 8 bit parallel data sent out after eight numbers more next by the counter meter.
Step S26 withdraws from
In the present embodiment, above-mentioned steps S21-S23 has accomplished the process that the retaking of a year or grade data stream is converted into 8 bit parallel data, and it is the I of serial that step S24-S26 has then accomplished above-mentioned 8 bit parallel data-switching
2The process of C bus data makes the retaking of a year or grade data be able at I
2Export on the C bus.
Present embodiment also relates to a kind of programmable gate array, comprises configuration mode selection circuit and configuration circuit, and its configuration mode selection circuit comprises that being used for selection utilizes I
2The selecting side of the said programmable gate array of C bus configuration; Newly-increased configured port M3 selects I on the basis of existing configuration mode selection circuit
2C bus configuration pattern, can set M3, M2, M1, M0}={1,0,0,0} is FPGA configuration I
2The configuration mode of C; Its configuration circuit be above the I of described programmable gate array
2The C interface configuration circuit.
In a word, in general electronic system (not having PC), core devices such as microprocessor need not the time sequential routine custom configuration communication interface according to FPGA specialized configuration interface, just can be configured and the retaking of a year or grade communication with FPGA easily, especially pass through I
2C interface downloads specialized configuration stream, by the overall control action of FPGA configuration-system to the full chip of FPGA; Thereby the FPGA device is implemented the operations such as special use control of the overall situation; Such as all input/output terminal IO of control FPGA device be in high-impedance state, with the trigger set-reset in the FPGA device etc., this makes and adopts this structure FPGA not need special-purpose configuration interface, cost low, more easy of integration.
The above embodiment has only expressed several kinds of embodiments of the utility model, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model claim.Should be pointed out that for the person of ordinary skill of the art under the prerequisite that does not break away from the utility model design, can also make some distortion and improvement, these all belong to the protection domain of the utility model.Therefore, the protection domain of the utility model patent should be as the criterion with accompanying claims.
Claims (6)
1. the I of a programmable gate array
2The C interface configuration circuit comprises the FPGA configuration interface circuit that is used to dispose said programmable gate array, it is characterized in that, also comprises appendent computer system, I
2C dispensing unit and I
2C retaking of a year or grade unit; Said configuration interface circuit comprises I
2C bus and with I
2The serial signal that the C bus is input to appendent computer system converts parallel signal into and is input to programmable gate array; Said appendent computer system is used for converting the parallel signal of the inner output of said programmable gate array into I
2C bus serial signal outputs to said I
2The C bus; Said I
2The C dispensing unit is used for the parallel signal that said appendent computer system is sent here is converted into data stream and is sent to said FPGA configuration interface circuit; Said I
2C retaking of a year or grade unit is used for the data stream of said FPGA configuration interface circuit output is converted into parallel data and outputs to said appendent computer system; Said I
2C dispensing unit and said I
2C retaking of a year or grade unit is connected between said appendent computer system and the said FPGA configuration interface circuit.
2. according to the I of the described programmable gate array of claim 1
2The C interface configuration circuit is characterized in that, said parallel signal is 8 bit parallel signals.
3. the I of programmable gate array according to claim 2
2The C interface configuration circuit is characterized in that, said appendent computer system comprises 8 bit shift register, data receiver circuit, first shake hands generator, 8 word counters, state machine control circuit, data transmit circuit, second shake hands generator and clock generator; Said I
2The serial data of the data line of C bus input is successively through the generator output of shaking hands of said 8 bit shift register, said data receiver circuit and said first; Said 8 word counters are connected with said 8 bit shift register, and said state machine control circuit is connected with said clock generator with said first the shake hands generator, said 8 bit shift register respectively; Said I
2The data stream of C retaking of a year or grade unit output is successively through said second shake hands generator, said data transmit circuit and said 8 bit shift register and the said I
2The data line of C bus connects; Said clock generator also with said I
2The clock line of C bus connects.
4. the I of programmable gate array according to claim 3
2The C interface configuration circuit is characterized in that, said I
2The C dispensing unit comprises the one 32 bit shift register, MUX, frame counter, synchronization character detecting device, I
2C data stream output circuit and handshake circuit; Wherein, said first shake hands the parallel signal of generator output successively through said the one 32 bit shift register, said MUX and said I
2C data stream output circuit outputs to the said configuration interface circuit of FPGA; Said I
2The output of C data stream output circuit also feeds back to an input end of said MUX; Said the one 32 bit shift register is also exported parallel data to said synchronization character detecting device, and said synchronization character detecting device output outputs to the control end of said MUX through said frame counter; Said handshake circuit outputs a control signal to said synchronization character detecting device and said I respectively
2C data stream output circuit.
5. the I of programmable gate array according to claim 4
2The C interface configuration circuit is characterized in that, said I
2C retaking of a year or grade unit comprises 32 extracting registers, the 2 32 bit shift register, counter and synchronizers; The data stream of the said configuration interface circuit output of FPGA outputs to said second generator circuit of shaking hands through said 32 extracting registers and said the 2 32 bit shift register successively, and said counter outputs a control signal to said the 2 32 bit shift register; Said synchronizer is used to produce the retaking of a year or grade enable signal that makes said FPGA configuration interface circuit output stream.
6. a programmable gate array comprises configuration mode selection circuit and interface configuration circuit, it is characterized in that, said configuration mode selection circuit comprises that being used for selection utilizes I
2The selecting side of the said programmable gate array of C bus configuration; Said interface configuration circuit is like any described I of claim 1-4
2The C interface configuration circuit.
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| CN201120455574XU CN202533933U (en) | 2011-11-16 | 2011-11-16 | I2C interface configuration circuit of programmable logic gate array and programmable logic gate array |
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| CN201120455574XU CN202533933U (en) | 2011-11-16 | 2011-11-16 | I2C interface configuration circuit of programmable logic gate array and programmable logic gate array |
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| CN103150952A (en) * | 2013-03-12 | 2013-06-12 | 广西生态工程职业技术学院 | Reconfigurable electronic design automation (EDA) experimental platform |
| CN105187899A (en) * | 2015-07-22 | 2015-12-23 | 深圳市特博赛科技有限公司 | Data transmission system |
| CN105718396B (en) * | 2016-01-21 | 2018-05-29 | 哈尔滨理工大学 | A kind of I of big data master transmissions2C bus units and its means of communication |
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| CN110851386A (en) * | 2019-10-24 | 2020-02-28 | 深圳市信锐网科技术有限公司 | Interface configuration equipment |
| CN111123792A (en) * | 2019-12-29 | 2020-05-08 | 苏州浪潮智能科技有限公司 | Multi-main-system interactive communication and management method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103150952A (en) * | 2013-03-12 | 2013-06-12 | 广西生态工程职业技术学院 | Reconfigurable electronic design automation (EDA) experimental platform |
| CN103150952B (en) * | 2013-03-12 | 2015-06-17 | 广西生态工程职业技术学院 | Reconfigurable electronic design automation (EDA) experimental platform |
| CN105187899A (en) * | 2015-07-22 | 2015-12-23 | 深圳市特博赛科技有限公司 | Data transmission system |
| CN105187899B (en) * | 2015-07-22 | 2018-06-29 | 深圳市特博赛科技有限公司 | Data transmission system |
| CN105718396B (en) * | 2016-01-21 | 2018-05-29 | 哈尔滨理工大学 | A kind of I of big data master transmissions2C bus units and its means of communication |
| CN110362524A (en) * | 2018-04-11 | 2019-10-22 | 杭州海康威视数字技术股份有限公司 | Timing signal generating method, device, logic card and storage medium |
| CN110362524B (en) * | 2018-04-11 | 2021-04-09 | 杭州海康威视数字技术股份有限公司 | Time sequence signal generation method and device, logic circuit board and storage medium |
| CN110851386A (en) * | 2019-10-24 | 2020-02-28 | 深圳市信锐网科技术有限公司 | Interface configuration equipment |
| CN110851386B (en) * | 2019-10-24 | 2021-05-04 | 深圳市信锐网科技术有限公司 | Interface configuration equipment |
| CN111123792A (en) * | 2019-12-29 | 2020-05-08 | 苏州浪潮智能科技有限公司 | Multi-main-system interactive communication and management method and device |
| CN111123792B (en) * | 2019-12-29 | 2021-07-02 | 苏州浪潮智能科技有限公司 | Multi-main-system interactive communication and management method and device |
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