CN103077142A - Simple communication method of bus transmission protocols - Google Patents
Simple communication method of bus transmission protocols Download PDFInfo
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- CN103077142A CN103077142A CN2012105798413A CN201210579841A CN103077142A CN 103077142 A CN103077142 A CN 103077142A CN 2012105798413 A CN2012105798413 A CN 2012105798413A CN 201210579841 A CN201210579841 A CN 201210579841A CN 103077142 A CN103077142 A CN 103077142A
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Abstract
The invention discloses a simple communication method of bus transmission protocols and relates to a transmission protocol for carrying out communication between a host computer and a slave computer in the communication field. A set of bus transmission protocols meeting the special application requirements is designed by the method in the existing relevant standard and design in the communication field. A bus consists of a chip selection enabling wire, a clock transmission wire and a two-way data transmission wire, and the advantages that the low bit is wide, the data synchronism is good, the transmission speed is high, simplicity is realized, and the use is easy are realized. When being applied, the method has the advantages that the higher transmission rate can be reached by using the less bus bit width, and the application requirements of special occasions are met.
Description
Technical field
The present invention relates in the SOC (system on a chip) communications field a kind of easy bus transfer agreement that main frame and slave communicate.
Background technology
In the SOC (system on a chip) field, the factor that communicating by letter between main frame and the slave need to be considered is a lot, such as bus bit wide, speed, realization complexity etc.For the deviser with, how to obtain a kind of high rate data transmission bus that is simple and easy to usefulness and consider emphatically at the design initial stage.
Summary of the invention
Technical matters to be solved by this invention is exactly how to realize the register read write operation of high speed between main frame and the slave.The invention provides a kind of by main frame initiate, the slave response, the bus transfer agreement of low-bit width, two-forty.The transfer clock of this host-host protocol is initiated by main frame, and slave is corresponding, and transfer rate is high, and this host-host protocol design complexities is lower, is easy to realize, is convenient to expansion, has guaranteed wider range of application.
The object of the present invention is achieved like this, and a kind of communication means of easy bus transfer agreement is applicable to the register read write operation between main frame, the slave, it is characterized in that may further comprise the steps:
1. this transfer bus is comprised of 3 signal wires, respectively that sheet selects enable line, clock transfer line, bidirectional data transfers line, sheet select enable line and bidirectional data transfers line reset after the acquiescence state be high level, the clock transfer line reset after the acquiescence state be low level;
When 2. this transfer bus transmits, at first drag down sheet by main frame and select enable line; Slave detect sheet select enable line be low after, the inner enabling signal that produces;
3. main frame drags down sheet and selects after the enable line, produces bus clock, and by the clock transfer line with clock transfer to slave; Bus clock can be the frequency-dividing clock of the inner high frequency clock of main frame, and frequency dividing ratio can be arbitrary value;
4. main frame sends data by data line, and data can be a plurality of bytes; At first send the high position of current byte, big-endian sends successively, and the variation of bidirectional data transfers line is positioned at the negative edge of clock;
5. slave begins data are sampled at the rising edge of bus clock, and carries out read-write operation according to the data of collecting;
6. the main frame the transmission of data complete after, stop bus clock and just produce, draw high sheet and select enable line, finish this time transmission.
Wherein, the main frame that 3., 4. step is described sends data and clock, the each data transmission of initiating of main frame, always take transfer clock cycle of fixed numbers as one group, when one group of clock period less than that slave receives, give up the data of last transmission; The data transmission of step in 6. is complete, the minimum transfer clock cycle that comprises two groups of fixed numbers.
Wherein, the frequency-dividing clock that the main frame of step in 3. produces, frequency dividing ratio comprises 1 frequency division, namely transfer clock and main frame internal clocking are with frequency, the highest mxm. that can reach the circuit interface frequency.
Wherein, step 4. middle main frame sends data by data line, comprises write operation and read operation, is specially:
When main frame need to carry out write operation to slave, the first byte that at first needs to send adds " slave start address " for " write and enable 1 ", second byte is for writing the data of " slave start address ", the 3rd byte is for writing the data of " slave start address+1 ", by that analogy, N byte is for writing the data of " slave start address+N-2 "; Wherein, N is the number of byte;
When main frame need to carry out read operation to slave, the first byte that at first needs to send adds " slave start address " for " reading to enable 0 ", main frame gives slave to control on the bidirectional data transfers line afterwards, and main frame only need to produce transfer clock, and slave carries out sending of data by this transfer clock; After main frame sends the order of reading, because slave needs to parse the instruction time after receiving order, need byte time of time-delay, at the 3rd byte time with the data transmission of " slave start address " to main frame, the 4th byte time with the data transmission of " slave start address+1 " to main frame, by that analogy, during N byte, the data for " slave start address+N-3 " that main frame is read by the bidirectional data transfers line; Wherein, transfer clock that byte time is fixed numbers.
The present invention compares with background technology, has following advantage:
(1) bus bit wide of the present invention only has 3, satisfies the different directions requirement of read-write by the bidirectional data transfers line.
(2) bus transfer clock of the present invention can be frequently same with the main frame internal clocking, and transfer rate is higher.
(3) the present invention can only send start address one time by the requirement in the agreement, and read-write operation afterwards is all cumulative on this start address basis, thereby has reduced the transmission time of address, has increased the efficient of bus transfer.
(4) agreement of the present invention is simple, and easy to understand is workable, can carry out the adjustment of byte bit wide according to concrete register bit wide.
Description of drawings
Fig. 1 is three bus transfer agreement skeleton diagrams of the present invention.
To select enable line be 100 to sheet among Fig. 1, and the clock transfer line is 200, and the bidirectional data transfers line is 300.The transmission first byte is that 310, the second bytes are that 320, the three bytes are 330.Start bit enables 311 for read-write in the first byte, and more data bit is start address 312.
Fig. 2 is three bus transfer agreement first byte transmission synoptic diagram of the present invention.
To select enable line be 100 to sheet among Fig. 2, and the clock transfer line is 200, and the bidirectional data transfers line is 300.Rising edge clock is 210.The first byte of data line transmission is high-order for read-write enables 310, all the other seven the common start addresses 320 that form.
Fig. 3 is three bus transfer agreement invalid data key diagrams of the present invention.Bus transfer is always with 8 clock period, namely complete bytes mode carry out clock generating, data transmission, read.Clock upset when 8 clock period of less than are arranged directly abandons.
Fig. 4 is that three bus transfer protocol hosts of the present invention are write the slave process flow diagram.To select enable line be 100 to sheet among Fig. 4, and the bidirectional data transfers line is 300.First byte is 310, second transmission byte 320 is for writing the data of start address, the 3rd transmission byte 330 adds one data for writing start address, the 3rd transmission byte 340 adds two data for writing start address, and N transmits byte 350 is the data that write start address+(N-2).First byte is high-order to enable 311 for writing, and the first byte low level is start address 312.
Fig. 5 is that three bus transfer protocol hosts of the present invention are read slave buffer status process flow diagram.To select enable line be 100 to sheet among Fig. 5, and the bidirectional data transfers line is 300.First byte is 310, second transmission byte 320 is idling cycle, the 3rd transmission byte 330 is the initial buffer status value of reading the address, the 4th transmission byte 340 adds 1 buffer status value for the initial address of reading, and N transmits byte 350 is the initial buffer status value of reading address+(N-3).First byte is high-order for reading to enable 311, and low seven of first byte is the initial address 312 of reading.Second transmission byte 320 changes for the transmission direction that is used for the bidirectional data transfers line between main frame, the slave.
Fig. 6 is that three bus transfer agreement slaves of the present invention are resolved main frame write operation schematic diagram.Idle condition is A, main frame drags down the sheet choosing and is A1, it is B that slave carries out data sampling, the first byte of principal and subordinate's transmission is C, and the high-order determining device of first byte is C1, and opening and writing enable operation is D, it is E that slave carries out the rising edge clock sampling operation, it is E1 that sheet is elected high determining device as, and it is E2 that byte is collected complete determining device, writes current one-over-one address and is operating as E3.
Fig. 7 is that three bus transfer agreement slaves of the present invention are resolved main frame read operation schematic diagram.Idle condition is A, the sheet choosing drags down and is A1, it is B that slave carries out data sampling, the first byte of principal and subordinate's transmission is C, the high-order determining device of first byte is C1, and opening and reading enable operation is G, waits for that a byte time is H, it is H1 that sheet is elected high determining device as, and the buffer status that sends current one-over-one address is operating as I.
Embodiment is as follows:
1. this transfer bus is comprised of 3 signal wires, respectively that sheet selects enable line, clock transfer line, bidirectional data transfers line, sheet select enable line and bidirectional data transfers line reset after the acquiescence state be high level, the clock transfer line reset after the acquiescence state be low level;
To accompanying drawing 5, sheet selects that enable line is 100, the clock transfer line is 200, the bidirectional data transfers line is 300 with reference to accompanying drawing 1;
When 2. this transfer bus transmits, at first drag down sheet by main frame and select enable line; Slave detect sheet select enable line be low after, the inner enabling signal that produces;
3. main frame drags down sheet and selects after the enable line, produces bus clock, and by the clock transfer line with clock transfer to slave; Bus clock can be the frequency-dividing clock of the inner high frequency clock of main frame, and frequency dividing ratio can be arbitrary value;
4. main frame sends data by data line, and data can be a plurality of bytes; At first send the high position of current byte, big-endian sends successively, and the variation of bidirectional data transfers line is positioned at the negative edge of clock, namely is positioned at the rising edge of clock the stationary phase of data;
With reference to Fig. 2, the stable sampling period of bidirectional data transfers line 300, be positioned at the rising edge 210 of clock;
Wherein, main frame sends data by data line, comprises write operation and read operation, is specially:
When main frame need to carry out write operation to slave, the first byte that at first needs to send adds " slave start address " for " write and enable 1 ", second byte is for writing the data of " slave start address ", the 3rd byte is for writing the data of " slave start address+1 ", by that analogy, N byte is for writing the data of " slave start address+N-2 "; Wherein, N is the number of byte;
With reference to Fig. 4, when main frame need to carry out write operation to slave, the first byte 310 that at first needs to send added " the initial write address 312 of slave " for " write and enable 311 "; Second byte 320 is for writing the data of " slave start address "; The 3rd byte 330 is for writing the data of " slave start address+1 "; By that analogy, N byte is for writing the data of " slave start address+(N-2) ";
When main frame need to carry out read operation to slave, the first byte that at first needs to send adds " slave start address " for " reading to enable 0 ", main frame gives slave to control on the bidirectional data transfers line afterwards, and main frame only need to produce transfer clock, and slave carries out sending of data by this transfer clock; After main frame sends the order of reading, because slave needs to parse the instruction time after receiving order, need byte time of time-delay, at the 3rd byte time with the data transmission of " slave start address " to main frame, the 4th byte time with the data transmission of " slave start address+1 " to main frame, by that analogy, during N byte, the data for " slave start address+N-3 " that main frame is read by the bidirectional data transfers line; Wherein, transfer clock that byte time is fixed numbers;
With reference to Fig. 5, when main frame need to carry out read operation to slave, the first byte 310 that at first needs to send adds " the initial address 312 of reading of slave " for " reading to enable 311 ", main frame gives slave to control on the bidirectional data transfers line afterwards, main frame only need to produce transfer clock, and slave carries out sending of data by this transfer clock; After main frame sends the order of reading, because slave needs to parse the instruction time after receiving order, need the time-delay data group time (transfer clock of fixed number); The 3rd 330 times of byte with the data transmission of " slave start address " to main frame; The 4th byte time 340 with the data transmission of " slave start address+1 " to main frame; By that analogy, during N byte, the data for " slave is initial read address+(N-3) " that main frame is read by the bidirectional data transfers line;
5. slave begins data are sampled at the rising edge of bus clock, and carries out read-write operation according to the data of collecting;
Wherein, slave parses write operation and read operation by the data line receive data, is specially:
With reference to Fig. 6, slave when being in idle condition A, selects A1 to be dragged down when determining sheet to the resolving of write operation, begins to carry out the sampling B of data, and the sampling clock of slave is the rising edge E of bus clock; Collect after the first byte C, judging first byte most significant digit C1 is 1, namely currently writes the slave register manipulation for main frame, opens to write to enable D, and continues to collect the data that main frame produces; In the process of collecting, can the choosing of real-time judge sheet whether be high E1, if be high, then directly finish this time transmission; If be low, then continue receive data, judge whether simultaneously to collect data integrity E2, complete after, carry out write operation; By that analogy, N byte data always will receiving is written in the address of initial write address+(N-2);
With reference to Fig. 7, slave when slave is in idle condition A, selects A1 to be dragged down when determining sheet to the resolving of read operation, begins to carry out the sampling B of data; Collect after the first byte C, judging first byte most significant digit C1 is 0, namely currently reads the slave register manipulation for main frame, opens and reads to enable G; At second byte transmission cycle, namely during latent period H, at first change BDB Bi-directional Data Bus into slave output, main frame input by slave input, main frame output; Then abandon second byte while of collecting, the data of reading first address are prepared in the transmitter register; When entering into the 3rd byte transmission cycle, the data transmission bus of this moment sends value in the transmitter register by slave; And the data that will read the next address of first address are written in the transmitter register; By that analogy, always will receive in N byte transmission course, the value in the transmitter register is sent the initial stage, and the data of next address is written in the transmitter register; In case H1 is drawn high in the sheet choosing in the transmission, namely interrupt this time transmission operation, enter idle condition.
6. the main frame the transmission of data complete after, stop bus clock and just produce, draw high sheet and select enable line, finish this time transmission;
Wherein, the main frame that 3., 4. step is described sends data and clock, the each data transmission of initiating of main frame, always take transfer clock cycle of fixed numbers as one group, when one group of clock period less than that slave receives, give up the data of last transmission; The data transmission of step in 6. is complete, the minimum transfer clock cycle that comprises two groups of fixed numbers;
With reference to Fig. 3, the data transmission when the clock period that not enough fixed number is arranged directly abandons.
Host-host protocol of the present invention is simple, and easy to understand for the register of different bit wides, can customize slave to the parsing module of first byte, to satisfy the separately particular demands of design according to the requirement of bit wide and the address degree of depth; Be fit to very much the communication between the chip, applied range, simple and practical.
Claims (4)
1. the communication means of an easy bus transfer agreement is applicable to the register read write operation between main frame, the slave, it is characterized in that may further comprise the steps:
1. this transfer bus is comprised of 3 signal wires, respectively that sheet selects enable line 100, clock transfer line 200, bidirectional data transfers line 300, sheet select enable line and bidirectional data transfers line reset after the acquiescence state be high level, the clock transfer line reset after the acquiescence state be low level;
When 2. this transfer bus transmits, at first drag down sheet by main frame and select enable line; Slave detect sheet select enable line be low after, the inner enabling signal that produces;
3. main frame drags down sheet and selects after the enable line, produces bus clock, and by the clock transfer line with clock transfer to slave; Bus clock can be the frequency-dividing clock of the inner high frequency clock of main frame, and frequency dividing ratio can be arbitrary value;
4. main frame sends data by data line, and data can be a plurality of bytes; At first send the high position of current byte, big-endian sends successively, and the variation of bidirectional data transfers line is positioned at the negative edge of clock;
5. slave begins data are sampled at the rising edge of bus clock, and carries out read-write operation according to the data of collecting;
6. the main frame the transmission of data complete after, stop bus clock and just produce, draw high sheet and select enable line, finish this time transmission.
2. the communication means of a kind of easy bus transfer agreement according to claim 1, it is characterized in that: wherein the main frame 3., 4. described of step sends data and clock, the each data transmission of initiating of main frame, always take transfer clock cycle of fixed numbers as one group, when one group of clock period less than that slave receives, give up the data of last transmission; The data transmission of step in 6. is complete, the minimum transfer clock cycle that comprises two groups of fixed numbers.
3. the communication means of a kind of easy bus transfer agreement according to claim 1, it is characterized in that: the frequency-dividing clock that the main frame of step in 3. produces, frequency dividing ratio comprises 1 frequency division, and namely transfer clock and main frame internal clocking are with frequency, the highest mxm. that can reach the circuit interface frequency.
4. the communication means of a kind of easy bus transfer agreement according to claim 1 is characterized in that: step 4. in main frame send data by data line, comprise write operation and read operation, be specially:
When main frame need to carry out write operation to slave, the first byte that at first needs to send adds " slave start address " for " write and enable 1 ", second byte is for writing the data of " slave start address ", the 3rd byte is for writing the data of " slave start address+1 ", by that analogy, N byte is for writing the data of " slave start address+N-2 "; Wherein, N is the number of byte;
When main frame need to carry out read operation to slave, the first byte that at first needs to send adds " slave start address " for " reading to enable 0 ", main frame gives slave to control on the bidirectional data transfers line afterwards, and main frame only need to produce transfer clock, and slave carries out sending of data by this transfer clock; After main frame sends the order of reading, because slave needs to parse the instruction time after receiving order, need byte time of time-delay, at the 3rd byte time with the data transmission of " slave start address " to main frame, the 4th byte time with the data transmission of " slave start address+1 " to main frame, by that analogy, during N byte, the data for " slave start address+N-3 " that main frame is read by the bidirectional data transfers line; Wherein, transfer clock that byte time is fixed numbers.
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Cited By (6)
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| CN104602036A (en) * | 2015-01-12 | 2015-05-06 | 深圳创维数字技术有限公司 | TS stream transmission method and related device |
| CN107743689A (en) * | 2015-06-19 | 2018-02-27 | Gwf测量系统股份公司 | For transmitting the method and apparatus and counting unit of data |
| CN108600066A (en) * | 2018-04-10 | 2018-09-28 | 武汉虹创联众科技有限公司 | A kind of monobus communication means |
| CN111339001A (en) * | 2020-03-09 | 2020-06-26 | 厦门润积集成电路技术有限公司 | Low-power-consumption single bus communication method and system |
| CN117573044A (en) * | 2024-01-18 | 2024-02-20 | 西安智多晶微电子有限公司 | Method and device for expanding DDRC bit width by splicing |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103838700A (en) * | 2014-02-20 | 2014-06-04 | 江苏理工学院 | level multiplexing control serial communication device and communication method thereof |
| CN104602036A (en) * | 2015-01-12 | 2015-05-06 | 深圳创维数字技术有限公司 | TS stream transmission method and related device |
| CN107743689A (en) * | 2015-06-19 | 2018-02-27 | Gwf测量系统股份公司 | For transmitting the method and apparatus and counting unit of data |
| CN107743689B (en) * | 2015-06-19 | 2021-10-22 | Gwf测量系统股份公司 | Method and device for transmitting data and counting unit |
| CN108600066A (en) * | 2018-04-10 | 2018-09-28 | 武汉虹创联众科技有限公司 | A kind of monobus communication means |
| CN108600066B (en) * | 2018-04-10 | 2021-07-02 | 武汉虹创联众科技有限公司 | Single bus communication method |
| CN111339001A (en) * | 2020-03-09 | 2020-06-26 | 厦门润积集成电路技术有限公司 | Low-power-consumption single bus communication method and system |
| CN111339001B (en) * | 2020-03-09 | 2021-07-30 | 厦门润积集成电路技术有限公司 | Low-power-consumption single bus communication method and system |
| CN117573044A (en) * | 2024-01-18 | 2024-02-20 | 西安智多晶微电子有限公司 | Method and device for expanding DDRC bit width by splicing |
| CN117573044B (en) * | 2024-01-18 | 2024-04-30 | 西安智多晶微电子有限公司 | Method and device for expanding DDRC bit width by splicing |
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Application publication date: 20130501 |