CN102541788A - APB (advanced peripheral bus) bridge and method for executing reading or writing by using APB bridge - Google Patents
APB (advanced peripheral bus) bridge and method for executing reading or writing by using APB bridge Download PDFInfo
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Abstract
The invention discloses an APB (advanced peripheral bus) bridge and a method for executing reading or writing by using the APB bridge. The APB bridge comprises an SPI (serial peripheral interface) transceiver logic, a write cache, a read cache, a data conversion logic and an APB interface, wherein the SPI transceiver logic is used for receiving or transmitting SPI data with predefined digits by an SPI; the write cache is coupled with the SPI transceiver logic, and used for caching the received SPI data when the SPI data indicate that an operation is required to be performed on a second SOC (system on a chip); the read cache is coupled with the SPI transceiver logic, arranged parallel to the write cache, and used for caching SPI data required to be transmitted back to a first SOC when a read-write mark bit in the SPI data indicates that a read-write operation is required to be performed on the second SOC; the data conversion logic is coupled with the write cache and the read cache, and used for carrying out conversion between the SPI data and the APB data; and the APB interface is coupled with the data conversion logic, and used for transmitting the APB data to the second SOC so as to execute a reading or writing operation.
Description
Technical field
The present invention relates to a kind ofly be used to make APB (advanced peripheral bus) bridge that SOC (SOC(system on a chip)) communicates by letter with the 2nd SOC of winning, and relate to and be used to utilize APB bridge of the present invention to make a SOC carry out the method for read or write operation to the 2nd SOC.
Background technology
For SOC; Advanced peripheral bus (APB) is that ARM invention a kind of is suitable for connecting low bandwidth, does not need the bus of high-performance channel interface peripheral hardware, has simple to operate; Advantages such as all signal transition are only relevant with rising edge clock; Often come out separately,, expanded the function of SOC chip to realize and the communicating by letter of low speed peripheral hardware as the peripheral bus interface.
Along with the appearance of present multiple special-purpose SOC, sometimes need make hardware, but the limited SOC of interface expands to some, to realize more function, perhaps two different SOC will use jointly, and the intercommunication mutually between needing mutually.
The present invention has designed a kind of APB bridge, communicates with outside SPI, and CPU can change APB bridge control APB system through this SPI; The APB system just can effectively use like this, can not take the resource of cpu bus, can effectively utilize limited interface resource expansion greater functionality; UART for example; I2C, PS2, LED etc.
Summary of the invention
Technical matters to be solved by this invention is effectively to utilize limited SOC interface resource expansion greater functionality, UART for example, I2C, PS2, LED etc.
In order to address the above problem, the present invention discloses a kind of APB bridge that a SOC is communicated by letter with the 2nd SOC of being used to, and it is characterized in that a said SOC is connected through SPI with the APB bridge, and said the 2nd SOC is connected through APB with the APB bridge, and said APB bridge comprises:
SPI receives and dispatches logic, is used for receiving or send the SPI data with predefine figure place through SPI;
With the buffer of writing of said SPI transmitting-receiving logic coupling, be used for indicating will be to the 2nd SOC executable operations the time SPI data that buffer memory received when said SPI data;
With the coupling of said SPI logic and with said write buffer parallel be provided with read buffer, be used for when the read-write zone bit indication of said SPI data will be to the 2nd SOC execution read operation, buffer memory will be passed the SPI data of a SOC back;
With said buffer and the said data switching logic of reading the buffer coupling write, be used between said SPI data and APB data, changing;
With the APB interface of said data switching logic coupling, be used for giving the 2nd SOC to carry out read or write operation the APB data transfer.
Also disclose and utilized APB bridge the one SOC of the present invention, comprised the steps: the method that the 2nd SOC with APB interface carries out write operation
SPI transmitting-receiving logic receives the SPI data with predefine figure place;
When the indication of the read-write zone bit in the said SPI data will be carried out write operation to the 2nd SOC, write the SPI data that the buffer buffer memory is received;
Data switching logic is the APB data with the SPI data-switching of said buffer memory;
The APB interface of APB bridge gives the 2nd SOC to carry out write operation said APB data transfer.
In addition, also disclose and utilized APB bridge the one SOC of the present invention, comprised the steps: the method that the 2nd SOC with APB interface carries out read operation
SPI transmitting-receiving logic receives the SPI data with predefine figure place;
When the indication of the read-write zone bit in the said SPI data will be carried out read operation to the 2nd SOC, write the SPI data that the buffer buffer memory is received;
Data switching logic is the APB data with said SPI data-switching;
The APB interface of APB bridge gives the 2nd SOC to carry out read operation said APB data transfer;
Data switching logic is another SPI data with the data-switching that is read;
Said another SPI metadata cache is read in the buffer said;
When a SOC initiated to transmit once more, SPI transmitting-receiving logic sent to a SOC with said another SPI data through SPI.
In a preferred embodiment, saidly write buffer and the said buffer of reading all is the FIFO buffer.In a further advantageous embodiment, the pointer information of said FIFO buffer is synchronous.
In another preferred embodiment, the agreement of said APB is APB2.0.
In another preferred embodiment again, said predefine figure place is 32 or 16.
Compared with prior art, the present invention has the following advantages:
The present invention has designed a kind of APB bridge; Communicate with outside SPI; CPU can change APB bridge control APB system through this SPI, and the APB system just can effectively use like this, can not take the resource of cpu bus; Can effectively utilize limited interface resource expansion greater functionality, for example UART, I2C, PS2, LED etc.Thereby, utilize APB bridge of the present invention can realize data transmission and control between the different on-chip integration system SOC, expand the function of SOC greatly, and realized fast data transmission and active data management.
Description of drawings
Other characteristic of the present invention and advantage will obtain more clearly manifesting from the description of reading below with reference to a plurality of preferred embodiments of the present invention of respective drawings:
Fig. 1 is the synoptic diagram of a kind of APB system of prior art;
Fig. 2 is the interface structure figure of the APB bridge of prior art;
Fig. 3 is the interface structure figure of the APB of prior art from module;
Fig. 4 is the structured flowchart that makes the APB bridge that the SOC that wins communicates by letter with the 2nd SOC according to of the present invention;
Fig. 5 is the sequential chart according to the total line write transactions of APB of the present invention;
Fig. 6 is the sequential chart according to APB bus of the present invention read operation;
Fig. 7 utilizes APB bridge the one SOC according to the present invention the 2nd SOC with APB interface to be carried out the process flow diagram of write operation;
Fig. 8 utilizes APB bridge the one SOC according to the present invention the 2nd SOC with APB interface to be carried out the process flow diagram of read operation.
Embodiment
Now will with reference to accompanying drawing the present invention be described more fully hereinafter, illustrative example of the present invention wherein shown in the drawings.In this accompanying drawing, for clear, the relative size of position or characteristic can be exaggerated.But the present invention can implement with many different forms, and will can not think the embodiment that is confined to set forth herein; On the contrary, these embodiment will be provided so that this openly will be comprehensive and complete, and send scope of the present invention to those skilled in the art all sidedly.It should be understood that it can directly be coupled or be connected to another element, perhaps can also have the insertion element when an element is known as " coupling " or is ' attach ' to another element.By contrast, be known as " directly coupling " when perhaps " directly connecting " to another element, do not have the element of insertion when an element.Identical numeral refers to components identical from start to finish.As use herein, this term " and/or " comprise one or more any He all combinations of the relevant project of listing.
Though it should be understood that can use a technical term herein first, second or the like remove to describe various elements, these elements will not receive the restriction of these terms.These terms only are used an element and the difference of another element.Therefore, under the situation that does not break away from the present invention's instruction, first element that is discussed below can be called as second element.
The term that uses herein only is in order to describe the purpose of specific embodiment, and is not intended to limit the present invention.As use herein, the form of this odd number " ", " one " are intended to comprise equally plural form, only if outside the expression of clear from context ground.Further it should be understood that; The term that in this instructions, uses " comprises " and/or " comprising " specify to exist characteristic, integer, step, operation, element and/or the parts of statement, does not exist or increases one or more other characteristic, integer, step, operation, element, parts and/or its groupings but do not get rid of.
Only and if outer, all terms (comprising technology and scientific terminology) that use herein have and the identical implication of being understood by this field those of ordinary skill that the invention belongs to usually by definition.Further it should be understood that; Should be interpreted as such as those terms that limit in the dictionary commonly used and to have following implication, that is, meet their implications in the context of correlation technique; And except limiting expressly herein, can not explained with idealized or too formal meaning.
Fig. 1 is the synoptic diagram of a kind of APB system of prior art.The APB system mainly is made up of from module APB bridge and APB as primary module.In Fig. 1,5 APB are arranged on the whole APB bus from module.From module an APB interface is arranged all for each APB.The interface structure figure of APB bridge is as shown in Figure 2, and APB is as shown in Figure 3 from the interface structure figure of module.
Fig. 2 is the interface structure figure of the APB bridge of prior art.The APB bridge has been realized system bus and APB communicating by letter from module.Address, data and selection signal etc. according to the system bus transmission; Produce the APB transmission address signal PADDR, read-write control signal PWRITE, select signal PSELx, gating signal PENABLE, write data signal PWDATA to APB on module, or pass back to system bus behind the reading of data PRDATA on from APB from module.Fig. 3 is the interface structure figure of the APB of prior art from module.Wherein, clock signal PCLK, address signal PADDER, read-write control signal PWRITE, selection signal PSEL, gating signal PENABLE and write data signal PWDATA are the input signal of APB from module, and reading data signal PRDATA is the output signal; From module an independently PSEL input signal is arranged all for each APB.And the signal wire that other signal all is all APB on the shared APB bus of module.PCLK is the clock signal of APB peripheral hardware, and PRESETn is the reset signal of system.PSELx, PADDR, the PWRITE combination has determined which register is carried out read-write operation, PWDATA/PRDATA is the data of transmission.
Along with the appearance of multiple SOC, need expand to realize more function and the solution that intercoms mutually limited SOC interface.For this reason, the present invention proposes a kind of APB bridge that a SOC is communicated by letter with the 2nd SOC of being used to.
Fig. 4 is the structured flowchart that makes the APB bridge 2 that a SOC 1 communicates by letter with the 2nd SOC 3 according to of the present invention.In Fig. 4, a SOC 1 is connected with APB bridge 2 through SPI; The 2nd SOC 3 is connected with APB bridge 2 through APB.SPI is a kind of synchronous serial Peripheral Interface, and it can make CPU and various peripherals communicate with serial mode.Can connect FLASHRAM, network controller, LCD display driver etc.4 lines of the general use of SPI: serial time clock line (SPICLK), main frame input/slave output data line MISO, main frame output/slave input data line MOSI and the effective slave selection wire of low level CS.
APB bridge 2 according to the present invention comprises SPI transmitting-receiving logic 4, is used for receiving or send the SPI data with predefine figure place through SPI; With 4 couplings of said SPI transmitting-receiving logic write buffer 5, be used for indicating will be to the 2nd SOC3 executable operations the time SPI data that buffer memory received when said SPI data; With 4 couplings of said SPI logic and with said write buffer 5 parallel be provided with read buffer 6, be used for when the read-write zone bit indication of said SPI data will be to the 2nd SOC 3 execution read operations, buffer memory will be passed the SPI data of a SOC 1 back; With said buffer 5 and the said data switching logic 7 of reading buffer 6 couplings write, be used between said SPI data and APB data, changing; With the APB interface 8 of said data switching logic 7 couplings, be used for giving the 2nd SOC 3 to carry out read or write operation the APB data transfer.
In a preferred embodiment, APB bridge 2 also comprises configuration register 9, for example disposes the register of SPI transmission mode, the duty register of APB bridge, register of SPI data definition or the like.
In a preferred embodiment, saidly write buffer 5, the said buffer 6 of reading all is FIFO (FIFO formula) buffer, its pointer information is synchronous, and logic is simple, is easy to realize.
SPI and SPI transmitting-receiving logic is supported the SPI standard agreement, can support 32 or 16 s' SPI data transmission, and therefore, said predefine figure place is 32 or 16.
In another preferred embodiment, the employed agreement of APB is APB2.0, and read-write efficiency is high.The write operation of APB2.0 and the sequential chart of read operation are described below.
The sequential of writing read operation of APB interface 8 is like Fig. 5, shown in 6.
Fig. 5 is APB 2.0 write operation sequential charts.When PADDR, PWRITE, PSEL, PWDATA all changed after rising edge clock, write operation began, and this cycle is called the SETUP cycle.Come into force at next clock period enable signal PENABLE, be called the ENABLE cycle, address, data and control signal are all remained valid in this cycle.After the end of transmission (EOT), select invalidating signal, address signal and write signal remain unchanged to reduce power consumption.
Fig. 6 is APB 2.0 read operation sequential charts.The address of read operation is write, select all the same with enable signal with write operation, must be from module in ENABLE cycle returned data, data are sampled by the APB bridge at the rising edge of ENABLE end cycle.
Fig. 7 utilizes the process flow diagram that has the 2nd SOC 2 execution write operations of APB interface according to 1 couple of APB bridge the one SOC of the present invention.
In step 701, SPI transmitting-receiving logic 4 receives the SPI data with predefine figure place through SPI from a SOC 1.In a preferred embodiment, according to the SPI agreement, this predefined figure place can be 32 or 16.
In the SPI data were 32 example, the SPI serial line interface as slave unit, received 32 bit data that the SPI main equipment sends, wherein being defined as of data according to the SPI host-host protocol of acquiescence:
[31] 1:write, 0:read reads or writes, i.e. PWRITE.
[30:27] if be not 0, the data number N of the continuous read/write of then indicating.If N is not 0, the N byte data of transmission all is data so afterwards, and does not comprise the address, selects information such as signal.The N byte data is counted from 32 low level.
The APB bus slave ID that [26:24] will select, i.e. PSEL_X.
The internal blas address of [23:16] APB bus slave, i.e. PADDR.
The data that [15:8] writes to the slave unit of APB bus, promptly PWDATA is generally 0, if be not 0 then the 2nd data that expression is write same address continuously.
[7:0] is to the slave unit write data of APB bus, i.e. PWDATA/PRDATA.
In step 702, when the indication of the read-write zone bit in the said SPI data will be carried out write operation to the 2nd SOC 3, write the SPI data that buffer 5 buffer memorys are received.That is to say, when the 31st PWRITE of SPI data is 1, shows and to carry out write operation to the 2nd SOC3.Write 32 SPI data that buffer 5 buffer memorys are received.
In step 703, data switching logic 7 is the APB data with the SPI data-switching of said buffer memory, and these APB data comprise read-write control signal, select signal, address signal, data-signal.
In step 704, APB interface 8 gives the 2nd SOC 3 to carry out write operation said APB data transfer.Particularly, APB interface 8 is with the address signal in the said APB data, selection signal, and APB signals such as data-signal send to the 2nd SOC 3.Thereby, accomplished the process of a SOC to the 2nd SOC execution write operation.
Utilize APB bridge of the present invention to carry out write operation with an example explanation below.
Tentation data is configured to acquiescence, i.e. PADDR, and PWDATA is 8, and PSEL_X is 3, and the number N of read/write is 4 continuously.The data that the SPI interface receives are 32`h810400aa; This 32 figure place can be deposited in write data FIFO buffer, and data switching logic is passed to APB interface, i.e. PWRITE=1 to this data-switching for the APB signal; PSEL_1 is 1; PADDR=04, PWDATA=8`haa, the APB bus is sent data 8`haa immediately to give 1 li offset address of slave unit is 04 register among such the 2nd SOC.
In addition; If continuous read-write operation is carried out in the same address among the 2nd SOC 3, the byte number that transmits after the special expression of number N is then arranged in 32 SPI data, N the byte that promptly the SPI interface receives after the expression all is data; And do not comprise information such as address, thereby improve transfer efficiency.
Next, illustrate and utilize APB bridge of the present invention that continuous read-write operation is carried out in same address among the 2nd SOC.
Tentation data is configured to acquiescence, and the data that SPI receives are 32`ha10400aa, and 4 bytes of expression 8`haa and reception afterwards all are that all will to write 1 li offset address of slave unit be in 04 the register to data.Earlier deposit 32`ha10400aa in write data FIFO buffer, pass to the APB interface through after the data-switching, the APB bus is sent data 8`haa immediately to give 1 li offset address of slave unit is 04 register among such the 2nd SOC.If the SPI interface has received 32`hbbccddee again, 32 SPI data writing so in the write data FIFO buffer are exactly 32`ha10400bb, 32`ha10400cc, 32`ha10400dd, and 32`ha10400ee.The APB bus is sent data 8`hbb successively, 8`hcc, and 8`hdd, 8`hee, giving 1 li offset address of slave unit is 04 register.
Fig. 8 utilizes APB bridge the one SOC according to the present invention the 2nd SOC with APB interface to be carried out the process flow diagram of read operation.
In step 801, SPI transmitting-receiving logic 4 receives the SPI data with predefine figure place.Equally, according to the SPI agreement, this predefined figure place can be 32 or 16.
In step 802, when the indication of the read-write zone bit in the said SPI data will be carried out read operation to the 2nd SOC 3, write the SPI data that buffer 5 buffer memorys are received.In the SPI data are 32 embodiment, when the 31st PWRITE of SPI data is 0, shows and to carry out read operations to the 2nd SOC 3.
In step 803, data switching logic 7 is the APB data with said SPI data-switching.Wherein these APB data comprise read-write control signal, select signal, address signal.
In step 804, APB interface 8 gives the 2nd SOC3 to carry out read operation said APB data transfer.Particularly, according to the reading of data from the 2nd SOC 3 of the address signal in the said APB data.
Next, in step 805, data switching logic 7 is another SPI data with the data-switching that is read.
Then, in step 806, said another SPI metadata cache is read in the buffer 6 said.
In a preferred embodiment, this method also is included in following steps:
When a SOC 1 initiated transmission once more, SPI transmitting-receiving logic 4 sent to a SOC 1 with said another SPI data through SPI.Thereby, accomplished the process that a SOC 1 couple the 2nd SOC 3 carries out read operations.
Utilize APB bridge of the present invention to carry out read operation with an example explanation below.Tentation data is configured to acquiescence, and the data that SPI receives are 32`h01040000, indicates to read 1 li offset address of slave unit and be the value of 04 register.Earlier deposit 32`h01040000 in write data FIFO buffer.Data switching logic is this data-switching the APB signal, i.e. PWRITE=0, and PSEL_1 is 1, and PADDR=04 is the value of 04 register through 1 li offset address of APB bus fetch equipment among the 2nd SOC then, is assumed to be 8`h55, and then PRDATA is 8`h55.The conversion of signals such as data that data switching logic reads APB are that 32 SPI data 32`h01040055 deposits read data FIFO buffer in.When the transmission of SPI main equipment initiation next time, this number will be sent to the SPI main equipment by SPI slave unit interface.
The definition that it is pointed out that the SPI data all can be changed, and defines according to actual needs.Also can support each 16 PWDATA data transmission, promptly [15:0] all is data.
In addition, in other embodiments, the SPI serial line interface also can be defined as following 16:
[15] 1: read 0: write
The APB bus slave ID that [14:12] will select, PSEL_X
The internal blas address of the slave unit of [11:8] APB bus
[7:0] is to the slave unit write data of APB bus, PWDATA/PRDATA
If be that the device id data are 000 under 32 or 16 s' the situation in the SIP data, then be to read and write to the internal register of SPI_APB bridge, at this time have only the data of least-significant byte that the SPI_APB internal configuration registers is read and write.
Through foregoing description with for example, can find out that advantage of the present invention is tangible.The present invention has realized data transmission and the control between the different on-chip integration system SOC, has expanded the function of SOC greatly, and has realized fast data transmission and active data management.
Foregoing is that the present invention will be described, and should not be construed as restriction the present invention.Though described several example embodiment of the present invention, those skilled in the art will easily understand, substantially do not break away under the present invention novel instruction and advantage, many modifications are admissible in exemplary embodiment.Therefore, all such modifications are intended to be included in as in the scope of the present invention that in claim, limits.In those claims, it is when carrying out the function of enumerating, to cover structure described herein and be not only structural equivalence that device adds function subordinate clause intention, and is the structure of equivalence.Therefore, it should be understood that the present invention is by following claim, and be included in that the equivalence of claim wherein limits.
Claims (11)
1. one kind is used to APB bridge that a SOC is communicated by letter with the 2nd SOC, it is characterized in that a said SOC is connected through SPI with the APB bridge, and said the 2nd SOC is connected through APB with the APB bridge, and said APB bridge comprises:
SPI receives and dispatches logic, is used for receiving or send the SPI data with predefine figure place through SPI;
With the buffer of writing of said SPI transmitting-receiving logic coupling, be used for indicating will be to the 2nd SOC executable operations the time SPI data that buffer memory received when said SPI data;
With the coupling of said SPI logic and with said write buffer parallel be provided with read buffer, be used for when the read-write zone bit indication of said SPI data will be to the 2nd SOC execution read operation, buffer memory will be passed the SPI data of a SOC back;
With said buffer and the said data switching logic of reading the buffer coupling write, be used between said SPI data and APB data, changing;
With the APB interface of said data switching logic coupling, be used for giving the 2nd SOC to carry out read or write operation the APB data transfer.
2. APB bridge according to claim 1 is characterized in that:
Saidly write buffer and the said buffer of reading all is the synchronization fifo buffer.
3. APB bridge according to claim 1, the agreement that it is characterized in that said APB is APB2.0.
4. APB bridge according to claim 1 is characterized in that said predefine figure place is 32 or 16.
5. a utilization makes a SOC to the method that the 2nd SOC with APB interface carries out write operation according to the APB bridge of claim 1, comprises the steps:
SPI transmitting-receiving logic receives the SPI data with predefine figure place;
When the indication of the read-write zone bit in the said SPI data will be carried out write operation to the 2nd SOC, write the SPI data that the buffer buffer memory is received;
Data switching logic is the APB data with the SPI data-switching of said buffer memory;
The APB interface of APB bridge gives the 2nd SOC to carry out write operation said APB data transfer.
6. method according to claim 5, the agreement that it is characterized in that said APB is APB2.0.
7. method according to claim 5 is characterized in that said predefine figure place is 32 or 16.
8. a utilization makes a SOC to the method that the 2nd SOC with APB interface carries out read operation according to the APB bridge of claim 1, comprises the steps:
SPI transmitting-receiving logic receives the SPI data with predefine figure place;
When the indication of the read-write zone bit in the said SPI data will be carried out read operation to the 2nd SOC, write the SPI data that the buffer buffer memory is received;
Data switching logic is the APB data with said SPI data-switching;
The APB interface is given the 2nd SOC according to said APB data transfer, to carry out read operation;
Data switching logic is another SPI data with the data-switching that is read;
Said another SPI metadata cache is read in the buffer said.
9. method according to claim 8 also comprises the steps:
When a SOC initiated to transmit once more, SPI transmitting-receiving logic sent to a SOC with said another SPI data through SPI.
10. method according to claim 8, the agreement that it is characterized in that said APB is APB2.0.
11. method according to claim 8 is characterized in that said predefine figure place is 32 or 16.
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Cited By (4)
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| CN102981996A (en) * | 2012-11-26 | 2013-03-20 | 福州瑞芯微电子有限公司 | Expansion device and method for periphery interfaces |
| CN103577368A (en) * | 2013-11-11 | 2014-02-12 | 东莞市泰斗微电子科技有限公司 | IIC communication extension method and device based on SPI protocol |
| CN109684245A (en) * | 2018-12-11 | 2019-04-26 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method and device of APB bus access SPI FLASH |
| CN116259347A (en) * | 2023-05-16 | 2023-06-13 | 上海灵动微电子股份有限公司 | Programming device of embedded flash memory based on SPI protocol |
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| 张桂友等: "串行外围接口SPI功能模块的设计", 《微处理机》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102981996A (en) * | 2012-11-26 | 2013-03-20 | 福州瑞芯微电子有限公司 | Expansion device and method for periphery interfaces |
| CN103577368A (en) * | 2013-11-11 | 2014-02-12 | 东莞市泰斗微电子科技有限公司 | IIC communication extension method and device based on SPI protocol |
| CN103577368B (en) * | 2013-11-11 | 2017-06-20 | 泰斗微电子科技有限公司 | A kind of IIC communication extension method and device based on SPI protocol |
| CN109684245A (en) * | 2018-12-11 | 2019-04-26 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method and device of APB bus access SPI FLASH |
| CN109684245B (en) * | 2018-12-11 | 2022-05-27 | 中国航空工业集团公司西安航空计算技术研究所 | Method and device for accessing SPI FLASH through APB bus |
| CN116259347A (en) * | 2023-05-16 | 2023-06-13 | 上海灵动微电子股份有限公司 | Programming device of embedded flash memory based on SPI protocol |
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