WO2012155674A1 - Concurrent access method and system and interface device - Google Patents

Abstract

Provided are a concurrent access method and system, and an interface device. The concurrent access system comprises: a master apparatus (1), an interface device (3) and a plurality of slave apparatuses (5). The master apparatus (1) is connected to the interface device (3) through a data bus (2). The interface device (3) is connected to the respective slave apparatuses (5) through a plurality of series peripheral interface (SPI) buses (4). The master apparatus (1) is configured to: convert serial data of the plurality of slave apparatuses (5) into parallel data according to the clock cycle, and then output the parallel data to the interface device (3) through the data bus (2); and output chip select data for selecting the plurality of slave apparatuses (5) to the interface device (3) through the data bus (2). The interface device (3) is configured to convert the parallel data and the chip select data into level signals, and then output the level signals to a corresponding slave apparatus (5) through a corresponding SPI bus (4). The provided concurrent access method and system and interface device can improve the access efficiency when a plurality of apparatuses is connected to the SPI interface.

Description

 Concurrent access method, system and interface device

 The present invention relates to the field of embedded system design, and more particularly to a method, system and interface device for implementing concurrent access of a set of slave devices by an embedded CPU in the existing SPI technology. Background technique

 The Serial Peripheral Interface (SPI) is a serial transmission interface used in the field of electronic technology. It is widely used in the design of embedded systems. The usual SPI interface consists of four kinds of logic signals: clock signal (SCLK); master device output, slave device input signal (MOSI); master device input, slave device output signal (MISO); chip select signal (SS) ). The principle of transmitting data on the SPI interface is as follows: The master device transmits data to the slave device through the MOSI under the driving of the clock signal (SCLK), and collects the data transmitted from the device to the master device on the MISO, and can output the chip select signal through the SS to implement the slave device. Choose one more. Among them, the serial clock frequency of the SPI interface is usually l~70MHz.

In many designs, there are multiple slave devices in the system, and the master device needs to access a group of identical slave devices through the SPI. A typical application scenario is that the main CPU (Host CPU) performs register configuration and status polling on a set of chips that process data through the SPI interface. In the usual SPI interface design, the Host CPU can output the chip select signal to the corresponding slave device, select the data transfer separately, and select the next one after the completion, until all the slave devices are traversed once. Assuming that the SPI clock frequency is Fsclk, the number of devices attached to the SPI is N, the number of bits transmitted is Nb, and the total transmission time is estimated to be N*(l/Fsclk)*Nb. In practical applications, when the number of device groups is large and the access is frequent, the time spent on the SPI access will be very large, especially for the design of the SPI timing using the 10-pin of the Host CPU. There will be a significant impact on system performance.

 Although the access frequency of the SPI interface can be around 70MHz, it is not possible to increase the access efficiency by infinitely increasing the clock frequency of the SPI, because the actual operating frequency is limited by many conditions, and the running frequency is usually below 10MHz. Based on this problem, it is necessary to develop a concurrent SPI access system. Summary of the invention

 It is an object of the present invention to provide a concurrent access method, system and interface device for improving access efficiency when multiple devices are attached to an SPI interface.

 To achieve the above object, the present invention provides the following technical solutions:

 A concurrent access system includes a master device, an interface device, and a plurality of slave devices, wherein the master device is connected to the interface device through a data bus, and the interface device is respectively connected to each slave device through a plurality of SPI buses, wherein :

 The master device is configured to convert serial data of the plurality of slave devices into parallel data according to a clock cycle, output to the interface device through the data bus, and The chip selection data selected by the device is output to the interface device through the data bus;

 The interface device is configured to convert the parallel data and the chip select data into a level signal, and then output to a corresponding slave device through a corresponding SPI bus.

 The above concurrent access system, wherein:

 The interface device is further configured to: collect a level signal output by each slave device from the SPI bus, and convert the level signal into input data;

 The master device is further configured to acquire the input data from the interface device through the data bus, and convert the input data of a plurality of clock cycles into serial data of each slave device.

 In the above concurrent access system, the interface device includes:

Multiple MOSI ports, each MOSI port is connected to a slave device's MOSI port; Multiple MISO ports, each MISO port is connected to a slave device's MIS0 port; multiple SS ports, each SS port is connected to a slave device's SS port;

 An output register, configured to store the parallel data, each bit corresponding to a slave device; an input register, configured to store the input data, each bit corresponding to a slave device; a chip select register, for storing The chip selection data, each bit corresponding to a slave device; a logic conversion unit, configured to convert the parallel data into a level signal, output through the MOSI port, convert the chip select data into a level signal, and then pass The SS port output converts the level signal acquired from the MISO port to the input data.

 In the above concurrent access system, the master device includes an SCLK port that provides a clock signal, and the SCLK port is connected to an SCLK port of each slave device.

 The concurrent access system, wherein: the interface device includes an SCLK port that provides a clock signal, the SCLK port is connected to an SCLK port of each slave device, and the clock signal is transmitted by the master device through the data bus to The SCLK port of the interface device.

 The concurrent access system, wherein the master device is a CPU, and the interface device is

CPLD.

 An interface device is connected to a master device through a data bus, and is used for concurrent access of the master device to the plurality of slave devices, where the interface device includes:

 Multiple MOSI ports, each MOSI port is connected to a slave device's MOSI port; multiple SS ports, each SS port is connected to a slave device's SS port;

 An output register, configured to store parallel data of the plurality of slave devices output by the master device through the data bus, each bit corresponding to a slave device;

 a chip select register, configured to store chip select data output by the master device through the data bus for selecting a plurality of slave devices, each bit corresponding to a slave device;

And a logic conversion unit, configured to convert the parallel data into a level signal and output through the MOSI port, convert the chip select data into a level signal, and output the signal through the SS port. The above interface device, further comprising:

 a plurality of MISO ports, each MISO port is connected to a slave device's MISO port; an input register for storing input data, each bit corresponding to a slave device; the logic conversion unit is further configured to: The acquired level signal is converted to the input data.

 The above interface device, further comprising:

 An SCLK port is provided for the clock signal, the SCLK port being coupled to the SCLK port of each slave device, the clock signal being transmitted by the master device over the data bus to the SCLK port of the interface device.

 A concurrent access method is applied to a system including a master device, an interface device, and a plurality of slave devices, wherein the master device is connected to the interface device through a data bus, and the interface device separately and each through multiple SPI buses Connected from the device, the method includes:

 The master device converts the serial data of the plurality of slave devices into parallel data according to a clock cycle, outputs the data to the interface device through the data bus, and selects the plurality of slave devices for selection. Chip selection data is output to the interface device through the data bus;

 The interface device converts the parallel data and the chip select data into a level signal, and outputs the same to the corresponding slave device through the corresponding SPI bus.

 The above concurrent access method, wherein, the method further includes:

 The interface device collects a level signal output by each slave device from the SPI bus, and converts the level signal into input data;

 The master device acquires the input data from the interface device through the data bus, and converts the input data of a plurality of clock cycles into serial data of each slave device.

Compared with the existing SPI transmission method, the present invention adds an interface device between the master device and the slave device, and the interface device is connected to the master device through a data bus, and each of the plurality of SPI buses is connected to each other. From the device connection, make full use of the width advantage and operation of the main device data bus The computing power enables the master device to concurrently access a group of slave devices through the interface device, and the access efficiency is significantly improved. The invention also retains the access capability to a single slave device, and is suitable for various application scenarios. DRAWINGS

 1 is a schematic structural view of a concurrent access system of the present invention;

 2 is a schematic diagram of a specific example of a concurrent access system of the present invention;

 3 is a schematic diagram showing the workflow of the concurrent access system shown in FIG. 2;

 4 is a schematic diagram of a data conversion manner in the concurrent access system shown in FIG. 2. detailed description

 The present invention will be described in detail below with reference to the drawings and specific embodiments.

 By analyzing the access characteristics of the CPU to the data processing chipset, it can be found that the CPU access requirements are mostly batch and concurrent. In other words, the CPU always needs to initiate the same operation for all data processing chips at the same time. For example, at some time, the CPU needs to initiate a status polling operation for all chips, and then, based on the status read, determines whether it needs to read the data transmitted by the chip. If these batch and concurrent accesses can be placed in an SPI access cycle, the access efficiency will be greatly improved, and the embodiment of the present invention is designed according to this theory.

 1 is a schematic structural diagram of a concurrent access system according to an embodiment of the present invention. Referring to FIG. 1, a concurrent access system includes: a main device 1, an interface device 3, and a plurality of slave devices 5, and the master device 1 is connected to the interface device 3 through a data bus 2. The interface device 3 is connected to each slave device 5 via a plurality of SPI buses 4, respectively.

The master device 1 may be a CPU or a microcontroller, etc., the slave device 5 is a peripheral chip that communicates with the master device 1 through the SPI, and the interface device 3 may employ a programmable logic device (Complex) Programmable Logic Device (CPLD) implementation, in the application can also use microprocessors, digital signal processing chips and other programmable chips plus appropriate peripheral auxiliary circuits instead of CPLD.

 The main device 1 includes a data conversion module, a chip selection signal generation module, and a clock signal generation module. The data conversion module is capable of converting serial data of the plurality of slave devices 5 into parallel data according to a clock cycle, and is also capable of converting input data of each slave device 5 of the plurality of clock cycles into serial data of each slave device 5; The signal generation module is capable of generating chip select data for selecting a plurality of slave devices 5; the clock signal generation module is configured to generate a clock signal. The master device 1 supports a data access bus, and can transmit parallel data and chip select data to the interface device 3 via the data bus 2, and acquire input data of each slave device 5 from the interface device 4 via the data bus 2.

 The interface device 3 provides a set of registers for access by the master device 1 and provides a logic conversion unit to perform logic conversion of the data signals (including parallel data and chip select data) to the level signals, and to complete the acquisition from the MISO signal line. The level signal is converted into input data, and the bit of the register is transparently transmitted with the MISO or MOSI or SS signal line state of the SPI. Wherein each bit of the register corresponds to a slave device 5.

 The interface device 3 is connected to each of the slave devices 5 via a plurality of SPI buses 4, each of which has an MISO signal line, a MOSI signal line, and an SS signal line. Each slave device 5 has a MISO port, a MOSI port, an SS port, and an SCLK port. Correspondingly, the interface device 3 further comprises: a plurality of MOSI ports each connected to a MOSI port of a slave device 5; a plurality of MISO ports, each MISO port being connected to a MISO port of a slave device 5; Port, each SS port is connected to an SS port of device 5.

If the clock signal is directly output from the master device 1 to the slave device 5, the SCLK ports of all the slave devices 5 are connected to the SCLK port of the master device 1; if the clock signal is output from the master device 1 control interface device 3 to the slave device 5, The interface device 3 further includes an SCLK port, and all of the SCLK ports of the slave device 5 are connected to the SCLK port of the interface device 3. A basic workflow for the above concurrent access system is as follows:

 The master device outputs chip selection data for selecting a plurality of slave devices to the interface device through the data bus;

 The master device converts serial data of the plurality of slave devices into parallel data according to a clock cycle, and outputs the data to the interface device through the data bus;

 The interface device converts the parallel data and the chip select data into a level signal, and outputs the same to the corresponding slave device through the corresponding SPI bus;

 The interface device collects the level signal output by each slave device from the SPI bus, and converts the level signal into input data;

 The master device acquires input data from the interface device through the data bus, and converts input data of a plurality of clock cycles into serial data of each slave device.

 2 is a schematic diagram of a specific example of the concurrent access system of the present invention. Referring to FIG. 2, in the specific example, the master device is a CPU, the interface device is a CPLD, and the CPU is connected to the CPLD through a data bus (Host Bus), and the CPLD provides three sets of SPI logic conversion registers to the CPU, respectively: an output register DataOutReg_N ( RAV ) (for storing parallel data), input register DataInReg_N ( RO ) (for storing input data) and chip select register SSReg_N ( RAV ) (for storing chip select data). The number of SPI slaves that can be accessed in parallel is determined by the CPU data bus bit width W (which is also the bit width of the register) and the number of registers N of each set of registers, which is N*W, where N and W are integers greater than one. One bit of the register set is combined into a data signal DataOutReg[0:(N*Wl)], DataInReg[0:(N*Wl)], SSReg[0:(N*Wl)], each bit respectively Corresponds to the corresponding SPI signal line of a slave device.

The CPLD provides a logic conversion, converting each bit of DataOutReg[0:(N*Wl)] into a high and low level, and outputting it to the corresponding MOSI of each slave device; collecting the input value of the level value on the MISO of the device To each bit of DataInReg[0:(N*Wl)]; convert each bit of SSReg[0:(N*Wl)] into a high and low level, and output it to the SS corresponding to each slave device. . The CPU generates a unified SPI clock signal through the general-purpose input/output (GPIO) port or controls the CPLD, and outputs it to the slave device.

 FIG. 3 is a schematic diagram of the workflow of the concurrent access system shown in FIG. Referring to Figure 3, the following steps are included:

 Step 301: When the CPU initiates a concurrent access, converting the original data sequence D into a data sequence B;

 In this step, the data conversion method is shown in Figure 4. The variables in the figure are as follows:

 D: raw data that needs to be transmitted;

 Wd: the bit length of the original data to be transmitted;

 B: converted data;

 N: the number of registers in each register group of the CPLD;

 W: Bit width of the CPU to CPLD data bus (also the bit width of the CPLD register).

 Step 302: The CPU combines the chip select signals into N W bit wide numbers, and writes each register corresponding to the SSReg register group through the data bus to select the slave device to be accessed;

Step 303: The CPU needs to send the data B _n to the slave device group in one clock cycle, and writes each register corresponding to the DataOutReg register group through the data bus;

 Step 304: The CPU outputs a clock signal, and the data is sent to the slave device in parallel, and the data returned from the device is also collected into the DatalnReg register group.

In this step, the data B _n is sent to the slave device in parallel, and the CPLD converts each bit value of the data B _n into a parallel level signal, and outputs it to the MOSI signal line corresponding to each slave device.

 In this step, the CPLD also collects all MISO level signals under clock drive, converts the level signals into input data and stores them in the DatalnReg register set for the CPU to read.

 Step 305: The CPU reads a set of data from the DatalnReg register group to complete data transmission of one clock cycle;

Step 306: Determine whether the transmission is completed. If yes, go to step 307. If no, return to the step. 303. Perform an operation on the next set of data B _n+1 ;

 Step 307: The CPU sets the SSReg register group to invalidate all the chip selects. Step 308: The CPU splits and combines each read DataInReg[0:(N*Wl)] bit to obtain the slave devices. The binary data of the CPU is combined in the reverse process of the mode shown in Figure 4, and will not be described here.

 At this point, the CPU completes concurrent access to each slave device.

 Compared with the existing SPI transmission method, the embodiment of the present invention adds an interface device between the master device and the slave device, and the interface device is connected to the master device through a data bus, and is respectively connected to the master device through multiple SPI buses. Each slave device is connected to take full advantage of the width advantage and computing power of the master device data bus, so that the master device can concurrently access a group of slave devices through the interface device, and the access efficiency is significantly improved. The embodiment of the present invention also retains the access capability to a single slave device, which is suitable for various application scenarios.

 It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to be limiting, and those skilled in the art should understand that the technical solutions of the present invention may be modified or equivalently substituted without departing from the technical solutions of the present invention. The spirit of the scope should be covered by the scope of the claims of the present invention.

Claims

Claim

 A concurrent access system, comprising: a master device, an interface device, and a plurality of slave devices, wherein the master device is connected to the interface device via a data bus, and the interface device separately and each through a plurality of SPI buses Connected from the device, where:

 The master device is configured to convert serial data of the plurality of slave devices into parallel data according to a clock cycle, output to the interface device through the data bus, and The chip selection data selected by the device is output to the interface device through the data bus;

 The interface device is configured to convert the parallel data and the chip select data into a level signal, and then output to a corresponding slave device through a corresponding SPI bus.

 2. The concurrent access system of claim 1 wherein:

 The interface device is further configured to: collect a level signal output by each slave device from the SPI bus, and convert the level signal into input data;

 The master device is further configured to acquire the input data from the interface device through the data bus, and convert the input data of a plurality of clock cycles into serial data of each slave device.

 3. The concurrent access system of claim 2, wherein the interface device comprises:

 Multiple MOSI ports, each MOSI port is connected to a slave device's MOSI port; multiple MISO ports, each MISO port is connected to a slave device's MISO port; multiple SS ports, each SS port and one slave device SS port connection;

An output register, configured to store the parallel data, each bit corresponding to a slave device; an input register, configured to store the input data, each bit corresponding to a slave device; a chip select register, for storing The chip selection data, each bit corresponding to a slave device; a logic conversion unit, configured to convert the parallel data into a level signal, output through the MOSI port, convert the chip select data into a level signal, and then pass SS port output, will be from MISO The level signal acquired by the port is converted into the input data.

 4. The concurrent access system of claim 3, wherein:

 The master device includes an SCLK port that provides a clock signal that is coupled to the SCLK port of each slave device.

 5. The concurrent access system of claim 3, wherein:

 The interface device includes an SCLK port that provides a clock signal, the SCLK port being coupled to an SCLK port of each slave device, the clock signal being transmitted by the master device through the data bus to an SCLK port of the interface device.

 6. The concurrent access system of claim 1 wherein:

 The master device is a CPU, and the interface device is a CPLD.

 An interface device, which is connected to the master device through a data bus, and is used for concurrent access of the master device to the plurality of slave devices, wherein the interface device includes:

 Multiple MOSI ports, each MOSI port is connected to a slave device's MOSI port; multiple SS ports, each SS port is connected to a slave device's SS port;

 An output register, configured to store parallel data of the plurality of slave devices output by the master device through the data bus, each bit corresponding to a slave device;

 a chip select register, configured to store chip select data output by the master device through the data bus for selecting a plurality of slave devices, each bit corresponding to a slave device;

 And a logic conversion unit, configured to convert the parallel data into a level signal and output through the MOSI port, convert the chip select data into a level signal, and output the signal through the SS port.

 8. The interface device of claim 7, further comprising:

a plurality of MISO ports, each MISO port is connected to a slave device's MISO port; an input register for storing input data, each bit corresponding to a slave device; the logic conversion unit is further configured to: The acquired level signal is converted to the input data.

9. The interface device of claim 8, further comprising: an SCLK port providing a clock signal, the SCLK port being coupled to an SCLK port of each slave device, the clock signal being passed by the master device The data bus is transmitted to the SCLK port of the interface device.

 10. A concurrent access method for use in a system comprising a master device, an interface device and a plurality of slave devices, the master device being connected to the interface device via a data bus, the interface device being respectively connected to the plurality of SPI buses Each of the slave devices is connected, wherein the method includes: the master device converts serial data of the plurality of slave devices into parallel data according to a clock cycle, and outputs the data to the interface device through the data bus And outputting chip selection data for selecting the plurality of slave devices to the interface device through the data bus;

 The interface device converts the parallel data and the chip select data into a level signal, and outputs the same to the corresponding slave device through the corresponding SPI bus.

 11. The concurrent access method according to claim 10, further comprising: said interface device collecting a level signal output by each slave device from said SPI bus, and converting said level signal into an input Data

 The master device acquires the input data from the interface device through the data bus, and converts the input data of a plurality of clock cycles into serial data of each slave device.