WO2014048327A1

WO2014048327A1 - Commissioning system and method

Info

Publication number: WO2014048327A1
Application number: PCT/CN2013/084223
Authority: WO
Inventors: 党君礼
Original assignee: 中兴通讯股份有限公司
Priority date: 2012-09-25
Filing date: 2013-09-25
Publication date: 2014-04-03
Also published as: CN103678078A; CN103678078B

Abstract

The present invention relates to a commissioning system and method. The commissioning system comprises: a core cluster, a data pool, a data acquisition module, a data transmission module, a clock management module, and a commissioning processing module. The core cluster comprises at least one IP core, the IP core comprising at least one integrated component; the clock management module is configured to generate a clock signal to drive the integrated component in the IP core and the data acquisition module to work; the data acquisition module is configured to acquire data of the integrated component in the IP core and obtain sampling data, and transmit the sampling data to the commissioning processing module by using the data transmission module; the commissioning processing module is configured to process the received sampling data, generate corresponding commissioning data and transmit the commissioning data to the data pool by using the data transmission module; and the data pool processes the commissioning data and loads the processed data to the corresponding integrated component for input. The present invention can improve the commissioning efficiency and accuracy.

Description

TECHNICAL FIELD The present invention relates to the field of chip testing, and in particular, to a debugging system and method. BACKGROUND OF THE INVENTION As Moore's Law gradually fails and the feature size of an integrated circuit approaches physical limits, power consumption and application diversity, and product launch cycles are further shortened in response to market demands, and system on chip (SOC) has been promoted. Has become the mainstream of integrated circuit design methodology. When trying to combine massive computation and control flexibility, and adapt to some special algorithms (because the delay is too tight or the throughput is too large, or both), DSP cooperates with CPU, in addition Some special hardware accelerators, as well as SOC systems composed of various interconnect structures and peripheral IPs, have become the mainstream design and implementation methods of current SOC systems. However, how to track and debug the SOC chip with multiple DSPs, CPUs and multiple hardware accelerators is a very difficult problem. Due to the large number of control signals to be observed and the large amount of data signals, it is difficult for the general commissioning system to meet the speed and throughput requirements, and there is no way to perform the cutting, and the CPU, DSP and hardware accelerators are separately implemented in the prior art. Debugging, very inefficient and inaccurate. SUMMARY OF THE INVENTION The main technical problem to be solved by the present invention is to provide a debugging system and method, which can improve the efficiency and accuracy of commissioning. To solve the above technical problem, the present invention provides a debugging system, and the specific technical solution thereof is as follows: A debugging system, comprising: a core cluster, a data pool, a data acquisition module, a data transmission module, a clock management module, and debugging Processing the module; the core cluster includes at least one IP core, the IP core includes at least one integrated component; the clock management module is configured to generate a clock signal to drive an integrated component in the IP core and the data acquisition module to operate; The data acquisition module is configured to collect data of the integrated component in the IP core to obtain sampling data, and transmit the sampling data to the debugging processing module by using the data transmission module; the debugging processing module is configured to receive The sampled data is processed, and corresponding debug data is generated and transmitted to the data pool by the data transmission module; the data pool is set to process the debug data, and the processed data is loaded into the corresponding data. The input of the integrated component. The debug data includes at least one of: load data and command parameter configuration data; the data pool is configured to perform predetermined data format conversion on the load data, and/or parse the command parameter configuration data. The data acquisition module includes: a multiplexer and a control register; the control register is configured to generate a control signal to the multiplexer in a configuration of the data pool; the multiplexer setting In order to select corresponding sampling data according to the control signal, the data transmission module is transmitted. The data transmission module includes: a data cache module and a bus bridge; the data cache module is configured to buffer the sample data output by the data module and the debug data generated by the debug processing module under the driving of the clock management module; The bus bridge is configured to transfer data between the data cache module and the debug processing module driven by the clock management module. The data buffering module includes a first FIFO data buffer and a first FIFO buffer controller; the first FIFO buffer controller is configured to control the first FIFO data buffer to buffer and output sampled data; a FIFO data buffer is configured to buffer the sampling data output by the data module under the driving of the clock management module, and when a full signal is generated, the full signal is transmitted to the clock management module; the clock management module further It is arranged to close the corresponding integrated component according to the full signal. The data cache module further includes a second FIFO data buffer and a second FIFO cache controller; the second cache controller is configured to control the second FIFO data buffer to buffer and output the debug data; The second FIFO data buffer is configured to buffer the debug data under the driving of the clock management module, and when a full signal is generated, the full signal is transmitted to the debug processing module; the debug processing module further It is set to stop transmitting debug data to the second FIFO data buffer after receiving the full signal. The IP core includes at least one integrated component of a CUP, a DSP, and a hardware accelerator. The present invention also provides a debugging method, and the technical solution thereof is as follows: A debugging method, comprising: the following steps: collecting at least one IP core in a core cluster driven by a clock management module Data of at least one of the integrated components obtains sampled data; processing the sampled data to generate corresponding debug data; processing the debug data, and loading the processed debug data to an input of the corresponding integrated component. After the data of the at least one integrated component of the at least one IP core in the core cluster is collected, before the processing the collected data, the method further includes: selecting corresponding sampling data according to the received control signal. The debugging data at least includes: one of loading data and command parameter configuration data; the processing the debugging data includes: performing predetermined data format conversion on the loading data, and/or parsing the command parameter Configuration Data. The invention has the beneficial effects that: the debugging system and the method provided by the invention can effectively debug the multi-core integrated circuit. In the setting of a multi-core cluster, it is possible to debug the integrated components in the IP core and solve the problem of multi-core debugging. The clock management module is set, and each module in the system is in the clock management module. Working under the control, can improve the system's commissioning speed and reduce energy consumption; set the multiplexer in the data acquisition module, you can select the sampling signal to be tested according to the requirements; set the data cache module to cache the commissioning data and Sampling data facilitates the stability and accuracy of the commissioning. At the same time, the first FIFO buffer is set in the data buffer module, and the full signal is transmitted to the clock management module for processing, and the dynamic debugging function can be realized. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic structural diagram of a debugging system according to an embodiment of the present invention; FIG. 2 is a schematic structural diagram of a core cluster according to an embodiment of the present invention; FIG. 3 is a schematic diagram of sampling a signal by a data collecting module according to an embodiment of the present invention; FIG. 5 is a schematic structural diagram of a data collection module according to an embodiment of the present invention; FIG. 6 is a schematic structural diagram of another embodiment of the debugging system according to an embodiment of the present invention; FIG. 8 is a schematic structural diagram of a clock management module according to an embodiment of the present invention; FIG. 9 is a schematic structural diagram of a bus bridge according to an embodiment of the present invention; FIG. 10 is a flowchart of a debugging method according to an embodiment of the present invention; . BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be further described in detail by way of specific embodiments with reference to the accompanying drawings. The debugging system described in this embodiment, as shown in FIG. 1, includes: a core cluster, a data pool, a data acquisition module, a data transmission module, a clock management module, and a debugging processing module, and the six modules cooperate to complete debugging, wherein: Including at least one IP core, the IP core includes at least one integrated component; the clock management module is configured to generate a clock signal to drive the integrated component and the data acquisition module in the IP core; and the data acquisition module is configured to acquire data of the integrated component in the IP core. Sampling data, and transmitting the sampling data to the debugging processing module through the data transmission module; the debugging processing module is configured to process the received sampling data, and generate corresponding debugging data to be transmitted to the data pool through the data transmission module; the data pool is set to The debug data is processed and the processed data is loaded into the input of the corresponding integrated component. The debugging system of this embodiment can debug various integrated circuits and compare the debugging of the SOC chip. The core cluster is the debug tracking object of the embodiment. The composition of the core cluster is flexible, including multiple IP cores, wherein multiple integrated components can be integrated in the IP core. Taking the SOC chip as an example, an IP core can include 4 CPUs or Four DSPs can also include CPU, DSP or hardware accelerators. The integrated components within the IP core can be one or more of a CPU, DSP, or hardware accelerator; the number and variety of CPUs, DSPs, and hardware accelerators are not limited. The CPU and the DSP may be IP cores provided by the manufacturer, or may be self-developed IP cores; the hardware accelerator refers to a logic circuit that the manufacturer provides or self-develops to perform a certain function. These CPUs, DSPs, and hardware accelerators can or do not support interrupts. As shown in FIG. 2, the core cluster includes an IP core including: IP0-IPti, and a clock signal of the clock management module is loaded at a clock input end of each IP core. When the clock management module controls the IP core and the data sampling module to work, the data sampling module receives the data transmitted by the IP core (which can be preset by the clock management module to control the IP core), and the data acquisition module will The sampling data is transmitted to the debugging processing module; the debugging processing module processes the sampling data to generate corresponding debugging data and transmits the data to the data pool; the data pool processes the debugging data and loads it into the corresponding IP core. The clock management module makes it easy to manage and maintain the stability of the commissioning. The clock management module of this embodiment is used to manage the operation of the core, and the generated clock signal is used as an enable signal to the IP core, and the IP core operates under the clock of the clock management module. The same data acquisition module is also in the clock management module. The specific sampling process is shown in Figure 3. Elk is the clock for the normal operation of IP_cl _US t _er . clk_gated is the output of the clock management module and is used to manage the operation of the core. On each rising edge of clk_gated, the core runs a clock, and then the output is sent to the data sampling module. The data sampling module drives the sampled N data one by one under the driving of elk to obtain a stable sampled data stream. And send it to the debug processing module for processing. The above debug data may include at least one of: load data and command parameter configuration data. When the debug data is loaded data, the data pool performs data format conversion on the load data according to a predefined format, and loads the converted data on the input of the integrated component. When the debug data is configured as command parameters, the data pool will parse the command parameter configuration data and distribute the parsed data to the corresponding integrated component. If the data transmitted from the debug processing module to the data pool is referred to as downlink data, the data transmitted from the data sampling module to the debug processing module is referred to as uplink data. The data pool is responsible for processing the downlink data. For example, according to the MSB of the data, the data type is determined. As shown in FIG. 4, the downlink data bit width is N+1 bits. If data[N] is l 'b0, it indicates that data[Nl :0] is the IP_cluster load data, the data pool will load the data into the IP_cluster input according to the predefined format; if the data[N] is ΓΜ, it indicates that the data[Nl:0] is the commissioning command parameter configuration. The data is parsed and the processed data is transferred to the corresponding integrated component in the corresponding IP (such as the first CPU in IP0, the second DSP in IP1, etc.). As shown in FIG. 5, in order to test specific or user-interested data according to user requirements, the data acquisition module in this embodiment includes a multiplexer and a control register; wherein the multiplexer receives the core cluster transmission The data, the control register generates a control signal to the multiplexer according to the configuration of the data pool, and the multiplexer selects corresponding data according to the control signal for output. For example, a core cluster consisting of three IP cores, IP0 includes 2 CPUs (CPU1, CPU2), IP1 includes 3 DSPs (DSP1, DSP2, DSP3), IP2 includes one CPU (CPU3), one DSP ( DSP4) and a hardware accelerator; the user only needs to debug the first CPU in the IPO, the second DSP in IP1 and the hardware accelerator in IP2, the specific process is as follows: Multiple selectors receive IP0, IP1 and D2, dl, d2, d3, d4, d5, d6, d7 data of IP2 transmission, d0, dl are the output data of 2 CPUs (CPU1, CPU2) in IPO, d2, d3, d4 are three DSPs in IP1 ( DSP1, DSP2, DSP3) output data, d5, d6, d7 are the output data corresponding to the three integrated components of CPU3, DSP4, and hardware accelerator in IP2; the data pool configures the control register to generate CPU1, DSP2, hardware The control signal of the accelerator, after receiving the control signal, the multi-selector receiver selects d0, d3, d7 data from d0, dl, d2, d3, d4, d5, d6, d7 for output. In the implementation of the debugging process, the data transmission module in the embodiment includes: a data cache module and a bus bridge; the data cache module is configured to cache the data module under the driving of the clock management module. The output sample data and the debug data generated by the debug processing module; the bus bridge is configured to transfer data between the data cache module and the debug processing module driven by the clock management module. The data pool reads the debug data from the data cache module, and the data acquisition module caches the collected data to the data cache module to debug the SOC chip as an example. The schematic diagram of the debug system is shown in FIG. 6 , wherein the core cluster, Clock management module The block, data pool, data acquisition module, data cache module, and bus bridge are all on the chip, and the debug processing module is located off-chip. As shown in FIG. 7, in order to enable the debugging system to implement the dynamic debugging function, the data buffering module includes a first FIFO data buffer and a first FIFO buffer controller; and the first FIFO buffer controller is configured to control the first FIFO data. The buffer buffers and outputs the sampled data; the first FIFO data buffer is configured to buffer the sampled data output by the data module under the driving of the clock management module, and when the full signal is generated, the full signal is transmitted to the clock management module The clock management module is also arranged to turn off the corresponding integrated component according to the full signal. The full signal of the upstream FIFO (alm _0S t_full) needs to be connected to the clock management module to prevent the upstream FIFO from overflowing due to the small bus transmission speed, thus preventing the uplink data from being lost; the full signal needs to be controlled in the clock management module, in the uplink When the FIFO data is about to overflow, when the almost_full is valid, the core clock is pulled to a fixed level (that is, the integrated component corresponding to the clock is turned off), and when the almost_foll is invalid, the core clock is released, thereby realizing dynamic debugging of the core. As shown in FIG. 7, in order to prevent the downlink load data from being lost due to the bus speed being too high, the data cache module further includes a second FIFO data buffer and a second FIFO buffer controller; and the second cache controller is configured to control the second FIFO data buffer. Debugging and outputting the debug data; the second FIFO data buffer is set to buffer the debug data under the driving of the clock management module, and when the full signal is generated, the full signal is transmitted to the debug processing module; the debug processing module is also set Stop transmitting debug data to the second FIFO data buffer after receiving the full signal. The full signal of the downstream FIFO (alm _0S t_foll) is used to prevent loss of configuration data or load data when the bus rate is too high. This signal needs to be connected to the bus bridge. The bus bridge transmits the full signal of the downlink FIFO to the debug processing module through the bus. The debug processing module receives the signal that the downlink FIFO is full, stops sending the debug data to the data cache module, and waits for Continue to send after the full signal fails. As shown in FIG. 8, the clock management module in this embodiment may be composed of clock gating management (clk_gate_ctrl), latch and AND gate; the gating management unit is controlled by the counting configuration register (cnt_config_reg) and almost_full. The counting configuration register can be dynamically configured by datajx) ₀ l, thereby controlling the running rate and sampling rate of the core, thereby controlling the overall speed of the commissioning. Almost_foll is used to lock the core when the upstream FIFO is full to prevent upstream data from overflowing. As shown in FIG. 9, the bus bridge in this embodiment may include: a bus bridge and a bus external interface. Through the diversification of the external interface, the on-chip to off-chip data transmission can be diversified, and various debugging processing modules corresponding to the interface can be satisfied. The bus bridge selection method is more flexible. Which bus is selected should be selected according to the size of the chip, the number and size of the signals to be tested, and the minimum commissioning time of each chip. The bus can be used with a variety of standard buses or custom buses. In order to speed up the progress involved, it is recommended that the bus external interface module use an off-the-shelf IP core. The bus bridge needs to be designed separately according to the type of bus. The above debugging processing module can be a debugging tracker, and the debugging tracker is an interface between the human and the chip, and has the following functions: parameter setting function; parameter conversion into standard format function; extracting simulation waveform, converting it into standard debugging format Function; It has the function of saving the sampled data; It can perform the waveform recovery function according to the configuration parameters; It has the function of real-time waveform; It can compare the measured waveform with the simulated waveform. The following functions can be implemented by the above-described debugging system of the present invention:

(1) Solved the problem of multiple DSP, CPU, and hardware accelerators on the current multi-core heterogeneous SOC;

(2) The external debugging interface has diversity, which solves the problem of few types of debugging interfaces and speed mismatches;

(3) The method of gated clock is used to improve the commissioning speed of the system; (4) The method of recovering the commissioning data is proposed, which solves the problem of real-time waveform reconstruction;

(5) The existing waveform can be converted into a commissioning loading signal, which enhances the debugging capability of the system;

(6) Added real-time waveform and simulation waveform comparison function for real-time error detection. Corresponding to the above debugging system, the embodiment further provides a debugging method. As shown in FIG. 10, the method includes the following steps: Step 101: Acquire at least one integrated component in at least one IP core in the core cluster driven by the clock management module. The data obtains the sampled data; Step 102: Process the sampled data to generate corresponding debug data; Step 103: Process the debug data, and load the processed debug data into the input of the corresponding integrated component. Further, after the data of the at least one integrated component in the at least one IP core in the core cluster is collected in step 101, before step 102, the method further comprises: selecting corresponding sampling data according to the received control signal. Further, the debugging data includes at least one of loading data and command parameter configuration data. The processing of the debugging data in step 103 specifically includes: performing predetermined data format conversion on the loading data, and/or parsing the command parameter configuration data. . The above is a further detailed description of the present invention in connection with the specific embodiments, and the specific implementation of the invention is not limited to the description. It will be apparent to those skilled in the art that the present invention may be made without departing from the spirit and scope of the invention.

Claims

Claim

A debugging system, comprising: a core cluster, a data pool, a data acquisition module, a data transmission module, a clock management module, and a debugging processing module; the core cluster includes at least one IP core, and the IP core includes at least one integrated component The clock management module is configured to generate a clock signal to drive the integrated component in the IP core and the data acquisition module to work; the data acquisition module is configured to collect data of the integrated component in the IP core to obtain sampling data, and And transmitting, by the data transmission module, the debugging processing module; the debugging processing module is configured to process the received sampling data, and generate corresponding debugging data to be transmitted to the office through the data transmission module. The data pool is configured to process the debug data and load the processed data to an input of the corresponding integrated component.

2. The debugging system of claim 1, wherein the debug data comprises at least one of: load data and command parameter configuration data; the data pool is configured to perform a predetermined data format conversion on the load data, and / / Analyze the command parameter configuration data.

3. The debugging system of claim 2, wherein the data acquisition module comprises: a multiplexer and a control register; the control register is configured to generate a control signal to the a multiplexer; the multiplexer is configured to select, according to the control signal, corresponding sampling data to be transmitted to the data transmission module.

The debugging system according to any one of claims 1 to 3, wherein the data transmission module comprises: a data cache module and a bus bridge; the data cache module is configured to be cached by the clock management module The sampling data output by the data module and the debug data generated by the debug processing module; the bus bridge is configured to transmit data between the data cache module and the debug processing module under the driving of the clock management module .

5. The debugging system of claim 4, wherein the data buffering module comprises a first FIFO data buffer and a first FIFO buffer controller; the first FIFO buffer controller being configured to control the first FIFO The data buffer buffers and outputs the sampled data; the first FIFO data buffer is configured to buffer the sampled data output by the data module under the driving of the clock management module, and when the full signal is generated, the full signal is to be Transmitting to the clock management module; the clock management module is further configured to turn off the corresponding integrated component according to the full signal. The debugging system of claim 5, wherein the data buffering module further comprises a second FIFO data buffer and a second FIFO buffer controller; the second cache controller is configured to control the second FIFO data buffer The buffer data is buffered and outputted; the second FIFO data buffer is configured to buffer the debug data under the driving of the clock management module, and when a full signal is generated, the full signal is transmitted to The debug processing module is further configured to stop sending debug data to the second FIFO data buffer after receiving a full signal. The debug system of claim 6, wherein the IP core comprises at least one integrated component of a CUP, a DSP, and a hardware accelerator. A debugging method that includes the following steps:

Acquiring data of at least one integrated component in at least one IP core in the core cluster to obtain sampling data, driven by a clock management module;

Processing the sampled data to generate corresponding debug data;

The debug data is processed, and the processed debug data is loaded into the input of the corresponding integrated component. The debugging method according to claim 8, wherein, after the collecting data of the at least one integrated component of the at least one IP core in the core cluster, before processing the collected data, the method further comprises:

Corresponding sampling data is selected according to the received control signal. The debugging method according to claim 9, wherein the debug data includes at least one of: load data and command parameter configuration data;

The processing the debugging data specifically includes:

Performing a predetermined data format conversion on the load data, and/or parsing the command parameter configuration data.