CN105245398A - Multichannel parallel detection system for massive LOC (Lab-on-Chip) signal processing - Google Patents
Multichannel parallel detection system for massive LOC (Lab-on-Chip) signal processing Download PDFInfo
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Abstract
The invention provides a multichannel parallel detection system for massive LOC (Lab-on-Chip) signal processing, which comprises clients, a host and a signal processing accelerator, wherein the clients are used for carrying out packaging processing on data acquired by a porous silicon micro resonant cavity sensor and a spectrometer, and data packets are obtained to serve as to-be-detected data; the host is used for sequentially serially transmitting the to-be-detected data from the multiple clients to the signal processing accelerator for signal feature detection, and a detection result obtained by the signal processing accelerator is fed back to a corresponding client; and the signal processing accelerator is used for carrying out signal feature detection on the to-be-detected data. The to-be-detected data with different data lengths and signal-to-noise ratios can be processed, applicability is good, the whole system has good extensibility and computing efficiency, and in addition, the system based on cloud can provide support for storage of future possible massive data.
Description
Technical field
The present invention relates to multi-channel parallel detection system, particularly, relate to a kind of multi-channel parallel detection system towards magnanimity LOC signal transacting.
Background technology
Micro-fluidic chip, also chip lab (Lab-on-Chip is claimed, LOC), be considered to one of 21 century most important front line science technology, this chip apparatus can on the micro-fluidic chip of a piece several square centimeters, construct complicated microchannel network, and fluid (sample or reagent) is wherein handled accurately and controlled, complete different biological or chemical courses of reaction, a large amount of biomolecule can be analyzed at short notice, bulk information in Obtaining Accurate sample, amount of information is hundreds and thousands of times of traditional detection means, at chemistry, revolutionary impact is caused in the fields such as medicine and life science.
The same success of LOC is in biological field.Enter 21 century from generation nineteen ninety, many outstanding achievements are converted the product in order to there be practical application, as optical biosensor.In order to improve the sensitivity of optical biosensor, researcher proposes to use porous material to increase surface area.After introducing porous material, more molecule can be adhered to, make limited decaying wave energy and more interaction of molecules, thus improve sensitivity.
Although porous silica microsphere resonant cavity optical biosensor is widely used, but design towards the porous silica microsphere resonant cavity of different application and processing are mainly partial in current research, application number be 201080022885.5 patent of invention disclose the process equipment of fluid stream in laboratory system on a kind of control strip, application number is that the patent of invention of 201080022886.X discloses a kind of valve and a kind of method for control valve.The data volume that sensors with auxiliary electrode gathers is less, and the determination and analysis of data all completes in transducer this locality.
On the other hand, signal processing system based on FPGA is also extensively studied, the patent of invention being 201010165660.7 as application number discloses a kind of platform based on FPGA processed electrocardiosignal, can effective promotion signal disposal ability, application number be 201010135630.1 patent of invention disclose a kind of restructural signal-processing board based on FPGA, improve throughput.But existing invention fails to tackle the demand of magnanimity signal transacting.
From the angle of future development, along with the design of porous silica microsphere resonant cavity optical biosensor and the maturation of technology of preparing, it is bound to be widely used in the field such as environmental monitoring, biomedical detection.To in application scenarios as detected in water quality monitoring and tele-medicine of the Real-Time Monitoring of environment, need to adopt a large amount of transducers, and can produce the signal data to be detected of magnanimity, sensor side may not possess process and the analysis ability of data simultaneously.
Summary of the invention
For defect of the prior art, the object of the invention is to: a kind of multi-channel parallel detection system towards magnanimity LOC signal transacting is provided, utilize the signal accelerator based on FPGA to tackle effectively and efficiently the processing demands of magnanimity signal.
In actual application scenarios, such as real time environment monitoring and tele-medicine detect, and will produce the signal of magnanimity, and sensor side not necessarily possesses local data processing and the ability of analysis.In addition, under the background of mass data, be separated independently feature detection analysis between sensing data and can only obtain limited information, and the potential rule existed between data and contact are crucial often.The present invention carrys out Design and implementation based on such application background.The acquisition and processing of data is separated by this system, has good versatility, extensibility and calculates usefulness, and for follow-up further data treatment and analysis such as data relation analysis provide convenient with support.
According to a kind of multi-channel parallel detection system towards magnanimity LOC signal transacting provided by the invention, comprise as lower device:
Client: for porous silica microsphere resonator sensor and spectrometer collection to data carry out packing process, obtain packet as data to be tested;
Main frame: for the data to be tested from multiple client successively serial transmission to be carried out the detection of signal characteristic to signal transacting accelerator, and the testing result that signal transacting accelerator draws is fed back to corresponding client;
Signal transacting accelerator: for carrying out the detection of signal characteristic to described data to be tested.
Preferably, client first uploads the data length of data to be tested corresponding data bag before uploading data to be tested to main frame, and main frame returns this data length to client after receiving data length; Client just starts to upload data to be tested after the correct data length receiving main frame return; Host side after receiving data to be tested by whether consistent with the data length uploaded before client upload data to be tested for the actual data length the received integrality detecting data to be tested, if consistent, think that the data to be tested of client upload are complete, otherwise, think incomplete; If it is incomplete that data to be tested occur, then main frame requires that client retransmits data to be tested.
Preferably, described signal transacting accelerator is realized by on-site programmable gate array FPGA, and described signal transacting accelerator comprises PCIExpressEndpoint module, data FIFO, task allocating module, feature detection module, testing result write back moderator and result FIFO;
Described PCIExpressEndpoint module, i.e. PCIExpress destination node module, for the communication between responsible main frame and signal transacting accelerator, the data that main frame transmits also are written in data FIFO by the data that Receiving Host transmits;
Described data FIFO, i.e. data First Input First Output are the data transmission interfaces between PCIExpressEndpoint module and task allocating module;
Described task allocating module, for finding an idle feature detection module to carry out the check processing of the signal characteristic of data for each group data to be tested;
Described feature detection module, for carrying out the detection of resonance paddy to data, obtains testing result;
Described testing result writes back moderator, for making feature detection module be written in result FIFO by testing result in an orderly manner, avoids occurring competition;
Described result FIFO, i.e. result First Input First Output, for as the data-interface between PCIExpressEndpoint module and feature detection module group.
Preferably, the handling process of one group of data to be tested in signal transacting accelerator is as follows:
After data are from Host Transfer to signal transacting accelerator, PCIExpressEndpoint module is by the whole one-time write of data that receives in data FIFO, and data will be waited in data FIFO; If available free feature detection module, then data will be read from data FIFO by task allocating module, and be transferred to idle feature detection module; Feature detection module carries out the detection of resonance paddy to data, produces to write back moderator to testing result after testing result and submit write request to result FIFO, is written in result FIFO after authorized by testing result; PCIExpressEndpoint module reads testing result from result FIFO, and testing result is passed to main frame.
Preferably, each feature detection module can export a useful signal valid to characterize self current operating state state;
When the useful signal valid that feature detection module exports is 1, represents that this feature detection module is in idle condition, can data to be tested be accepted;
When the useful signal valid that feature detection module exports is 0, represents that this feature detection module is carrying out the feature detection of data, can not data to be tested be accepted;
The data processing task distribution mechanism of task allocating module is: the data FIFO between PCIExpressEndpoint module and task allocating module is not for time empty, show currently have data to need to carry out feature detection, task allocating module just carries out poll to the operating state state of feature detection module group from highest order to lowest order, find first be 1 that position, then this characteristic of correspondence detection module reads the data in data FIFO;
Wherein, described feature detection module group is made up of all feature detection module, be specially, the operating state state of feature detection module group is the binary number of a N position, wherein N is the number of feature detection module, the operating state state of feature detection module group is made up of the useful signal valid of all feature detection module, each correspondence of the operating state state of feature detection module group feature detection module.
Preferably, the packet header of described packet comprises client id number, and wherein, client id number determines the ownership client of result data when client returns result data for main frame.
Compared with prior art, the present invention has following beneficial effect:
1, the present invention devises a kind of multi-channel parallel detection system towards magnanimity LOC signal transacting, and utilizes FPGA as data processing accelerator module to realize the calculating of parallel high-speed.System can process the data to be tested with different data lengths and signal to noise ratio, has good applicability.Whole system also has good extensibility and calculates usefulness simultaneously.In addition, the system based on cloud can provide support for the storage of mass data possible in the future.
2, signal transacting accelerator adopts a kind of streaming structure based on FIFO.This structure is different from the structure of traditional embedded system, and do not have processor, Large Copacity internal memory and bus, save hardware resource in a large amount of sheet, the design for user logic provides larger space.In addition, signal transacting accelerator is with good expansibility, and along with the increase of PCIExpressEndpoint data transfer bandwidth, can throughput be made to keep the state of optimum by integrated more feature detection module in accelerator.
3, mass data feature detection module is dynamic and configurable, has good applicability.Mass data feature detection module is not that it is applicable to the data to be tested of different data lengths for the data of certain particular data length and signal to noise ratio realize.In system operation, revise configuration register, different down-sampled rates is set and mean filter window long, different noise reductions can be provided for the data of different signal to noise ratio.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is magnanimity LOC signal transacting multi-channel parallel detection system structural representation;
Fig. 2 is the collection schematic diagram of porous silica microsphere resonator sensor reflectance spectrum signal;
Fig. 3 is data to be tested pack arrangement schematic diagram;
Fig. 4 is the high-level schematic functional block diagram of signal accelerator;
Fig. 5 is PCIExpressEndpoint module interface schematic diagram;
Fig. 6 is the synchronous schematic diagram of State signal cross clock domain;
Fig. 7 is the block diagram representation of feature detection module.
In figure:
1-tungsten halogen lamp
2-spectrometer
3-waste liquid
4-glucose solution
5-PsiMC transducer
6-peristaltic pump
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.Following examples will contribute to those skilled in the art and understand the present invention further, but not limit the present invention in any form.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, some changes and improvements can also be made.These all belong to protection scope of the present invention.
The invention discloses a kind of multi-channel parallel detection system towards magnanimity LOC signal transacting, it uses porous silica microsphere resonator sensor and spectrometer collection mass data, is sent to client rs PC; Client rs PC is utilized to carry out packing process to the mass data collected; Main frame accepts the data to be tested from multiple client, and these data successively serial must be passed to the detection that signal transacting accelerator carries out signal characteristic, Received signal strength processor accelerator is drawn testing result and is fed back to corresponding client by main frame simultaneously; The mass data to be detected obtained is input to signal transacting accelerator, completes the feature detection of signal data to be detected; Main frame is transmitted back from signal transacting accelerator by detecting the data obtained.
Particularly, according to a kind of multi-channel parallel detection system towards magnanimity LOC signal transacting provided by the invention, comprise as lower device:
Client: for porous silica microsphere resonator sensor and spectrometer collection to data carry out packing process, obtain packet as data to be tested;
Main frame: for the data to be tested from multiple client successively serial transmission to be carried out the detection of signal characteristic to signal transacting accelerator, and the testing result that signal transacting accelerator draws is fed back to corresponding client;
Signal transacting accelerator: for carrying out the detection of signal characteristic to described data to be tested.
Preferably, client first uploads the data length of data to be tested corresponding data bag before uploading data to be tested to main frame, and main frame returns this data length to client after receiving data length; Client just starts to upload data to be tested after the correct data length receiving main frame return; Host side after receiving data to be tested by whether consistent with the data length uploaded before client upload data to be tested for the actual data length the received integrality detecting data to be tested, if consistent, think that the data to be tested of client upload are complete, otherwise, think incomplete; If it is incomplete that data to be tested occur, then main frame requires that client retransmits data to be tested.
Preferably, described signal transacting accelerator is realized by on-site programmable gate array FPGA, and described signal transacting accelerator comprises PCIExpressEndpoint module, data FIFO, task allocating module, feature detection module, testing result write back moderator and result FIFO;
Described PCIExpressEndpoint module, i.e. PCIExpress destination node module, for the communication between responsible main frame and signal transacting accelerator, the data that main frame transmits also are written in data FIFO by the data that Receiving Host transmits;
Described data FIFO, i.e. data First Input First Output are the data transmission interfaces between PCIExpressEndpoint module and task allocating module;
Described task allocating module, for finding an idle feature detection module to carry out the check processing of the signal characteristic of data for each group data to be tested;
Described feature detection module, for carrying out the detection of resonance paddy to data, obtains testing result;
Described testing result writes back moderator, for making feature detection module be written in result FIFO by testing result in an orderly manner, avoids occurring competition;
Described result FIFO, i.e. result First Input First Output, for as the data-interface between PCIExpressEndpoint module and feature detection module group.
Preferably, the handling process of one group of data to be tested in signal transacting accelerator is as follows:
After data are from Host Transfer to signal transacting accelerator, PCIExpressEndpoint module is by the whole one-time write of data that receives in data FIFO, and data will be waited in data FIFO; If available free feature detection module, then data will be read from data FIFO by task allocating module, and be transferred to idle feature detection module; Feature detection module carries out the detection of resonance paddy to data, produces to write back moderator to testing result after testing result and submit write request to result FIFO, is written in result FIFO after authorized by testing result; PCIExpressEndpoint module reads testing result from result FIFO, and testing result is passed to main frame.
Preferably, each feature detection module can export a useful signal valid to characterize self current operating state state;
When the useful signal valid that feature detection module exports is 1, represents that this feature detection module is in idle condition, can data to be tested be accepted;
When the useful signal valid that feature detection module exports is 0, represents that this feature detection module is carrying out the feature detection of data, can not data to be tested be accepted;
The data processing task distribution mechanism of task allocating module is: the data FIFO between PCIExpressEndpoint module and task allocating module is not for time empty, show currently have data to need to carry out feature detection, task allocating module just carries out poll to the operating state state of feature detection module group from highest order to lowest order, find first be 1 that position, then this characteristic of correspondence detection module reads the data in data FIFO;
Wherein, described feature detection module group is made up of all feature detection module, be specially, the operating state state of feature detection module group is the binary number of a N position, wherein N is the number of feature detection module, the operating state state of feature detection module group is made up of the useful signal valid of all feature detection module, each correspondence of the operating state state of feature detection module group feature detection module.
Preferably, the packet header of described packet comprises client id number, and wherein, client id number determines the ownership client of result data when client returns result data for main frame.
The described multi-channel parallel detection system towards magnanimity LOC signal transacting, can be realized by a kind of multi-channel parallel detection method towards magnanimity LOC signal transacting.Those skilled in the art by the multi-channel parallel detection method towards magnanimity LOC signal transacting, can be interpreted as a described embodiment towards the multi-channel parallel detection system of magnanimity LOC signal transacting.Particularly, the described multi-channel parallel detection method towards magnanimity LOC signal transacting, comprises the following steps:
Step S1: use porous silica microsphere resonator sensor and spectrometer collection data, and be sent to client rs PC.
Wherein, the porous silica microsphere resonator sensor and the spectrometer that are positioned at client are responsible for the collection of data and the transmission of data.Each client can gather reflectance spectrum signal data for determination and analysis independently by spectrometer, as shown in Figure 2.
Step S2: utilize client rs PC to carry out packing process to the data collected.
After obtaining data to be tested, client can carry out preliminary treatment to data, adds packet header and bag tail.There are two data in packet header, first data marked the client id number belonging to these data, main frame energy Quick when returning result data to client is made to go out the ownership client of result data, second number it was noted the numerical value of configuration register in feature detection algorithm hardware circuit implementation (feature detection module), for the function of the down-sampled and mean filter in dynamic conditioning hardware circuit.Because dissimilar spectrometer has different sample rates, the data collected also just have different length, by add at data handbag tail 0x00 (there will not be in spectral signature data reflectivity be 0 situation) judge the end of a packet as the end mark task allocating module of helping in signal transacting accelerator system of data and the data processing task be switched to next time distributes.As shown in Figure 3.
Step S3: main frame is collected and feedback data.
The Main Function of main frame is exactly the terminal of data.Main frame receives data to be tested from multiple client, and these data are passed to the detection that signal transacting accelerator carries out signal characteristic successively serially, simultaneously the testing result that drawn by Received signal strength processor accelerator of main frame returned to corresponding client.
Due to the restriction of the network bandwidth and the unsteadiness of network, may there is packet loss to the process of main frame uploading data in Terminal Server Client.The loss of data packet head or bag tail can cause the logic error of hardware circuit.In order to avoid this situation, in the communication of client and main frame, add the verification to data integrity.The data length of the first uploading data bag of meeting before client upload data to be tested bag, main frame can return this data to client after receiving data length.Client just can start to upload data to be tested bag after the correct data length receiving main frame return.Host side need after receiving data by the actual data length received with before the data length that confirms compare the integrality detecting data.As there is packet loss, main frame can require client data retransmission.
Step S4: utilize signal transacting accelerator to carry out feature detection.
Signal transacting accelerator main task has been exactly the feature detection of signal data to be detected.Communication between signal transacting accelerator and main frame is by PCIExpress protocol realization.PCIExpress has high transmission bandwidth, can make to have very high data throughput between main frame and signal accelerator, realizes transfer of data at a high speed.
The handling process of one group of data to be tested in signal transacting accelerator is as follows: when after the signal transacting accelerator in data are from Host Transfer to FPGA, PCIExpressEndpoint module can whole one-time write be in data FIFO by the data received, and data can be waited in data FIFO.If available free feature detection module, data will be read from data FIFO by task allocating module, and be transferred to idle feature detection module.Feature detection module carries out the detection of resonance paddy to data, and the backward testing result born results writes back moderator and submits write request to result FIFO, writes results in result FIFO after authorized.
Signal transacting accelerator in step S4 is primarily of 6 main module compositions: PCIExpressEndpoint module, data FIFO, task allocating module, feature detection module, testing result write back moderator and result FIFO:
1, PCIExpressEndpoint module
PCIExpress standard is followed in the communication of PCIExpress link.In the hierarchical structure of PCIExpress bus, RootComplex can connect multiple PCIExpressEndpoint by direct-connected or switch on the point-to-point link of all PCIExpress.In addition, RootComplex is also responsible for bus structures and the connection between CPU and main memory.
In FPGA, physical layer and data link layer interface just use in inside, and the interface of transport layer is used to be connected with user's hardware.Such embedded system usually also with bus as AMBA, AXI and jumbo internal memory module, this just causes whole embedded system to need a large amount of Resources on Chips, also just limits the used resource of User-defined logic simultaneously.For the design in the present invention, little for the data scale of feature detection, so data to be tested do not need first to concentrate in the mass storage be buffered in sheet, this also just avoids and uses mass storage in sheet.The data processing method of what design in addition in the present invention needed to realize is a kind of Fast Flow, we wish that data to be tested are sent to after in FPGA by PCIExpress can distribute to the detection analysis that feature detection module carries out resonance paddy as early as possible.Based on above 2 points, in the design of signal accelerator, have employed a kind of streaming structure based on FIFO, and using FIFO as the data-interface between PCIExpress and task allocating module and between PCIExpress and feature detection module.
2, data FIFO
Better flexibility, freedom and possibility can be brought for the design of user logic module using FIFO as the data communication interface of PCIExpressEndpoint and other intermodules.User logic module can use the data bit width of the clock frequency different from PCIExpressEndpoint and different input/output interfaces.Relative to other communication interface implementations, user logic module can have more Resources on Chip to use, and makes more complicated user logic become possibility like this.
3, task allocating module
The major function of task allocating module the data to be tested that PCIExpressEndpoint module receives is distributed to the detection that an idle feature detection module carries out characteristic point, ensure each moment from PCIExpressEndpoint module to feature detection module group a data path of an existence anduniquess.Task allocating module determines the data processing bandwidth of whole interior signal-data processing accelerator to a certain extent to the distribution mechanism of data processing task and efficiency, so a reasonable effective Mechanism of Task Allocation is vital.
A valid signal can be exported to characterize current operating state state about having described each feature detection module in the description of the Design and implementation of feature detection module above.When the valid signal that feature detection mould exports is 1, represents that this feature detection module is in idle condition, can data to be tested be accepted.And represent that when valid signal is 0 this feature detection module is carrying out the feature detection of data, can not data to be tested be accepted.The data processing task distribution mechanism of task allocating module is exactly that the operating state state of feature based detection module group designs.The operating state state of feature detection module group is the binary number of a N position, wherein N is the number of feature detection module in sheet, it is made up of the valid signal of all feature detection module, that is its each correspondence feature detection module.When FIFO between PCIExpressEndpoint module and task allocating module is not empty, show currently have data to need to carry out feature detection, task allocating module will carry out poll to state from highest order to lowest order, find first be 1 that position, its characteristic of correspondence detection module will read the data in data FIFO.
The working clock frequency of task allocating module is identical with PCIExpressEndpoint module, and it completes under self working clock frequency the reading of the operating state state of feature detection module group.But state is made up of the valid signal of all feature detection module, it produces and is under the operating frequency of feature detection module.This is two different clock frequencies, and that is state is the data-signal of a cross clock domain, needs the process carrying out data syn-chronization to avoid metastable issues.We use FIFO to solve state from slow clock zone to the data syn-chronization of fast clock zone, as shown in Figure 6.Using state FIFO also has a benefit, the bit wide of state signal is determined by the number of the feature detection module of Embedded, along with the expansion of systems axiol-ogy module scale in sheet, the bit wide of state signal also can increase thereupon, and FIFO can configure the data bit width of its read-write according to the applicable cases of reality, it is designed to system flexibly and brings good extensibility.Need when FIFO is empty, to its write state data, to upgrade the operating state of current signature detection module group.State data at FIFO for being immediately written into time empty, but can not need the spacing wave in 5 cycles of wait.Such design be in order to ensure each state more new capital be up-to-date state.
Task allocating module is not continuous print for the reading of data FIFO yet, all can have the pause in several cycle between every two groups of data to be tested.This time of pausing is that task allocating module is determining that idle feature detection module is to accept data.Can judge in task allocating module whether the data of reading in from data FIFO are end mark, if the data that current period reads in are end mark, illustrate one group of data to be tested by complete must read complete, need to be switched to next feature detection module to accept one group of new data, now halt signal suspend can be set high.To data FIFO read enable signal be by the spacing wave of data FIFO and control logic inside produce halt signal carry out NOR operation generation, once halt signal is set high, read enable signal will be set low, task allocating module will suspend the reading to data FIFO.Also be simultaneously write enable signal to feature detection module inside FIFO to the enable signal of reading of data FIFO, can ensure like this between the reading of data and write, to keep synchronous.After halt signal is set high, task allocating module meeting reading state FIFO, obtains the operating state of up-to-date feature detection module group, and comes data and the control signal of gating individual features detection module according to operating state.After the new feature detection module for receiving data to be tested is chosen, halt signal is set low, and task allocating module restarts to read data from data FIFO, this completes the distribution of a data processing task.The mode of this task matching only produces the pause in several cycle between the switching of data processing task, and the efficiency that overall task is distributed is still very high.
4, feature detection module
For the data with different signal to noise ratio that dissimilar spectrometer collects, feature detection module needs the window of down-sampled rate and mean filter can be regulated long and be applicable to different data lengths.
Feature detection module comprises 6 main functional modules: Bram memory, controller module, down-sampled module, mean filter module, first stage detection module, second stage detection module.
Bram memory is used for the total data required for storage feature point detection.
Down-sampled module completes the down-sampled process to described total data.
Mean filter module carries out filtering and noise reduction to the data after down-sampled, makes for data to be detected enough level and smooth.
The first stage that first stage detection module corresponds in detection method is detected, major function finds out the approximate location of resonance paddy, first can find out and correspond to troughs all on the smoothed curve of the data smoothly, then find the trough in all troughs with maximum reflectivity.
The second stage that second stage detection module corresponds in detection method detects, and on the basis of first stage testing result, finds the exact position of resonance paddy in one section of interval range centered by the described trough with maximum reflectivity.
Controller module is a most important part in whole feature detection module, and the control signal that it produces other modules comprises the read/write address of Bram memory, the enable signal etc. of read/write enable signal, two detection modules.Controller module controls the workflow of whole feature detection module.
5, result writes back moderator
The major function that result writes back moderator makes feature detection module group must write in result FIFO by testing result in order exactly, if when having two or more feature detection module to ask write-back result simultaneously, authorize successively by the order of prior agreement, and by the data of authorized feature detection module with write the enable corresponding port being connected to result FIFO.
If all feature detection module are all that the data processing cycle number of so each feature detection module is identical for the data to be tested of same data requirement are disposed.Data to be tested are that serial must be assigned to feature detection module, so any two feature detection module can not start the check processing of data simultaneously, the time obtaining testing result is also different.Do not have two or more feature detection module when like this testing result being write back to result FIFO to compete simultaneously.Dispose if feature detection module is the data to be tested for having different pieces of information specification, data processing cycle number so for the feature detection module of different pieces of information specification data to be tested is different, although this just may cause the start time of two or more feature detection module Data Detection different, but terminate at synchronization, need to write testing result to result FIFO, this will cause race hazard simultaneously.The Limited Number of the feature detection module that institute's energy is integrated in current FPGA plate, as long as ensure that upper testing result once was written in result FIFO by each feature detection module before obtaining new testing result.Based on above consideration, have employed a kind of design of fair poll moderator.Data point at least containing more than 1,000 in one group of data to be tested, such one group of data to be tested are written to feature detection module from data at least needs cycle of more than 1,000 to producing testing result, and inquire that a feature detection module only needs one to two cycles, so can meet completely before producing new testing result by this condition of old testing result write result FIFO.
Moderator is connected with all feature detection module, and its inside, primarily of two main submodules, is respectively write request FIFO and polling system (PollingCtrl) module.In write request FIFO stored in be the data (N is the number of feature detection module) of a N position, be made up of the done signal of each feature detection module.The write signal of write request FIFO obtains by after the done signal of all feature detection module or operation.When asking FIFO non-NULL, polling logic reads FIFO.
Step S5: step S4 is detected the data obtained and transmits back main frame from signal transacting accelerator.
Result FIFO and data FIFO have identical function, and as the data-interface between PCIExpressEndpoint module and feature detection module group, PCIExpressEndpoint module reads testing result from result FIFO, and is passed to main frame.
Those skilled in the art will know that, except realizing except system provided by the invention and each device thereof in pure computer readable program code mode, system provided by the invention and each device thereof can be made to realize identical function with the form of gate, switch, application-specific integrated circuit (ASIC), programmable logic controller (PLC) and embedded microcontroller etc. by method step being carried out programming in logic completely.So system provided by the invention and every device thereof can be considered to a kind of hardware component, and to the structure that also can be considered as the device realizing various function in hardware component comprised in it; Also the device being used for realizing various function can be considered as not only can be implementation method software module but also can be structure in hardware component.
Above specific embodiments of the invention are described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, those skilled in the art can make a variety of changes within the scope of the claims or revise, and this does not affect flesh and blood of the present invention.When not conflicting, the feature in the embodiment of the application and embodiment can combine arbitrarily mutually.
Claims (6)
1. towards a multi-channel parallel detection system for magnanimity LOC signal transacting, it is characterized in that, comprise as lower device:
Client: for porous silica microsphere resonator sensor and spectrometer collection to data carry out packing process, obtain packet as data to be tested;
Main frame: for the data to be tested from multiple client successively serial transmission to be carried out the detection of signal characteristic to signal transacting accelerator, and the testing result that signal transacting accelerator draws is fed back to corresponding client;
Signal transacting accelerator: for carrying out the detection of signal characteristic to described data to be tested.
2. the multi-channel parallel detection system towards magnanimity LOC signal transacting according to claim 1, it is characterized in that, before client uploads data to be tested to main frame, first upload the data length of data to be tested corresponding data bag, main frame returns this data length to client after receiving data length; Client just starts to upload data to be tested after the correct data length receiving main frame return; Host side after receiving data to be tested by whether consistent with the data length uploaded before client upload data to be tested for the actual data length the received integrality detecting data to be tested, if consistent, think that the data to be tested of client upload are complete, otherwise, think incomplete; If it is incomplete situation that data to be tested occur, then main frame requires that client retransmits data to be tested.
3. the multi-channel parallel detection system towards magnanimity LOC signal transacting according to claim 1, it is characterized in that, described signal transacting accelerator is realized by on-site programmable gate array FPGA, and described signal transacting accelerator comprises PCIExpressEndpoint module, data FIFO, task allocating module, feature detection module, testing result write back moderator and result FIFO;
Described PCIExpressEndpoint module, i.e. PCIExpress destination node module, for the communication between responsible main frame and signal transacting accelerator, the data that main frame transmits also are written in data FIFO by the data that Receiving Host transmits;
Described data FIFO, i.e. data First Input First Output are the data transmission interfaces between PCIExpressEndpoint module and task allocating module;
Described task allocating module, for finding an idle feature detection module to carry out the check processing of the signal characteristic of data for each group data to be tested;
Described feature detection module, for carrying out the detection of resonance paddy to data, obtains testing result;
Described testing result writes back moderator, for making feature detection module be written in result FIFO by testing result in an orderly manner, avoids occurring competition;
Described result FIFO, i.e. result First Input First Output, for as the data-interface between PCIExpressEndpoint module and feature detection module group.
4. the multi-channel parallel detection system towards magnanimity LOC signal transacting according to claim 3, is characterized in that, the handling process of one group of data to be tested in signal transacting accelerator is as follows:
After data to be tested are from Host Transfer to signal transacting accelerator, PCIExpressEndpoint module is by the whole one-time write of data that receives in data FIFO, and data will be waited in data FIFO; If available free feature detection module, then data will be read from data FIFO by task allocating module, and be transferred to idle feature detection module; Feature detection module carries out the detection of resonance paddy to data, produces to write back moderator to testing result after testing result and submit write request to result FIFO, is written in result FIFO after authorized by testing result; PCIExpressEndpoint module reads testing result from result FIFO, and testing result is passed to main frame.
5. the multi-channel parallel detection system towards magnanimity LOC signal transacting according to claim 3, is characterized in that,
Each feature detection module can export a useful signal valid to characterize self current operating state state;
When the useful signal valid that feature detection module exports is 1, represents that this feature detection module is in idle condition, can data to be tested be accepted;
When the useful signal valid that feature detection module exports is 0, represents that this feature detection module is carrying out the feature detection of data, can not data to be tested be accepted;
The data processing task distribution mechanism of task allocating module is: the data FIFO between PCIExpressEndpoint module and task allocating module is not for time empty, show currently have data to need to carry out feature detection, task allocating module just carries out poll to the operating state state of feature detection module group from highest order to lowest order, find first be 1 that position, then this characteristic of correspondence detection module reads the data in data FIFO;
Wherein, described feature detection module group is made up of all feature detection module, be specially, the operating state state of feature detection module group is the binary number of a N position, wherein N is the number of feature detection module, the operating state state of feature detection module group is made up of the useful signal valid of all feature detection module, each correspondence of the operating state state of feature detection module group feature detection module.
6. the multi-channel parallel detection system towards magnanimity LOC signal transacting according to claim 1, it is characterized in that, the packet header of described packet comprises client id number, and wherein, client id number determines the ownership client of result data when client returns result data for main frame.
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