CN100458731C - Method for checking IC design with hardware logic - Google Patents
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Abstract
It's a method using a pair of hardware logic to verify IC design, including associated logic analyzer, hardware logic and external memory system. the method includes the following steps: (a) identify the target signal, and set the sampling clock and sampling depth, for generation test code to complete the sampling signal measurement and data transmission function; (b) synthesize and layout the function code and testing code to generate the configuration files, and download to the hardware logic; (c) input trigger signal to hardware logic signal and start the testing process, sample signals, transfer sampling data to external storage memory, then upload logic analyzer after sampling; (d) After sampling, read the preserved sample data from external memory, upload to a logic analyzer through the interface of the logic analyzer interface to follow-up analysis and processing.
Description
Technical field
The present invention relates to a kind of detection method, relate in particular to a kind of hardware logic method that design detects to IC that adopts.
Background technology
In the journey that adopts hardware logic checking IC designs such as FPGA, need observe the internal signal of hardware logic usually with logic analyser.A kind of verification method is the appliance id EDNTIFY that SYNPLILIFY company releases, these function codes and test code are generated configuration file through logic synthesis and wiring together, download to hardware logics such as FPGA, in test process, carry out signal sampling then and pass through JTAG (JTAG, Joint Test Action Group) interface being transferred to logic analyser (as PC) and analyzing.Boundary-scan test technology is the standard in the exploitation eighties in 20th century, is mainly used in the chip internal test.Most now high-grade device are all supported the JTAG agreement, as FPGA (FieldProgrammable Gate Array, field programmable gate array), CPLD (ComplexProgrammable Logic Device, CPLD) and EPLD (ErasableProgrammable Logic Device, Erasable Programmable Logic Device) etc.
Realize that the detection of FPGA internal signal must a storage that problem is a signal to be processed.Because JTAG is an interface that speed is very slow, so it can not be sent to the data that sample the PC end in real time.Common in the market way is the data storage that will the sample logical block to FPGA, be in the FPGA storer, by the time after sampling process finishes, again the data that sample are extracted from the FPGA storer, and be sent to demonstration of PC end and storage by the JTGA interface.
But, adopt said method only to be suitable for the semaphore and the lower environment of sampling depth that will detect.Big or when needing darker sampling depth when the semaphore that will detect, adopt said method often to need to expend a large amount of hardware logic resources such as FPGA.Therefore, in the project of hardware logic resources such as FPGA, adopt above-mentioned IDENTIFY method often not meet the cost requirement of design, therefore can't adopt than anxiety.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of detection method and system of hardware logic internal signal, can reduce the hardware logic resource occupation.
In order to address the above problem, the invention provides a kind of hardware logic method that design is verified to IC that adopts, be applied to comprise the system of the logic analyser, hardware logic and the external memory storage that link to each other successively, the method includes the steps of:
(a) signal that need to detect of sign, and given sampling clock and sampling depth generate and are used to finish the test code for the treatment of that detection signal is sampled and the sampled data that sampling obtains being transmitted;
(b) function code to be tested and described test code are carried out logic synthesis and wiring together, generate configuration file, and download to hardware logic;
(c) to the hardware logic input signal and start test process, to treat detection signal and sample, the sampled data that sampling is obtained is transferred to external memory storage and stores;
(d) after sampling finishes, the sampled data that is stored in described external memory storage is transferred to logic analyser by the interface with logic analyser carry out follow-up analysis and processing.
In addition, after described step (b) downloaded to the hardware logic platform with configuration file, described function code was corresponding to the module to be tested that generates in the hardware logic, and described test code is corresponding to the signal sampling module that generates in the hardware logic;
Described step (c) is further divided into following steps:
(c1) pumping signal of being scheduled to by the module input to be tested of man-machine interface in hardware logic of logic analyser, and start test process;
(c2) number of signals that detects as required of signal sampling module is distributed the temporary storage cell of hardware logic, and size is the bit number of the sampled data in the sampling clock cycle;
(c3) on the sampling clock edge, treat detection signal and sample the speed of the speed/sampling clock of the bit wide * external memory storage of the signal bit number=external memory storage that can sample simultaneously;
(c4) with same sampling clock along on the data storage that collects in the temporary storage cell of hardware logic;
(c5), in the cycle data batchwise transfer to the external memory storage of preserving in the described temporary storage cell is preserved at a sampling clock;
(c6) repeating step (c3) finishes until sampling to step (c5).
In addition, communicate by the JTAG jtag interface between described logic analyser and the hardware logic, and described logic analyser uses the JTAG man-machine interface.
In addition, described logic analyser is PC, and described hardware logic is a field programmable gate array, and described external memory storage is a synchronous DRAM.
In addition, the condition that sampling finishes in the described step (c6) is a kind of or combination in any in the following condition: the sampling depth that has satisfied appointment; The user forces the end signal sampling by the man-machine interface of logic analyser; The external memory storage insufficient space.
The present invention also provides a kind of hardware logic system that design is verified to IC that adopts, and comprises the logic analyser and the hardware logic that link to each other successively, it is characterized in that, also comprises the external memory storage that links to each other by interface with described hardware logic, wherein:
Described logic analyser comprises human-computer interface module and test interface, and this test interface links to each other with test access port on the hardware logic, is used for communicating by letter between logic analyser and the hardware logic; Described human-computer interface module is used to provide user's input test control command and signal, and gives the user with the data presentation that collects;
Comprise functional module to be tested, signal sampling module, test access port and external memory interface in the described hardware logic; Wherein the signal sampling module is used at test process the signal to be detected that the test function module generates being sampled, store the sampled data that samples into external memory storage earlier, read the sampled data of storage after sampling finishes again from external memory storage, test interface is uploaded to logic analyser.
In addition, the signal sampling module further comprises temporary storage area allocation units, sampling unit, sampled data preservation unit, external memory storage control module and data upload unit, wherein:
Described temporary storage area allocation units are used for the temporary storage cell according to number of signals distribution hardware logic to be detected, and its size is the bit number of the sampled data in the sampling clock cycle;
Described sampling unit, the signal to be detected that is used for treating in each sampling clock cycle the test function module carries out data sampling, and the sampled data that sampling obtains is kept in the described temporary storage cell;
Described sampled data is preserved the unit, is used for cooperating with the external memory storage control module, from described temporary storage cell the data that obtain in the sampling clock is delivered to external memory storage in batches;
Described external memory storage control module is used for by external memory interface external memory storage being carried out the control operation of reading of data;
Described data upload unit is used for after sampling process finishes, and by external memory storage control module reading of data from external memory storage, and by test access port these data is sent to logic analyser.
In addition, the test interface of described logic analyser is the JTAG jtag interface, and described logic analyser uses the JTAG man-machine interface.
In addition, described logic analyser is PC, and described hardware logic is a field programmable gate array.
In addition, described external memory storage is a synchronous DRAM.
The present invention can supply the SDRAM storer hardware logic direct access, the hardware logic outside by using, in the signal sampling process, the hardware logic internal signal data that sample are stored, and after signal sampling finishes, it is uploaded to the PC end, thereby realized reducing the purpose of hardware logic resource occupation, enlarged the scope of application of boundary-scan test tools.
Description of drawings
Fig. 1 is the structural representation that adopts embodiment of the invention system;
Fig. 2 is the process flow diagram of embodiment of the invention method.
Embodiment
Basic ideas of the present invention are, the internal signal data of the hardware logic that samples are kept in the outside SDRAM storer by the sdram interface in the hardware logic, after sampling finishes, again by sdram interface from the SDRAM storer with the internal signal data upload of above-mentioned hardware logic in PC.
Below in conjunction with accompanying drawing one embodiment of the present of invention are described in detail.
As shown in Figure 1, a kind of hardware logic system that design is verified to IC that adopts of present embodiment comprises PC end, FPGA platform and the SDRAM that links to each other successively.Wherein:
The PC end comprises JTAG human-computer interface module and jtag interface.TAP on jtag interface and the FPGA platform (Test Access Port, test access port) links to each other, be used for FPGA between communicate by letter; The JTAG human-computer interface module is used to provide user's input test control command and signal, as sampling initiation command, predetermined pumping signal etc., and can give the user with the data presentation that collects.
Comprise functional module to be tested, signal sampling module, TAP, synchronous DRAM (SDRAM) interface in the FPGA platform.
The jtag interface of TAP and signal sampling module and PC end links to each other, and is used to realize communicating by letter between FPGA and PC;
The signal sampling module is used for treating detection signal at test process samples, and stores the data that sample into outside SDRAM earlier, again from the sampled data of SDRAM reading and saving, is uploaded to PC by jtag interface after sampling finishes; This module further comprises:
The temporary storage area allocation units distribute the FPGA temporary storage cell according to number of signals to be detected, and its size is the bit number of the sampled data in the sampling clock cycle.For example, a sampling clock has the signal demand collection of 128 single-bit in the cycle, and then the size of FPGA temporary storage cell is 128 bits.
Sampling unit, the signal to be detected that is used for treating in each sampling clock cycle the test function module carries out data sampling, and the sampled data that sampling obtains is kept in the FPGA temporary storage cell.
Sampled data is preserved the unit, is used for cooperating with the SDRAM control module, from the FPGA temporary storage cell data that obtain in the sampling clock is delivered to the SDRAM storer in batches.
The SDRAM control module is used for by sdram interface the SDRAM storer being carried out the control operation of reading of data.
The data upload unit is used for after sampling process finishes, and by SDRAM control module reading of data from the SDRAM storer, and by TAP these data is sent to the PC end.
The part that relates to the data input and output in the above unit need be revised the IO defined file of FPGA.
Fig. 2 is the process flow diagram that present embodiment adopts the hardware logic method that design is verified to IC, comprises following steps:
Step 110: the signal that sign need to detect, and given sampling clock and sampling depth generate and are used to finish the sampling for the treatment of detection signal and the test code of data-transformation facility;
There has been similar test code Core Generator at present, as IDENTIFY.But, in the test code of the present invention with signal storage with to upload relevant part different with it, for example existing way is that the data that will collect deposit in earlier in the FIFO memory block among the FPGA, present embodiment then becomes the allocation of codes of above-mentioned FIFO memory block the storer of schedule of apportionment bit, and and for example present embodiment need increase the sdram controller logic section and grades.Specifically need the operation carried out can be referring to above to the detailed description of signal sampling functions of modules.
So-called logic synthesis promptly is by logic synthesis tool the test code of high level language and function code compiling to be mapped to the most basic logical block, as with door or door, d type flip flop, storage unit etc.Described wiring refers to use special wiring tool that the mode of these basic logic units by design coupled together, and generates configuration file.This configuration file is downloaded to FPGA to be cured to the logical circuit that these basic logic units are formed in the FPGA platform, at this moment, function code is corresponding to the module to be tested that generates among the FPGA, and test code is corresponding to the signal sampling module that generates in the FPGA platform.
Step 130: input signal and start test process in FPGA, treat detection signal and sample, and with the data storage that samples to outside SDRAM storer;
This step further can be divided into following steps:
A by the to be tested module input predetermined pumping signal of JTAG man-machine interface to FPGA, and starts test process;
B, the number of signals that detects is distributed the FPGA temporary storage cell as required, and size is the bit number of the sampled data in the sampling clock cycle;
For example, a sampling clock has the signal demand collection of 128 single-bit in the cycle, and then the size of FPGA temporary storage cell is 128 bits.
C treats detection signal and samples on the sampling clock edge;
The speed of the signal bit number that can sample simultaneously and the bit wide of SDRAM storer, SDRAM storer and the speed of sampling clock are relevant.Concrete pass is: the speed of the speed/sampling clock of the bit wide of signal bit number=SDRAM storer * SDRAM storer.For example, the bit wide of SDRAM storer is 64 bits, and the speed of SDRAM is 96MHZ, and the speed of sampling clock is 12MHz, and the signal bit number that can sample simultaneously so is exactly 64 * 96/12=512.Usually can satisfy application requirements.
D, with same sampling clock along on the data storage that collects in the FPGA temporary storage cell;
When the signal demand collection of 128 single-bit was arranged, just the data storage of 128 bits of earlier this clock period being adopted was in the FPGA temporary storage cell;
E, delivers to the SDRAM storer with the data of preserving in the FPGA temporary storage cell in batches and preserves in the cycle at a sampling clock;
Wherein, data are saved to the batch relevant with the interface bit width of SDRAM storer of SDRAM storer, for example, under the situation that the sampled data that 128 bits are arranged need be preserved, if the interface bit width of SDRAM storer is 32 bits, then divide 4 batches to deliver among the SDRAM; If the interface bit width of SDRAM storer is 64 bits, just deliver among the SDRAM in two batches.
F, repeating step C finish until sampling to step e.
The condition that sampling finishes can be: the sampling depth that has satisfied appointment; The user forces the end signal sampling by the JTAG man-machine interface; Or SDRAM storage space deficiency.
Step 140 after sampling finishes, reads the sampled data of preserving in the SDRAM storer and is uploaded to the PC end by TAP by sdram controller and carry out follow-up analysis and processing.
On the basis of the foregoing description, the present invention can also have other mapping mode.For example, the PC end can be replaced by other logic analyser, as long as have corresponding module.FPGA can be other hardware logic, as CPLD (Complex Programmable Logic Device, CPLD), EPLD (Erasable Programmable Logic Device, Erasable Programmable Logic Device) etc.As for the interface between testing tool and the hardware logic, be not confined to jtag interface yet, for the PC end, also can use other interfaces such as USB, just the use of jtag interface is more ripe at present and convenient.
Claims (10)
1, a kind of hardware logic that adopts designs the method for verifying to IC, is applied to comprise the system of the logic analyser, hardware logic and the external memory storage that link to each other successively, and the method includes the steps of:
(a) signal that need to detect of sign, and given sampling clock and sampling depth generate and are used to finish the test code for the treatment of that detection signal is sampled and the sampled data that sampling obtains being transmitted;
(b) function code to be tested and described test code are carried out logic synthesis and wiring together, generate configuration file, and download to hardware logic;
(c) to the hardware logic input signal and start test process, to treat detection signal and sample, the sampled data that sampling is obtained is transferred to external memory storage and stores;
(d) after sampling finishes, the sampled data that is stored in described external memory storage is transferred to logic analyser by the interface with logic analyser carry out follow-up analysis and processing.
2, the method for claim 1 is characterized in that:
After described step (b) downloaded to the hardware logic platform with configuration file, described function code was corresponding to the module to be tested that generates in the hardware logic, and described test code is corresponding to the signal sampling module that generates in the hardware logic;
Described step (c) is further divided into following steps:
(c1) pumping signal of being scheduled to by the module input to be tested of man-machine interface in hardware logic of logic analyser, and start test process;
(c2) number of signals that detects as required of signal sampling module is distributed the temporary storage cell of hardware logic, and size is the bit number of the sampled data in the sampling clock cycle;
(c3) on the sampling clock edge, treat detection signal and sample the speed of the speed/sampling clock of the bit wide * external memory storage of the signal bit number=external memory storage that can sample simultaneously;
(c4) with same sampling clock along on the data storage that collects in the temporary storage cell of hardware logic;
(c5), in the cycle data batchwise transfer to the external memory storage of preserving in the described temporary storage cell is preserved at a sampling clock;
(c6) repeating step (c3) finishes until sampling to step (c5).
3, method as claimed in claim 1 or 2 is characterized in that:
Communicate by the JTAG jtag interface between described logic analyser and the hardware logic, and described logic analyser uses the JTAG man-machine interface.
4, the method for claim 1 is characterized in that:
Described logic analyser is PC, and described hardware logic is a field programmable gate array, and described external memory storage is a synchronous DRAM.
5, method as claimed in claim 2 is characterized in that:
The condition that sampling finishes in the described step (c6) is a kind of or combination in any in the following condition: the sampling depth that has satisfied appointment; The user forces the end signal sampling by the man-machine interface of logic analyser; The external memory storage insufficient space.
6, a kind of hardware logic system that design is verified to IC that adopts comprises the logic analyser and the hardware logic that link to each other successively, it is characterized in that, also comprises the external memory storage that links to each other by interface with described hardware logic, wherein:
Described logic analyser comprises human-computer interface module and test interface, and this test interface links to each other with test access port on the hardware logic, is used for communicating by letter between logic analyser and the hardware logic; Described human-computer interface module is used to provide user's input test control command and signal, and gives the user with the data presentation that collects;
Comprise functional module to be tested, signal sampling module, test access port and external memory interface in the described hardware logic; Wherein the signal sampling module is used for treating the signal to be detected that the test function module generates at test process and samples, store the sampled data that samples into external memory storage earlier, read the sampled data of storage after sampling finishes again from external memory storage, test interface is uploaded to logic analyser.
7, system as claimed in claim 6 is characterized in that: the signal sampling module further comprises temporary storage area allocation units, sampling unit, sampled data preservation unit, external memory storage control module and data upload unit, wherein:
Described temporary storage area allocation units are used for the temporary storage cell according to number of signals distribution hardware logic to be detected, and its size is the bit number of the sampled data in the sampling clock cycle;
Described sampling unit, the signal to be detected that is used for treating in each sampling clock cycle the test function module carries out data sampling, and the sampled data that sampling obtains is kept in the described temporary storage cell;
Described sampled data is preserved the unit, is used for cooperating with the external memory storage control module, from described temporary storage cell the data that obtain in the sampling clock is delivered to external memory storage in batches;
Described external memory storage control module is used for by external memory interface external memory storage being carried out the control operation of reading of data;
Described data upload unit is used for after sampling process finishes, and by external memory storage control module reading of data from external memory storage, and by test access port these data is sent to logic analyser.
8, system as claimed in claim 6 is characterized in that: the test interface of described logic analyser is the JTAG jtag interface, and described logic analyser uses the JTAG man-machine interface.
9, system as claimed in claim 6 is characterized in that: described logic analyser is PC, and described hardware logic is a field programmable gate array.
10, system as claimed in claim 6 is characterized in that: described external memory storage is a synchronous DRAM.
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| US8914681B2 (en) | 2009-08-18 | 2014-12-16 | Lexmark International, Inc. | Integrated circuit including a programmable logic analyzer with enhanced analyzing and debugging capabilities and a method therefor |
| CN102541707B (en) * | 2010-12-15 | 2014-04-23 | 中国科学院电子学研究所 | Multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method |
| CN103678078B (en) * | 2012-09-25 | 2016-05-11 | 深圳市中兴微电子技术有限公司 | A kind of debug system and method |
| CN103049361A (en) * | 2013-01-11 | 2013-04-17 | 加弘科技咨询(上海)有限公司 | FPGA (Field Programmable Gata Array) with embedded logical analysis function and logical analysis system |
| CN105242997A (en) * | 2015-08-11 | 2016-01-13 | 中国航空工业集团公司西安飞机设计研究所 | Automatic test method and apparatus for airborne computer |
| EP3532929B1 (en) * | 2016-10-31 | 2023-08-16 | Synopsys, Inc. | Power computation logic |
| CN108363567B (en) * | 2018-02-12 | 2021-02-12 | 盛科网络（苏州）有限公司 | Database-based verification platform exciter automatic generation method |
| CN109800172B (en) * | 2019-01-25 | 2022-05-24 | 上海创景信息科技有限公司 | System and method for positioning embedded processor crash based on EJTAG interface |
| CN113407389A (en) * | 2021-05-19 | 2021-09-17 | 无锡中微亿芯有限公司 | FPGA (field programmable Gate array) online debugging method for realizing continuous sampling |
| CN113407390B (en) * | 2021-05-19 | 2022-08-30 | 无锡中微亿芯有限公司 | High-accuracy FPGA (field programmable Gate array) online debugging method |
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