CN101858953A - ARM (Advanced RISC Machines) core chip based automatic test system and method of digital-to-analog converter - Google Patents
ARM (Advanced RISC Machines) core chip based automatic test system and method of digital-to-analog converter Download PDFInfo
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Abstract
The invention relates to ARM (Advanced RISC Machines) core chip based automatic test system and method of a digital-to-analog converter. The system comprises a voltage measuring device, a test host, an ARM emulator, an ARM core chip and an FRGA (Field Programmable Gate Array) module, wherein the test host is connected with the voltage measuring device by the ARM emulator, the ARM core chip, the FRGA module and the measured digital-to-analog converter sequentially. The method comprises the following steps of: burning an FPGA logical code into the FPGA module; storing a test code into the test host; running the test code and inputting a test digital signal sequence to the measured digital-to-analog converter by the ARM core chip; recording each group of analog voltage output values measured by the voltage measuring device; and calculating a performance index of a subsequent digital-to-analog converter. The ARM core chip based automatic test system and the method of the digital-to-analog converter are not easy to make a mistake, improve testing efficiency, save testing time and have strong flexibility, wide applicability, good transportability, simple and practical structure, convenient and quick use, stable and reliable working performance and very wide application range.
Description
Technical field
The present invention relates to integrated circuit fields, particularly the IC chip test technical field specifically is meant a kind of digital to analog converter Auto-Test System and method thereof based on ARM nuclear chip.
Background technology
Chip testing is a step of crucial importance in the chip R﹠D process, and the quality of testing scheme greatly affects the R﹠D cycle and the R﹠D costs of chip.Good testing scheme can improve the yield rate of chip, shortens the R﹠D cycle, reduces R﹠D costs.In present science and technology field, for example communication waits the DA converter that extensive use is arranged, how its performance is tested fast, and be the problem of a very worth research.
Arm processor is a kind of high-performance, the risc chip of low-power consumption.Adopt the chip of ARM IP kernel technology to spread all over various product markets such as automobile, consumer electronics, imaging, Industry Control, communication.Being closely related with ARM IP kernel technology is the AMBA bus.In the SoC design based on IP reuse, the on-chip bus design is the problem of most critical.The AMBA on-chip bus of being released by ARM company has been subjected to numerous IP developer and SoC system integration person's favor, has become structure on a kind of popular industrial standard sheet.The AMBA standard has mainly comprised AHB (Advanced High performance Bus) system bus and APB (Advanced Peripheral Bus) peripheral bus.
FPGA (Field Programmable Gate Array) is a field programmable gate array, and it is the product that further develops on the basis of programming devices such as PAL, GAL, EPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome the limited shortcoming of original programming device gate circuit number again.The use of FPGA is very flexible, can produce different circuit functions with a slice FPGA by different programming datas.FPGA has obtained widespread use in various fields such as communication, data processing, network, instrument, Industry Control, military affairs and Aero-Space.The kind of FPGA is a lot of at present, and the Virtex series of XILINX company, the TPC series of TI company, the Stratix series of ALTERA company etc. are arranged.
DA converter (digital to analog converter) be a kind of discrete signal with binary digit amount form to convert to standard volume (or reference quantity) be the converter of the analog quantity of benchmark, be called for short DAC or D/A converter.Modal digital to analog converter is that the digital quantity with parallel binary is converted to DC voltage.Be widely used in every field such as communication at present.Seeing also shown in Figure 1ly, wherein is a kind of block diagram of 8 DA converters, and the left side is the binary digit input end, and the right side is an analog output.
In existing method of testing at the DA converter, general way is the digital input end of the manual DA of modification converter, promptly manually with DA converter input end and high level (1.5V～5V) or low level (0V～0.5V) be connected.Each group Serial No. combination of corresponding digital input end, output terminal all can have an analog output voltage value, observes and write down this value with multimeter.Usually the analog output voltage value of every group of numeral list entries need be noted, every performance index of DA converter could be calculated more accurately.
As can be seen, the manual test method expends time in very much.If one of the every increase of the input end figure place of DA converter, the input coding combination just doubles, and for example one 10 DA converter just has 2
10The combination of=1024 kinds of list entries, we must manual wire jumper 1024 times.This method was both lost time, and made mistakes easily again, had delayed the cycle of chip testing.
Summary of the invention
The objective of the invention is to have overcome above-mentioned shortcoming of the prior art, provide a kind of and can obviously shorten the test duration, realize that test fast, simple and practical, convenient to use, stable and reliable working performance, the scope of application are comparatively widely based on the digital to analog converter Auto-Test System and the method thereof of ARM nuclear chip.
In order to realize above-mentioned purpose, digital to analog converter Auto-Test System and the method thereof based on ARM nuclear chip of the present invention is as follows:
Should be based on the digital to analog converter Auto-Test System of ARM nuclear chip, comprise the voltage measuring apparatus that is connected with the analog signal output of measurand weighted-voltage D/A converter, its principal feature is, described system also comprises Test Host, ARM emulator, ARM nuclear chip and FPGA module, fast Test Host be connected with the digital signal input end of FPGA module by described ARM emulator, ARM nuclear chip successively with described measurand weighted-voltage D/A converter.
Should be based on comprising AMBA bus and internal bus converting unit in the FGPA module in the digital to analog converter Auto-Test System of ARM nuclear chip, read-write RAM logical block, test starting with stop the steering logic unit, described AMBA bus is connected with described ARM nuclear chip by the AMBA bus with the internal bus converting unit, described AMBA bus and internal bus converting unit are respectively by internal bus (mp bus) and described read-write RAM logical block, test starting with stop the steering logic unit and all be connected, described test starting with stop the digital signal input end of steering logic unit and be connected with described measurand weighted-voltage D/A converter.
Should comprise following signal based on the internal bus (mp bus) in the digital to analog converter Auto-Test System of ARM nuclear chip:
(1) address bus signal---mpa;
(2) input data bus signal---mpd;
(3) output data bus signal---mpq;
(4) host service function request signal---mpreq, and high level is effective;
(5) signal---mpwrite is selected in read-write, is used with described host service function request signal mpreq, and high level is represented to ask to carry out write operation, low level to represent to ask to carry out read operation;
(6) slave busy status signal---mpbusy, high level represent that slave is busy, and low level is represented the slave free time, and only when the slave Idle state main frame just allow to initiate operation.
Should be PC based on the Test Host in the digital to analog converter Auto-Test System of ARM nuclear chip.
Should be multimeter based on the voltage measuring apparatus in the digital to analog converter Auto-Test System of ARM nuclear chip.
This utilizes above-mentioned system to carry out examining based on ARM the digital to analog converter automatic test approach of chip, and its principal feature is that described method may further comprise the steps:
(1) system operates according to the user, and the fpga logic code that weaves is passed through in the burned described FPGA module of replication tool;
(2) system operates according to the user, deposits corresponding test code in Test Host in;
(3) system drives described ARM nuclear chip by described ARM emulator and moves described test code, and by described FPGA module to measurand weighted-voltage D/A converter input test digital signal sequences;
(4) described system operates according to the user, and the recording voltage measurement mechanism is measured respectively organizes the pairing aanalogvoltage output valve of test of digital signal sequence;
(5) system carries out the computing of the performance index of follow-up digital to analog converter according to the aanalogvoltage output valve that is write down.
This carries out can being the logical code of VHDL language or Verilog language based on the fpga logic code in the digital to analog converter automatic test approach of ARM nuclear chip.
This carries out can being the test code of C language or assembly language based on the test code in the digital to analog converter automatic test approach of ARM nuclear chip.
The digital to analog converter Auto-Test System and the method thereof based on ARM nuclear chip of this invention have been adopted, because it utilizes the mode of establishment test code in computing machine to finish most of testing process, thereby only need at PC end input test routine, allow the ARM chip control the digital signal input end supplied with digital signal sequence of FPGA module automatically to digital to analog converter, and the analog output voltage value of noting the DA converter of multimeter demonstration gets final product, thereby optimized the step of the manual DA of modification converter digital input end signal in the common test method, change the robotization mode into, be not easy to make mistakes, and improved testing efficiency, saved the test duration, simultaneously, because the programmability of FPGA module is strong, thereby can at variety classes not the digital to analog converter of isotopic number change flexibly digital signal content and the length that inputs to digital to analog converter, dirigibility is very strong, moreover, system of the present invention can be applicable to various different ARM chip and FPGA module, has adaptability widely, portable good, thereby it is simple and practical, convenient to use, stable and reliable working performance, the scope of application are comparatively extensive.
Description of drawings
Fig. 1 is 8 figure place weighted-voltage D/A converter principle schematic of the prior art.
Fig. 2 is the digital to analog converter Auto-Test System synoptic diagram based on ARM nuclear chip of the present invention.
Fig. 3 is the internal logic functional schematic based on FPGA module in the digital to analog converter Auto-Test System of ARM nuclear chip of the present invention.
Fig. 4 is of the present invention based on the internal bus theory diagram in the digital to analog converter Auto-Test System of ARM nuclear chip.
Fig. 5 is of the present invention based on the internal bus sequential chart in the digital to analog converter Auto-Test System of ARM nuclear chip.
Fig. 6 is a schematic flow sheet of examining the digital to analog converter automatic test approach of chip based on ARM of the present invention.
Embodiment
In order more to be expressly understood technology contents of the present invention, describe in detail especially exemplified by following examples.
See also shown in Figure 2, should be based on the digital to analog converter Auto-Test System of ARM nuclear chip, comprise the voltage measuring apparatus that is connected with the analog signal output of measurand weighted-voltage D/A converter, wherein, described system also comprises Test Host, ARM emulator, ARM nuclear chip and FPGA module, fast Test Host be connected with the digital signal input end of FPGA module by described ARM emulator, ARM nuclear chip successively with described measurand weighted-voltage D/A converter, wherein, described Test Host is a PC, and described voltage measuring apparatus is a multimeter.
Simultaneously, see also shown in Figure 3, comprise AMBA bus and internal bus converting unit in the described FGPA module, read-write RAM logical block, test starting with stop the steering logic unit, described AMBA bus is connected with described ARM nuclear chip by the AMBA bus with the internal bus converting unit, described AMBA bus and internal bus converting unit are respectively by internal bus (mp bus) and described read-write RAM logical block, test starting with stop the steering logic unit and all be connected, described test starting with stop the digital signal input end of steering logic unit and be connected with described measurand weighted-voltage D/A converter.
See also Fig. 4 and shown in Figure 5 again, should comprise following signal based on the internal bus (mp bus) in the digital to analog converter Auto-Test System of ARM nuclear chip:
(1) address bus signal---mpa;
(2) input data bus signal---mpd;
(3) output data bus signal---mpq;
(4) host service function request signal---mpreq, and high level is effective;
(5) signal---mpwrite is selected in read-write, is used with described host service function request signal mpreq, and high level is represented to ask to carry out write operation, low level to represent to ask to carry out read operation;
(6) slave busy status signal---mpbusy, high level represent that slave is busy, and low level is represented the slave free time, and only when the slave Idle state main frame just allow to initiate operation.
In the middle of practical application, comprise a PC, a chip in the system of the present invention, an ARM emulator, general FPGA modular platform and the multimeter of a cover based on ARM IP kernel technology.
Industry has the debugging aboundresources relevant with arm processor now.In the PC side, debugging software commonly used has for example that ADS, ARM emulator have JEDI etc.By the debugging software and the ARM emulator of PC side, C that the PC end can be write among the present invention or ARM assembly code convert discernible ARM instruction to, and are input in the ARM chip, and the ARM chip will be carried out corresponding operation according to tester's wish like this.
Because ARM can not so a cover general programmable FPGA platform (for example virtex 4 series of Xilinx) is arranged among the present invention, realize that ARM is to the control relation between the DA converter directly to DA converter input end supplied with digital signal.
FPGA inside has been realized three partial logic functions altogether: the conversion of AMBA bus and mp bus, the read-write RAM logic that has mp control bus interface, FPGA send the startup of data and stop steering logic to DA converter input end.
In order to make the logic function in the FPGA controlled, a kind of control bus is arranged among the present invention, and the AMBA bus of ARM relatively and this simple peripherals of FPGA too in complexity, in this programme, provide a kind of structure more simple, the bus architecture that function is more optimized is called the mp bus among the present invention.The basic structure of mp bus, mp bus have only 6 groups of signals, except basic address bus mpa, and data bus mpd and mpq, other three groups of mpreq, mpwrite, mpbusy are control signal wire, simple in structure, the control signal kind is few.FPGA is exactly a slave (slave) that is controlled by ARM like this.
Simultaneously, have the space among the present invention and store the Serial No. combination that sends to the DA converter, realize the RAM logic of a band mp bus interface in the inside of FPGA, deposit the digital signal sequences combination in this block RAM space.
In FPGA, realize sending the enable logic of data and stopping logic, make transmission and stop to move controlled toward the DA input end.
Write C or the ARM assembly code is very easily in the PC side.Finish (comprising FPGA internal logic function) after the preliminary work of all hardware platform, most of testing process can be realized automatically by test code.By this method, the present invention allows the ARM chip control FPGA automatically and pours into digital signal sequences to the digital input end of DA converter at PC end input test routine, and the analog output voltage value of noting the DA converter that multimeter shows gets final product.
Structure about the mp bus sees also shown in Figure 4.Bus has 6 groups of signals:
(1) address bus signal: mpa.
(2) input data bus signal: mpd.
(3) output data bus signal: mpq.
(4) main frame (host) operation request signal: mpreq is effectively high.
(5) signal: mpwrite is selected in read-write, and (mpreq) is used with operation request signal.Write operation is carried out for high expression request in this position, and read operation is carried out for low expression request in this position.
(6) slave (slave) busy status signal: mpbusy, high expression slave is busy, the low expression slave free time.Only at the slave Idle state, host just can initiate operation.
After having realized that AHB or APB bus arrive the conversion of mp bus, the RAM that has the mp bus interface is operated just very convenient.When ARM operated FPGA internal RAM address, the mp bus will be deciphered accordingly, and corresponding slave is initiated operation.
Illustrate: during write operation, if mpbusy is low, mpreq and mpwrite can become height, and address bus mpa can export appropriate address, and data-out bus mpd is correct data, and so corresponding ram space will be modified; During read operation, if mpbusy is low, mpreq can uprise, mpwrite meeting step-down (expression read operation), and address bus mpa can export appropriate address, and the data of so corresponding address ram will be exported from data-out bus mpq.Detailed signal timing diagram as shown in Figure 5.
In the present invention, agreement is an address ram from 0x1,000 0000～0x1FFF FFFF (sexadecimal), and 0x2,000 0000 is the instruction address.When 0x1,000 0000～0x1FFF FFFF address field was operated, the RAM in the FPGA can be carried out corresponding read-write; And when 0x2,000 0000 address operated, FPGA can send digital signal toward the digital input end of DA converter.In this programme, set toward 0x2,000 0000 and write at 1 o'clock, start transmit operation, write at 0 o'clock, stop to send.
Start and to stop sending function vhdl code as follows:
ifmpa＝x“20000000”and?mpreq＝‘1’and?mpd＝‘1’then
tx_go＝‘1’；
end?if；
ifmpa＝x“20000000”and?mpreq＝‘1’and?mpd＝‘0’then
tx_go＝‘0’；
end?if；
Wherein, tx_go is the control signal that starts and stop to send, and is to start FPGA at 1 o'clock to send data to the DA converter, is to stop to send in 0 o'clock.
With each part of detecting be connected finish after, PC end editor with revise test code (C or ARM compilation).After compiling is passed through, test instruction is poured in the ARM chip by the ARM emulator.
See also shown in Figure 6ly again, this utilizes above-mentioned system to carry out digital to analog converter automatic test approach based on ARM nuclear chip, and its principal feature is that described method may further comprise the steps:
(1) system operates according to the user, and the fpga logic code that weaves is passed through in the burned described FPGA module of replication tool, and described fpga logic code can be the logical code of VHDL language or Verilog language;
(2) system operates according to the user, deposits corresponding test code in Test Host in, and described test code can be the test code of C language or assembly language.
(3) system drives described ARM nuclear chip by described ARM emulator and moves described test code, and by described FPGA module to measurand weighted-voltage D/A converter input test digital signal sequences;
(4) described system operates according to the user, and the recording voltage measurement mechanism is measured respectively organizes the pairing aanalogvoltage output valve of test of digital signal sequence;
(5) system carries out the computing of the performance index of follow-up digital to analog converter according to the aanalogvoltage output valve that is write down.
In the middle of reality was used, it was as follows to test performing step accordingly:
The first step---the each several part device is connected according to shown in Figure 2.
Second step---write the fpga logic code (VHDL or Verilog language) that needs realization, by the burned FPGA platform of instrument.
The 3rd step---write C or assembly test code at the PC end.
The 4th goes on foot---and automatically perform code by debugging software by the ARM chip, FPGA is to DA converter supplied with digital signal sequence.
The 5th step---respectively organize the corresponding aanalogvoltage output valve of digital signal sequences by multimeter observation and record.
The 6th step---according to the aanalogvoltage output valve of record, the performance index of accurate Calculation DA converter.
The each several part device is linked to each other, behind the burned logical code of FPGA platform, just can carry out testing procedure automatically by test code.
DA converter with one ten is example, and is specific as follows:
Any one group of sequence that digital input end can be 0000000000 (scale-of-two) between 1111111111.
In this 4th above-mentioned step, because the programmability of C code is strong, can realize easily that FPGA imports the Serial No. that is incremented to 1111111111 (scale-of-two) from 0000000000 (scale-of-two) to the digital input end of DA converter, so just makes the test automation degree improve greatly.Simultaneously, as the institute's statement of testing process the 5th step, note the DA aanalogvoltage of every group of digital test sequence correspondence successively and export.After having traveled through all digital list entries combinations, according to the analog output voltage value of all records, every performance index of detailed calculated DA.
In the above-mentioned testing process, the realization of fpga logic is very ingenious and flexibly.The particularly logic function between AMBA bus and mp bus conversion, and the writing of RAM logic that has the mp interface.The correlation technique content of relevant AMBA bus has belonged to the ordinary skill knowledge of this area, and corresponding public publication data is very many, specifically can consult related chip handbook and the related web site of ARM, need not do being described in detail at this.
The logic module method of testing of comparing common, the invention provides a kind of brand-new method of testing based on general ARM nuclear chip and general FPGA platform, owing to wherein have a kind of simple in structure, easy mp bus architecture of realizing of function, the ARM chip has just become controlled host and slave with the FPGA platform, the logic function of FPGA platform is able to programme simultaneously, and the tester just can build the test platform of a cover at the operational blocks which partition system chip very easily like this.And not only be applied to the test of DA converter.So versatility of the present invention and dirigibility are extremely strong, this also is the advantage of maximum of the present invention.
Above-mentioned digital to analog converter Auto-Test System and method thereof have been adopted based on ARM nuclear chip, because it utilizes the mode of establishment test code in computing machine to finish most of testing process, thereby only need at PC end input test routine, allow the ARM chip control the digital signal input end supplied with digital signal sequence of FPGA module automatically to digital to analog converter, and the analog output voltage value of noting the DA converter of multimeter demonstration gets final product, thereby optimized the step of the manual DA of modification converter digital input end signal in the common test method, change the robotization mode into, be not easy to make mistakes, and improved testing efficiency, saved the test duration, simultaneously, because the programmability of FPGA module is strong, thereby can at variety classes not the digital to analog converter of isotopic number change flexibly digital signal content and the length that inputs to digital to analog converter, dirigibility is very strong, moreover, system of the present invention can be applicable to various different ARM chip and FPGA module, has adaptability widely, portable good, thereby it is simple and practical, convenient to use, stable and reliable working performance, the scope of application are comparatively extensive.
In this instructions, the present invention is described with reference to its certain embodiments.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (8)
1. digital to analog converter Auto-Test System based on ARM nuclear chip, comprise the voltage measuring apparatus that is connected with the analog signal output of measurand weighted-voltage D/A converter, it is characterized in that, described system also comprises Test Host, ARM emulator, ARM nuclear chip and FPGA module, fast Test Host be connected with the digital signal input end of FPGA module by described ARM emulator, ARM nuclear chip successively with described measurand weighted-voltage D/A converter.
2. the digital to analog converter Auto-Test System based on ARM nuclear chip according to claim 1, it is characterized in that, comprise AMBA bus and internal bus converting unit in the described FGPA module, read-write RAM logical block, test starting with stop the steering logic unit, described AMBA bus is connected with described ARM nuclear chip by the AMBA bus with the internal bus converting unit, described AMBA bus and internal bus converting unit are respectively by internal bus and described read-write RAM logical block, test starting with stop the steering logic unit and all be connected, described test starting with stop the digital signal input end of steering logic unit and be connected with described measurand weighted-voltage D/A converter.
3. the digital to analog converter Auto-Test System based on ARM nuclear chip according to claim 2 is characterized in that described internal bus comprises following signal:
(1) address bus signal---mpa;
(2) input data bus signal---mpd;
(3) output data bus signal---mpq;
(4) host service function request signal---mpreq, and high level is effective;
(5) signal---mpwrite is selected in read-write, is used with described host service function request signal mpreq, and high level is represented to ask to carry out write operation, low level to represent to ask to carry out read operation;
(6) slave busy status signal---mpbusy, high level represent that slave is busy, and low level is represented the slave free time, and only when the slave Idle state main frame just allow to initiate operation.
4. the digital to analog converter Auto-Test System based on ARM nuclear chip according to claim 1 is characterized in that described Test Host is a PC.
5. according to each described digital to analog converter Auto-Test System in the claim 1 to 4, it is characterized in that described voltage measuring apparatus is a multimeter based on ARM nuclear chip.
6. one kind is utilized the described system of claim 1 to carry out digital to analog converter automatic test approach based on ARM nuclear chip, it is characterized in that described method may further comprise the steps:
(1) system operates according to the user, and the fpga logic code that weaves is passed through in the burned described FPGA module of replication tool;
(2) system operates according to the user, deposits corresponding test code in Test Host in;
(3) system drives described ARM nuclear chip by described ARM emulator and moves described test code, and by described FPGA module to measurand weighted-voltage D/A converter input test digital signal sequences;
(4) described system operates according to the user, and the recording voltage measurement mechanism is measured respectively organizes the pairing aanalogvoltage output valve of test of digital signal sequence;
(5) system carries out the computing of the performance index of follow-up digital to analog converter according to the aanalogvoltage output valve that is write down.
7. the digital to analog converter automatic test approach that carries out based on ARM nuclear chip according to claim 6 is characterized in that described fpga logic code is the logical code of VHDL language or Verilog language.
8. the digital to analog converter automatic test approach that carries out based on ARM nuclear chip according to claim 6 is characterized in that described test code is the test code of C language or assembly language.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102722457A (en) * | 2012-05-30 | 2012-10-10 | 中国科学院微电子研究所 | Bus interface conversion method and bus bridging device |
| WO2013007068A1 (en) * | 2011-07-11 | 2013-01-17 | 北京北大众志微系统科技有限责任公司 | Automatic test system and method oriented to functions of hardware apparatus |
| CN106992782A (en) * | 2017-03-01 | 2017-07-28 | 湘潭大学 | A kind of Timing Synchronization DAC static parameter test methods |
| CN111510483A (en) * | 2020-04-09 | 2020-08-07 | 眸芯科技（上海）有限公司 | Configuration synchronization system between different network domains in chip test and application |
| CN111913841A (en) * | 2020-05-11 | 2020-11-10 | 电子科技大学 | Low-cost chip function test platform |
-
2009
- 2009-04-07 CN CN200910048936A patent/CN101858953A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013007068A1 (en) * | 2011-07-11 | 2013-01-17 | 北京北大众志微系统科技有限责任公司 | Automatic test system and method oriented to functions of hardware apparatus |
| CN102722457A (en) * | 2012-05-30 | 2012-10-10 | 中国科学院微电子研究所 | Bus interface conversion method and bus bridging device |
| CN102722457B (en) * | 2012-05-30 | 2014-12-31 | 中国科学院微电子研究所 | Bus interface conversion method and bus bridging device |
| CN106992782A (en) * | 2017-03-01 | 2017-07-28 | 湘潭大学 | A kind of Timing Synchronization DAC static parameter test methods |
| CN106992782B (en) * | 2017-03-01 | 2021-08-31 | 湘潭大学 | Timing synchronization DAC static parameter testing method |
| CN111510483A (en) * | 2020-04-09 | 2020-08-07 | 眸芯科技（上海）有限公司 | Configuration synchronization system between different network domains in chip test and application |
| CN111913841A (en) * | 2020-05-11 | 2020-11-10 | 电子科技大学 | Low-cost chip function test platform |
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Application publication date: 20101013 |