WO2020177283A1

WO2020177283A1 - Axi2wb bus bridge implementation method and device, equipment and storage medium

Info

Publication number: WO2020177283A1
Application number: PCT/CN2019/103674
Authority: WO
Inventors: 于锦辉
Original assignee: 苏州浪潮智能科技有限公司
Priority date: 2019-03-06
Filing date: 2019-08-30
Publication date: 2020-09-10
Also published as: CN109828941B; CN109828941A

Abstract

An AXI2WB bus bridge implementation method and device, equipment and a storage medium, the method comprising the following steps: latching an AXI write address channel signal and an AXI write data channel signal; determining the number of WB transmissions required for current AXI write data according to the magnifications of AXI write data bit width and WB write data bit width (S530); for each one-time WB write operation, converting the AXI write address into a WB write address for the one-time WB write operations, converting the AXI write data into WB write data for the one-time WB write operations, and on the basis of the WB write address and WB write data, executing one-time WB write operations until the number of WB write operations reaches the number of WB transmissions required for the AXI write data (S540). The present method may implement the design of a high-speed cache-free AXI2WB bus bridge suitable for use inside of an FPGA.

Description

AXI2WB bus bridge realization method, device, equipment and storage medium

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office, the application number is 201910168109.9, and the invention title is "AXI2WB bus bridge realization method, device, equipment and storage medium" on March 6, 2019. The entire content is by reference Incorporated in this application.

Technical field

This application relates to the technical field of chip design, and in particular to an AXI2WB bus bridge implementation method, device, equipment and storage medium.

Background technique

At present, SoC (System on Chip) has become the mainstream technology for large-scale digital integrated circuit design. SoC chips are generally composed of multiple IP modules, such as embedded CPUs, DSPs, various functional modules, storage modules, and external interface modules. The master module and the slave module are connected by an on-chip bus to complete the transfer of control signals and data signals. The most widely used SoC bus protocol is ARM's AMBA (Advanced Microcontroller Bus Architecture) bus protocol. The AMBA bus protocol includes AXI (Advanced eXtensible Interface) and AHB (Advanced High-performance). Bus, advanced high-performance bus), APB (Advanced Peripheral Bus, advanced peripheral bus) and other bus protocols. Among them, the AXI bus protocol has the fastest transmission rate, but it is also the most complex. It is a high-performance, high-bandwidth, low-latency chip The internal bus can meet the needs of ultra-high performance and complex SoC design.

The existing RISC-V SoC system is based on the existing open source RISC-V core verilog RTL code, and independently adds related peripherals to the MMIO (Memory-mapped I/O) interface. In MEMIO ( Memory I/O, storage I/O) interface adds DDR (Double Data Rate, double rate) as SoC memory. The RISC-V SoC system implementation environment is the xilinux FPGA development board.

In order to increase the processor speed, the MMIO interface of the RISC-V SoC system uses the AXI bus protocol. When the peripheral is directly mounted on the AXI bus, the peripheral interface needs to be encapsulated into the AXI protocol. Due to the large number of AXI bus protocol signals, when the number of peripherals is large, the interface of each peripheral needs to be encapsulated into an AXI interface, resulting in work The amount is large and the work efficiency is low.

Summary of the invention

The purpose of this application is to provide an AXI2WB bus bridge implementation method, device, equipment, and storage medium to implement the conversion from the AXI bus protocol to the WB (Wishbone) bus protocol.

To solve the above technical problems, this application provides the following technical solutions:

An AXI2WB bus bridge implementation method, including:

When monitoring that the AXI write address channel signal is valid, the AXI write address is aligned, and the AXI write address channel signal is latched;

When monitoring that the AXI write data channel signal is valid, latch the AXI write data channel signal;

According to the multiple of the bit width of the AXI write data and the bit width of the WB write data, determine the number of WB transmissions required for the current AXI write data;

For each WB write operation, the AXI write address is converted to the WB write address of the WB write operation according to the AXI write address channel signal, and the AXI write data is converted into the AXI write data according to the AXI write data channel signal. The WB write data of the second WB write operation is performed based on the WB write address and the WB write data; until the number of WB write operations reaches the number of WB transmissions required for the AXI write data.

In a specific implementation manner of the present application, the converting the AXI write address into the WB write address of the WB write operation according to the AXI write address channel signal includes:

Convert the AXI write address to the WB write address of this WB write operation according to the following formula:

wb_waddr=awaddr_ff+(w_data_cnt–1)*data_width+addr_addend*(w_wb_transfer_cnt–1);

Among them, w_data_cnt is the number of valid data wdata transferred by the current AXI write address; w_wb_transfer_cnt is the number of WB write operations completed under the current valid data wdata; addr_addend is the number of WB data bytes; awaddr_ff is the latched aligned AXI write Address; wb_waddr is the WB write address; data_width is the width of the AXI data byte.

In a specific implementation manner of the present application, the converting the AXI write data into the WB write data of the WB write operation according to the AXI write data channel signal includes:

Convert the AXI write data into the WB write data of this WB write operation according to the following formula:

wb_dat_o=(wdata_ff>>(data_width*addr_addend*(wb_transfer_cnt-1)));

Among them, wb_dat_o is WB write data; wdata_ff is latched AXI write data.

In a specific implementation of this application, it further includes:

When monitoring that the AXI read address channel signal is valid, the AXI read address is aligned and the AXI read address channel signal is latched;

Determine the number of WB transmissions required for the current AXI read data according to the multiple of the bit width of the AXI read data and the bit width of the WB read data;

For each WB read operation, according to the AXI read address channel signal, the AXI read address is converted to the WB read address of the WB read operation, and the WB read data is converted to AXI read data, based on the WB read address and The WB reads data, and executes this WB read operation; until the number of WB read operations reaches the number of WB transmissions required for the AXI read data.

In a specific implementation manner of the present application, the conversion of the AXI read address to the WB read address of the WB read operation according to the AXI read address channel signal includes:

Convert the AXI read address to the WB read address of this WB read operation according to the following formula:

wb_raddr=araddr_ff+(r_data_cnt–1)*data_width+addr_addend*(r_wb_transfer_cnt–1);

Among them, r_data_cnt is the number of effective data rdata that needs to be transferred at the current AXI read address; r_wb_transfer_cnt is the number of WB read operations completed under the current effective data rdata that needs to be transferred; addr_addend is the number of WB data bytes; araddr_ff is the latched alignment The following AXI read address; wb_raddr is the WB read address; data_width is the AXI data byte width.

In a specific implementation manner of the present application, the converting WB read data into AXI read data includes:

Convert WB read data to AXI read data according to the following formula:

rdata=wb_dat_i<<(data_width*addr_addend*(r_wb_transfer_cnt-1));

Among them, wb_dat_i is WB read data.

An AXI2WB bus bridge realization device, including:

The latch unit is used to align the AXI write address when monitoring the AXI write address channel signal is valid, and latch the AXI write address channel signal; when monitoring the AXI write data channel signal is valid, latch the AXI write data Channel signal

The adaptation unit is used to determine the number of WB transmissions required for the current AXI write data according to the multiple of the bit width of the AXI write data and the bit width of the WB write data;

The control unit is configured to convert the AXI write address to the WB write address of the WB write operation according to the AXI write address channel signal for each WB write operation, and convert the AXI write address according to the AXI write data channel signal The write data is converted into the WB write data of the WB write operation, and the WB write operation is executed based on the WB write address and the WB write data; until the number of WB write operations reaches the WB transmission required by the AXI write data frequency.

In a specific implementation of this application,

The latch unit is also used to perform alignment processing on the AXI read address when monitoring that the AXI read address channel signal is valid, and latch the AXI read address channel signal;

The adaptation unit is further configured to determine the number of WB transmissions required for the current AXI read data according to the multiple of the bit width of the AXI read data and the bit width of the WB read data;

The control unit is also used to convert the AXI read address to the WB read address of the WB read operation, and convert the WB read data to AXI read data according to the AXI read address channel signal for each WB read operation, And based on the WB read address and the WB read data, perform this WB read operation; until the number of WB read operations reaches the number of WB transmissions required for the AXI read data.

An AXI2WB bus bridge implementation device, including:

Memory, used to store computer programs;

The processor is used to implement the steps of any one of the foregoing AXI2WB bus bridge implementation methods when executing the computer program.

A computer-readable storage medium having a computer program stored on the computer-readable storage medium, and when the computer program is executed by a processor, implements the steps of any one of the above-mentioned AXI2WB bus bridge implementation methods.

Applying the technical solutions provided by the embodiments of this application can realize the design of a high-speed cacheless AXI2WB bus bridge suitable for FPGA internals, which can reduce the difficulty of peripheral development in the process of processor peripheral design, and is useful for building RISC-V processors. The SoC system has breakthrough significance, which is helpful to the process of independent research and development of CPU, and this application is suitable for bus conversion with multiple bit widths, and has universality.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

Figure 1 is a schematic diagram of the implementation structure of the AXI2WB bus bridge in an embodiment of the application;

2 is a schematic diagram of the AXI bus protocol reading channel in an embodiment of the application;

FIG. 3 is a schematic diagram of the AXI bus protocol writing channel in an embodiment of the application;

4 is a schematic diagram of WB master-slave interconnection signals in an embodiment of the application;

FIG. 5 is an implementation flowchart of an implementation method of an AXI2WB bus bridge in an embodiment of the application;

Figure 6 is a schematic diagram of the AXI write address channel processing flow in an embodiment of the application;

Figure 7 is a schematic diagram of the AXI write data channel processing flow in an embodiment of the application;

FIG. 8 is a schematic diagram of a WB write operation processing flow in an embodiment of the application;

9 is a schematic diagram of the AXI write response channel processing flow in an embodiment of the application;

FIG. 10 is a schematic diagram of the AXI read address channel processing flow in an embodiment of the application;

Figure 11 is a schematic diagram of the AXI read data channel processing flow in an embodiment of the application;

FIG. 12 is a schematic diagram of a WB read operation processing flow in an embodiment of the application;

FIG. 13 is a schematic structural diagram of an AXI2WB bus bridge implementation device in an embodiment of the application;

Fig. 14 is a schematic structural diagram of an AXI2WB bus bridge implementation device in an embodiment of the application.

detailed description

The core of this application is to provide an implementation method of the AXI2WB bus bridge to realize the conversion from the AXI bus protocol to the WB (Wishbone, an on-chip bus) bus protocol, so that the AXI bus can mount related peripherals with the WB protocol interface. Such as UART (Universal Asynchronous Receiver/Transmitter), GPIO (General Purpose Input Output, universal input/output), etc., as shown in Figure 1, is a schematic diagram of the realization of the AXI2WB bus bridge. AXI2WB bus bridge is used to connect AXI Convert the bus protocol to the WB bus protocol, and then mount low-speed peripherals that do not require high speed, such as peripherals such as GPIO and UART. WB arbitrates WB_Arbiter to determine which peripheral is currently communicating, S is Slave, from Interface, M is Master, main interface, AXI2WB bus bridge can include address alignment module Addr_Align, bit width adaptation module Width_Adapt and flow control module Flow_Ctrl.

First explain the difference between the AXI protocol and the WB protocol:

First, the AXI protocol is based on burst transmission, and defines 5 independent transmission channels: read address channel, read data channel, write address channel, write data channel, write response channel, as shown in Figure 2 and Figure 3 respectively .

Each channel of the AXI protocol can be carried out simultaneously. AXI is a data transmission protocol based on the VALID/READY handshake mechanism. The transmission source uses VALID to indicate that the address/control signal and data are valid, and the destination uses READY to indicate that it can accept information.

Read/write address channel: Each of read and write transmissions has its own address channel, and the corresponding address channel carries the address control information for the corresponding transmission.

Read data channel: The read data channel carries the read data and read response signals, including the data bus (8/16/32/64/128/256/512/1024bit) and the read response signal indicating the completion of the read transfer.

Write data channel: The data information of the write data channel is considered to be buffered, and the "master" can initiate a new write transmission without waiting for the "slave" to confirm the last write transmission. The write channel includes a data bus (8/16...1024bit) and a byte line (used to indicate the validity of the 8bit data signal).

Write response channel: "Slave" uses the write response channel to respond to write transmission. All write transfers require the completion signal of the write response channel.

The WB protocol has only one channel, and read and write operations cannot be performed at the same time. As shown in FIG. 4, the signals required for the WB protocol read and write operations are shared except for data, and the meaning of each signal is the general meaning in the prior art, which will not be repeated in the embodiment of the application.

Second, the data width of the AXI protocol is 32-bit, 64-bit, 128-bit, etc., and the data width of the WB protocol is up to 32-bits, and data bit width matching is required.

Third, the AXI protocol has address alignment rules. The address signal and byte strobe signal cannot be directly transferred to the WB protocol, and a certain conversion is required before they can be transferred to the WB protocol.

In order to enable those skilled in the art to better understand the solution of the application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

Referring to FIG. 5, an implementation flowchart of an AXI2WB bus bridge implementation method provided by an embodiment of this application, the method may include the following steps:

S510: When it is monitored that the AXI write address channel signal is valid, the AXI write address is aligned, and the AXI write address channel signal is latched.

The implementation method of the AXI2WB bus bridge provided by the embodiments of the present application can be applied to the AXI2WB bus bridge. For the convenience of description, all are referred to as the bus bridge below.

In practical applications, the bus bridge can monitor the AXI write address channel, AXI write data channel, and AXI write response channel. When monitoring that the AXI write address channel signal is valid, the AXI write address can be aligned, and the AXI write address channel signal can be latched.

Specifically, you can determine whether the AXI write address channel signal is valid through the following steps:

When the signal wdata_valid indicating whether the currently latched write data is valid, the signal bresp_valid indicating whether the currently latched feedback is valid, and the signal araddr_valid indicating whether the currently latched read address is valid are all low, awvalid and awready When it is high at the same time, confirm that the AXI write address channel signal is valid.

As shown in Figure 6, the bus bridge judges whether the signal wdata_valid indicating whether the currently latched write data is valid, the signal bresp_valid indicating whether the currently latched feedback is valid, and the signal araddr_valid indicating whether the currently latched read address is valid are all low If not, it can be repeated to determine whether the signal wdata_valid indicating whether the currently latched write data is valid, the signal bresp_valid indicating whether the current latched feedback is valid, and the signal araddr_valid indicating whether the currently latched read address is valid are all low If yes, then further judge whether awvalid and awready are both high at the same time, if yes, you can confirm that the AXI write address channel signal is valid, otherwise, you can repeat the step of judging whether awvalid and awready are both high at the same time, and after confirming that AXI write When the address channel signal is valid, AXI write address alignment can be performed.

In the embodiment of the present application, after the AXI write address channel signal is latched, awready can be set to 0, and the signal awaddr_valid indicating whether the currently latched write address is valid or not is set high, as shown in FIG. 6. Further, if the AXI is judged If the wlast signal is high, awready is set to 1, and the signal awaddr_valid, which indicates whether the currently latched write address is valid, is set to 0.

S520: When monitoring that the AXI write data channel signal is valid, latch the AXI write data channel signal.

When the bus bridge monitors the AXI write address channel and the AXI write data channel, if it monitors that the AXI write data channel signal is valid, it can latch the AXI write data channel signal.

Specifically, you can determine whether the AXI write data channel signal is valid through the following steps:

When the number of AXI write operations data_cnt is 0, the AXI signal awaddr_valid indicating whether the currently latched write address is valid is high, and wvalid and wready are both high at the same time, it is determined that the AXI write data channel signal is valid.

As shown in Figure 7, when the number of AXI write operations data_cnt is 0, the bus bridge can determine whether the AXI signal awaddr_valid indicating whether the currently latched write address is valid is high. If not, the number of AXI write operations data_cnt can be 0. If it is, it can be further judged whether wvalid and wready are both high at the same time. If it is high at the same time, it can be determined that the AXI write data channel signal is valid. Otherwise, the step of judging whether wvalid and wready are both high can be repeated.

In the embodiment of the present application, after latching the AXI write data channel signal, you can also set wready to 0, set the signal wdata_valid indicating whether the currently latched write data is valid, and increase the number of AXI write operations data_cnt by 1, as shown in the figure 7 shown.

S530: Determine the number of WB transmissions required for the current AXI write data according to the multiple of the bit width of the AXI write data and the bit width of the WB write data.

In the embodiment of the present application, a macro definition switch can be preset to select the bit width of AXI and WB. According to the multiple of the bit width of the AXI write data and the bit width of the WB write data, determine the number of WB transmissions required for the current AXI write data. That is, the number of WB transmissions tranfer_conv required for an AXI write data wdata.

Through the macro definition switch, the bit width of AXI and WB can be easily selected, and the intermediate variable addr_addend in the control logic code can be controlled to realize the design of the AXI2WB bus bridge with different bit widths without major changes to the code.

S540: For each WB write operation, according to the AXI write address channel signal, the AXI write address is converted to the WB write address of the WB write operation, and the AXI write data is converted to the WB write operation according to the AXI write data channel signal Based on the WB write address and WB write data, execute this WB write operation; until the number of WB write operations reaches the number of WB transfers required for AXI write data.

After determining the number of WB transmissions required for the current AXI write data, for each WB write operation, according to the AXI write address channel signal, the AXI write address is converted to the WB write address of the WB write operation, and the data channel signal is written according to the AXI , Convert the AXI write data into the WB write data of the WB write operation, and execute the WB write operation based on the WB write address and WB write data.

Specifically, the AXI write address can be converted to the WB write address of the WB write operation according to the following formula:

Convert AXI write data into WB write data of this WB write operation according to the following formula:

wb_dat_o=(wdata_ff>>(data_width*addr_addend*(wb_transfer_cnt-1)));

Among them, wb_dat_o is WB write data; wdata_ff is latched AXI write data.

Based on the WB write address and WB write data, each WB write operation is executed until the number of WB write operations reaches the number of WB transmissions required for AXI write data.

Specifically, as shown in FIG. 8, the bus bridge determines whether the signal awaddr_valid indicating whether the currently latched write address is valid and the signal wdata_valid indicating whether the currently latched write data is valid are both high and indicating whether the currently latched read address is Whether the valid signal araddr_valid is low, if they are all, then pull up the read and write transmission distinguishing signal wb_we_o, data cycle signal wb_stb_o, bus cycle signal wb_cyc_o, and start a WB write operation, otherwise, repeat the judgment and indicate the current latched write The step of whether the signal awaddr_valid indicating whether the address is valid and the signal wdata_valid indicating whether the currently latched write data is valid are both high and whether the signal araddr_valid indicating whether the currently latched read address is valid are low. Further, the bus bridge can determine whether the WB response signal wb_ack_i is high, and if so, determine whether the number of WB write operations wb_transfer_cnt is equal to the required number of WB transfers transfer_conv, if not, add 1 to the number of WB write operations wb_transfer_cnt, and repeat the judgment Whether the number of WB write operations wb_transfer_cnt is equal to the required number of WB transfers transfer_conv, if yes, complete all WB write operations, pull down the read and write transfer distinguishing signal wb_we_o, data cycle signal wb_stb_o, and bus cycle signal wb_cyc_o.

When the bus bridge judges that the number of WB write operations wb_transfer_cnt is equal to the required number of WB transfers transfer_conv, it sets wready to 1, and sets the signal wdata_valid, which indicates whether the currently latched write data is valid, to 0, as shown in Figure 7.

When the bus bridge is performing a WB write operation, it judges whether the AXI bvalid and bread signals of the AXI write response channel are both high at the same time. If so, it sets bvalid to 0, and further judges whether the AXI wlast signal is high, and if it is, it sets bvalid to 1, as shown in Figure 9.

In an embodiment of the present application, the method may further include the following steps:

Step 1: When monitoring that the AXI read address channel signal is valid, align the AXI write address and latch the AXI read address channel signal;

Step 2: Determine the number of WB transmissions required for the current AXI read data according to the multiple of the bit width of the AXI read data and the bit width of the WB read data;

Step 3: For each WB read operation, according to the AXI read address channel signal, the AXI read address is converted to the WB read address of the WB read operation, and the WB read data is converted to AXI read data, based on the WB read address and WB To read data, perform this WB read operation; until the number of WB read operations reaches the number of WB transmissions required for AXI read data.

In the embodiment of the present application, the bus bridge can monitor the AXI read address channel and the AXI read data channel. When monitoring that the AXI read address channel signal is valid, the AXI read address can be aligned, and the AXI read address channel signal can be latched.

Specifically, you can determine whether the AXI read address channel signal is valid through the following steps:

When the signal awaddr_valid indicating whether the currently latched write address is valid, the signals wdata_valid and bvalid indicating whether the currently latched write data is valid, and the signal araddr_valid indicating whether the currently latched read address is valid are all low, When arvalid and areready are both high at the same time, it is determined that the AXI read address channel signal is valid.

As shown in Figure 10, the bus bridge judges whether the signal awaddr_valid indicating whether the currently latched write address is valid, the signals wdata_valid and invalid indicating whether the currently latched write data is valid, and the signal araddr_valid indicating whether the currently latched read address is valid. All are low, if not, you can repeat the execution of the signal awaddr_valid that indicates whether the currently latched write address is valid, the signals that indicate whether the currently latched write data is valid, wdata_valid, bvalid, and the signals that indicate whether the currently latched read address is valid The step of whether the signal araddr_valid is low. If it is, it is further judged whether arvalid and areready are both high at the same time. If it is, it can be determined that the AXI read address channel signal is valid. Otherwise, it can be repeated to judge whether arvalid and areready are both high at the same time. Step: When it is determined that the AXI read address channel signal is valid, the AXI read address alignment can be performed.

In the embodiment of the present application, after the AXI read address channel signal is latched, arrivey can be set to 0, and the signal araddr_valid, which indicates whether the currently latched read address is valid, is set high, as shown in FIG. 10. If it is judged that the number of WB read operations wb_transfer_cnt is equal to the number of required WB transfers, transfer_conv, set arrivey to 1, the signal araddr_valid, which indicates whether the currently latched read address is valid, is set to 0, and rlast is set to 1.

When the bus bridge data_cnt is 0 when the number of AXI read operations is 0, when the AXI signal that indicates whether the currently latched read address is valid or not, the signal araddr_valid is high, the current can be determined according to the multiple of the bit width of the AXI read data and the bit width of the WB read data The number of WB transmissions required for AXI to read data. That is, the number of WB transmissions tranfer_conv required for an AXI read data rdata.

For each WB read operation, according to the AXI read address channel signal, the AXI read address is converted to the WB read address of the WB read operation, and the WB read data is converted to AXI read data, and based on the WB read address and WB read data, Perform this WB read operation.

Specifically, the AXI read address can be converted to the WB read address of the WB read operation according to the following formula:

Among them, r_data_cnt is the number of valid data rdata that needs to be transferred at the current AXI read address; r_wb_transfer_cnt is the number of WB read operations completed under the current valid data rdata that needs to be transferred; addr_addend is the number of WB data bytes; araddr_ff is the alignment of the latch The following AXI read address; wb_raddr is the WB read address; data_width is the AXI data byte width.

Convert WB read data to AXI read data according to the following formula:

rdata=wb_dat_i<<(data_width*addr_addend*(r_wb_transfer_cnt-1));

Among them, wb_dat_i is WB read data.

Based on the WB read address and WB write data, each WB read operation is performed until the number of WB read operations reaches the number of WB transmissions required for AXI read data.

Specifically, as shown in FIG. 12, the bus bridge judges the signal awaddr_valid that indicates whether the currently latched write address is valid, the signal wdata_valid that indicates whether the currently latched write data is valid, and the signal araddr_valid that indicates whether the currently latched read address is valid. If they are all low, if yes, pull up the data cycle signal wb_stb_o, bus cycle signal wb_cyc_o, and start a WB read operation, otherwise, repeat the execution of the signal awaddr_valid, which indicates whether the currently latched write address is valid, and indicates the current latch The signal wdata_valid indicating whether the write data is valid and the signal araddr_valid indicating whether the currently latched read address is valid are all low steps. Further, the bus bridge can determine whether the WB response signal wb_ack_i is high, if it is, then determine whether the number of WB read operations wb_transfer_cnt is equal to the required number of WB transfers transfer_conv, if not, add 1 to the number of WB read operations wb_transfer_cnt, and repeat the judgment Whether the number of WB read operations wb_transfer_cnt is equal to the required number of WB transfers transfer_conv step, if yes, complete all WB read operations, pull down the read and write transfer distinguishing signal wb_we_o, data cycle signal wb_stb_o, bus cycle signal wb_cyc_o, make WB read operation The number of times is 0.

When the bus bridge judges that the number of WB read operations wb_transfer_cnt is equal to the required number of WB transfers transfer_conv, it sets the read data channel rvalid to 1, increases the number of AXI read operations data_cnt by 1, as shown in Figure 11, and can further determine the AXI read data channel signal Whether it is valid, that is, whether rvalid and rready are both high at the same time, if so, set rvalid to 0, and add 1 to the number of AXI read operations data_cnt.

Application of the technical solutions provided by the embodiments of this application can realize the design of a high-speed cacheless AXI2WB bus bridge suitable for FPGAs, which can reduce the difficulty of peripheral development in the process of processor peripheral design, and is useful for building RISC-V processor-based The SoC system is of breakthrough significance and is helpful to the process of independent research and development of the CPU, and this application is applicable to bus conversions with multiple bit widths and is universal.

Corresponding to the above method embodiments, the embodiments of the present application also provide an AXI2WB bus bridge implementation device. The AXI2WB bus bridge implementation device described below and the AXI2WB bus bridge implementation method described above can be referenced correspondingly.

As shown in Figure 13, the device includes the following units:

The latch unit 1301 is used to align the AXI write address when monitoring that the AXI write address channel signal is valid, and latch the AXI write address channel signal; when it monitors that the AXI write data channel signal is valid, latch the AXI write Data channel signal;

The adaptation unit 1302 is configured to determine the number of WB transmissions required for the current AXI write data according to the multiple of the bit width of the AXI write data and the bit width of the WB write data;

The control unit 1303 is used to convert the AXI write address to the WB write address of the WB write operation according to the AXI write address channel signal for each WB write operation, and convert the AXI write data to the AXI write data channel signal according to the AXI write data channel signal. The WB write data of the WB write operation is executed, and the WB write operation is executed based on the WB write address and the WB write data; until the number of WB write operations reaches the number of WB transmissions required for the AXI write data.

In a specific implementation manner of this application, the control unit 1303 is specifically configured to:

wb_dat_o=(wdata_ff>>(data_width*addr_addend*(wb_transfer_cnt-1)));

Among them, wb_dat_o is WB write data; wdata_ff is latched AXI write data.

In a specific implementation of this application,

The latch unit 1301 is also used to perform alignment processing on the AXI read address when monitoring that the AXI read address channel signal is valid, and latch the AXI read address channel signal;

The adaptation unit 1302 is further configured to determine the number of WB transmissions required for the current AXI read data according to the multiple of the bit width of the AXI read data and the bit width of the WB read data;

The control unit 1303 is also used for each WB read operation, according to the AXI read address channel signal, convert the AXI read address to the WB read address of the WB read operation, convert the WB read data to AXI read data, and based on WB Read address and WB read data, execute this WB read operation; until the number of WB read operations reaches the number of WB transmissions required for AXI read data.

Convert WB read data to AXI read data according to the following formula:

rdata=wb_dat_i<<(data_width*addr_addend*(r_wb_transfer_cnt-1));

Among them, wb_dat_i is WB read data.

Corresponding to the above method embodiment, the embodiment of the present application also provides an AXI2WB bus bridge implementation device, as shown in FIG. 14, including:

The memory 1401 is used to store computer programs;

The processor 1402 is used to implement the steps of the AXI2WB bus bridge implementation method when executing computer programs.

Corresponding to the above method embodiments, the embodiments of the present application also provide a computer-readable storage medium with a computer program stored on the computer-readable storage medium. When the computer program is executed by a processor, the steps of the AXI2WB bus bridge implementation method are implemented. .

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

Professionals may further realize that the units and algorithm steps of the examples described in the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both, in order to clearly illustrate the possibilities of hardware and software. Interchangeability. In the above description, the composition and steps of each example have been generally described in accordance with the function. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

The steps of the method or algorithm described in the embodiments disclosed in this document can be directly implemented by hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or all areas in the technical field. Any other known storage medium.

Specific examples are used in this article to describe the principles and implementation of the application, and the description of the above examples is only used to help understand the technical solutions and core ideas of the application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

An AXI2WB bus bridge implementation method, which is characterized in that it includes:

When monitoring that the AXI write address channel signal is valid, the AXI write address is aligned, and the AXI write address channel signal is latched;

When monitoring that the AXI write data channel signal is valid, latch the AXI write data channel signal;

According to the multiple of the bit width of the AXI write data and the bit width of the WB write data, determine the number of WB transmissions required for the current AXI write data;

For each WB write operation, the AXI write address is converted to the WB write address of the WB write operation according to the AXI write address channel signal, and the AXI write data is converted into the AXI write data according to the AXI write data channel signal. The WB write data of the second WB write operation is performed based on the WB write address and the WB write data; until the number of WB write operations reaches the number of WB transmissions required for the AXI write data.
The method according to claim 1, wherein the converting the AXI write address to the WB write address of the WB write operation according to the AXI write address channel signal comprises:

Convert the AXI write address to the WB write address of this WB write operation according to the following formula:

wb_waddr=awaddr_ff+(w_data_cnt–1)*data_width+addr_addend*(w_wb_transfer_cnt–1);

Among them, w_data_cnt is the number of valid data wdata transferred by the current AXI write address; w_wb_transfer_cnt is the number of WB write operations completed under the current valid data wdata; addr_addend is the number of WB data bytes; awaddr_ff is the latched aligned AXI write Address; wb_waddr is the WB write address; data_width is the width of the AXI data byte.
The method according to claim 2, wherein the converting the AXI write data into the WB write data of the WB write operation according to the AXI write data channel signal comprises:

Convert the AXI write data into the WB write data of this WB write operation according to the following formula:

wb_dat_o=(wdata_ff>>(data_width*addr_addend*(wb_transfer_cnt-1)));

Among them, wb_dat_o is WB write data; wdata_ff is latched AXI write data.
The method according to any one of claims 1 to 3, further comprising:

When monitoring that the AXI read address channel signal is valid, the AXI read address is aligned and the AXI read address channel signal is latched;

Determine the number of WB transmissions required for the current AXI read data according to the multiple of the bit width of the AXI read data and the bit width of the WB read data;

For each WB read operation, according to the AXI read address channel signal, the AXI read address is converted to the WB read address of the WB read operation, and the WB read data is converted to AXI read data, based on the WB read address and The WB reads data, and executes this WB read operation; until the number of WB read operations reaches the number of WB transmissions required for the AXI read data.
The method according to claim 4, wherein the converting the AXI read address into the WB read address of the WB read operation according to the AXI read address channel signal comprises:

Convert the AXI read address to the WB read address of this WB read operation according to the following formula:

wb_raddr=araddr_ff+(r_data_cnt–1)*data_width+addr_addend*(r_wb_transfer_cnt–1);

Among them, r_data_cnt is the number of valid data rdata that needs to be transferred at the current AXI read address; r_wb_transfer_cnt is the number of WB read operations completed under the current valid data rdata that needs to be transferred; addr_addend is the number of WB data bytes; araddr_ff is the alignment of the latch The following AXI read address; wb_raddr is the WB read address; data_width is the AXI data byte width.
The method according to claim 5, wherein said converting WB read data into AXI read data comprises:

Convert WB read data to AXI read data according to the following formula:

rdata=wb_dat_i<<(data_width*addr_addend*(r_wb_transfer_cnt-1));

Among them, wb_dat_i is WB read data.
An AXI2WB bus bridge implementation device, which is characterized in that it comprises:

The latch unit is used to align the AXI write address and latch the AXI write address channel signal when it monitors that the AXI write address channel signal is valid; latch the AXI write data when it monitors the AXI write data channel signal is valid Channel signal

The adaptation unit is used to determine the number of WB transmissions required for the current AXI write data according to the multiple of the bit width of the AXI write data and the bit width of the WB write data;

The control unit is configured to convert the AXI write address to the WB write address of the WB write operation according to the AXI write address channel signal for each WB write operation, and convert the AXI write address according to the AXI write data channel signal The write data is converted into the WB write data of the WB write operation, and the WB write operation is executed based on the WB write address and the WB write data; until the number of WB write operations reaches the WB transmission required for the AXI write data frequency.
The device according to claim 7, wherein:

The latch unit is also used to perform alignment processing on the AXI read address when monitoring that the AXI read address channel signal is valid, and latch the AXI read address channel signal;

The adaptation unit is further configured to determine the number of WB transmissions required for the current AXI read data according to the multiple of the bit width of the AXI read data and the bit width of the WB read data;

The control unit is also used to convert the AXI read address to the WB read address of the WB read operation, and convert the WB read data to AXI read data according to the AXI read address channel signal for each WB read operation, And based on the WB read address and the WB read data, perform this WB read operation; until the number of WB read operations reaches the number of WB transmissions required for the AXI read data.
An AXI2WB bus bridge implementation device, which is characterized in that it includes:

Memory, used to store computer programs;

The processor is configured to implement the steps of the AXI2WB bus bridge implementation method according to any one of claims 1 to 6 when executing the computer program.
A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the realization of the AXI2WB bus bridge according to any one of claims 1 to 6 is realized Method steps.