CN113495862A - Bus bridge device with ECC function - Google Patents
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- 238000013500 data storage Methods 0.000 claims description 7
- 230000004044 response Effects 0.000 claims description 5
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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Abstract
The invention discloses a bus bridge device with an ECC function, which comprises an instruction processing module, a WD channel and an RD channel. The WD channel comprises an ECC encoding module and a write operation ECC code caching module, the ECC encoding module encodes input data and outputs normal data and ECC codes, and the write operation ECC code caching module is responsible for caching the ECC codes and corresponding addresses. The RD channel comprises an ECC decoding module and a read operation ECC code caching module, the ECC decoding module checks input data and an ECC code, the output data comprises normal data and check bits, and the read operation ECC code caching module is responsible for caching the ECC code and a corresponding address. The invention realizes ECC protection in the bus transmission process, realizes ECC protection on past data stream of the bus, and gets rid of the requirement limit on a terminal control line.
Description
Technical Field
The invention relates to the technical field of bus data transmission, in particular to a bus bridge device with an ECC (error correction code) function.
Background
Ecc (error Correcting code) is a technology capable of realizing "error checking and correction", is developed on the basis of parity check, and is widely applied to NAND flash memories and high-reliability memories.
The AHB bus and the AXI bus are important components of the AMBA bus specification, wherein the AHB bus is an important component of the AMBA bus specification 2.0, and are the most favored industry standard on-chip structures by IP developers and SOC system integrators due to the characteristics of block processing, single cycle bus host handover, single clock edge operation, pipelining, wider data bus architecture, and support for multiple bus masters and devices, and are widely used among high performance modules (such as CPU, DMA, DSP, and the like). The AHB system consists of a master module, a slave module and an Infrastructure (Infrastructure)3 part, wherein the AHB master is the initiator of all actions in the system, and the slave is the actual executor of all operations in the system.
The AXI bus is the most important part of AMBA3.0 protocol, and is an on-chip bus oriented to high performance, high bandwidth and low latency. The address/control and data phases of the system are separated, the system supports unaligned data transmission, and meanwhile, in burst transmission, only a first address is needed, and simultaneously, the system supports obvious transmission access and disorder access through separated read-write address channels. AXI is a new high performance protocol in AMBA. The AXI technology enriches the content of the existing AMBA standard and meets the requirements of ultra-high performance and complex system on chip (SoC) design.
At present, for the requirement of high-reliability data transmission, the SOC system design based on the AHB protocol and the AXI protocol generally performs ECC protection on the transmitted terminal, and particularly implements corresponding functions on a response controller for a memory or a flash memory, etc., thereby bringing great limitations to system design and use.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a bus bridge device with an ECC function, which realizes ECC protection in the bus transmission process, realizes ECC protection on the past data stream of a bus and gets rid of the requirement limitation on a terminal control line.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a bus bridge device with ECC function comprises an instruction processing module, a WD channel and a RD channel;
the WD channel comprises an ECC coding module and a write operation ECC code caching module, the ECC coding module codes input data and outputs normal data and ECC codes, and the write operation ECC code caching module is responsible for caching the ECC codes and corresponding addresses; when the instruction processing module receives a write instruction, writing data enters the ECC encoding module for ECC encoding, normal data is sent out, an ECC code is temporarily stored in the write operation ECC code cache module, after the data is sent, ECC write operation is started, the ECC code is written into a corresponding address space, and the current write operation is completed;
the RD channel comprises an ECC decoding module and a read operation ECC code caching module, the ECC decoding module checks input data and an ECC code and outputs normal data and check bits, and the read operation ECC code caching module is responsible for caching the ECC code and a corresponding address; when the instruction processing module receives the read instruction, the read ECC instruction is generated and sent out, the received ECC code is stored in the read operation ECC code cache module, the read instruction is normally sent out after the ECC code is received, the read back data and the temporarily stored ECC code enter the ECC decoding module together for verification, the read back normal data after the verification is returned to the AXI bus at the upper end, and the error response is replied or an error marking position is placed by the verification error RRESP.
Further, the WD channel further includes a bit width determining module, a write channel data caching module, and a data combining module, where the bit width determining module is configured to determine whether a write operation corresponding to a write instruction is a full-bit wide write operation, if the write operation is a write operation not full-bit wide, the data first enters the write channel data caching module, the instruction processing module generates a corresponding read ECC instruction and a corresponding read data instruction according to the received write instruction, the received data is temporarily stored in the read operation ECC caching module, the received data and the data read back by a subsequent read data instruction sequentially enter the ECC decoding module for verification, the read data and the write data temporarily stored in the write channel data caching module are combined to form full-bit wide transmission data, the combined data enters the ECC encoding module for ECC encoding, the normal data is sent, the ECC code is temporarily stored in the write operation ECC code caching module, and the ECC write operation is started after the data is completely sent, writing the ECC code into the corresponding address space to complete the current writing operation; if the data is the write operation with the full bit width, the write data enters the ECC encoding module to carry out ECC encoding, the normal data is sent out, the ECC code is temporarily stored in the write operation ECC code cache module, after the data is sent, the ECC write operation is started, the ECC code is written into the corresponding address space, and the current write operation is completed.
Furthermore, the ECC coding module is connected with the transmission injection module, when the injection function is needed, the card transmits the injection module and sets the position needed to inject the injection and the data volume polluted by the injection, the transmission injection module injects the corresponding position of the normal data coded by the ECC coding module, and the injection is stopped when the total injection data volume reaches the configuration data volume.
Furthermore, a branch control and gating module I is arranged in front of the ECC encoding module, and the data written by the full bit width or the data combined by the non-full bit width are transmitted to the ECC encoding module through the branch control and gating module I; and the write instruction ECC cache module is connected with the branch control and gating module II, and normal data generated after ECC encoding is sent out through the branch control and gating module II.
Furthermore, the bus bridge device is used in a point-to-point bridging mode, the memory module with the bus interface is directly mounted on the host interface of the bus bridge device, and the space for mounting the memory module simultaneously meets the requirements of data storage and ECC code storage.
Furthermore, the bus bridge device is used in a bus cascade bridging mode, and the bus bridge device mounts a plurality of memory modules through a bus and stores data and ECC codes in different slaves.
Further, the bus bridge device is applicable to an AXI bus and an AHB bus.
Further, the instruction processing module comprises a write instruction processing module and a read instruction processing module.
The invention has the beneficial effects that: the invention realizes ECC protection in the bus transmission process, realizes ECC protection on past data stream of the bus, and gets rid of the requirement limit on a terminal control line. Meanwhile, the embedded position of the module can be flexibly selected, the storage positions of the data and the ECC check code can be flexibly distributed, and the limitation of using the ECC function of the original system is broken through. Has the function of injecting poison and can be used for the reverse test of the system.
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FIG. 1 is a schematic block diagram of a bus bridge apparatus according to embodiment 1;
FIG. 2 is a schematic diagram illustrating point-to-point bridging of a bus bridge device according to embodiment 1;
FIG. 3 is a schematic diagram of bus cascade bridging of the bus bridge apparatus according to embodiment 1;
FIG. 4 is a schematic block diagram of a bus bridge apparatus according to embodiment 2;
FIG. 5 is a schematic diagram illustrating point-to-point bridging of the bus bridge device according to embodiment 2;
fig. 6 is a schematic diagram of bus cascade bridging of the bus bridge apparatus according to embodiment 2.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
The present embodiment discloses an AHB bus bridge device with ECC function, as shown in fig. 1, including an instruction processing module, a WD channel, and an RD channel.
The WD channel comprises a bit width judging module, a write channel data caching module FIFO, a data combination module D MERGE, a branch control and gating module I, ECC encoding module ENC, a write operation ECC code caching module DA, a transmission POISON injection module POISON and a branch control and gating module II.
One path of the bit width judging module is directly connected to the branch control and gating module I, and the other path of the bit width judging module is connected to the branch control and gating module I through the write channel data cache module FIFO and the data combination module D MERGE. The branch control and gating module I, ECC comprises an encoding module ENC, a write operation ECC code buffer module DA and a branch control and gating module II which are connected in sequence, and a transmission injection module POISON is connected between the ECC encoding module ENC and the branch control and gating module II.
The RD channel comprises an ECC decoding module and a read operation ECC code caching module which are connected in sequence.
The ENC is an ECC encoding module, encodes input data, and outputs the input data including normal data and ECC. DEC is an ECC decoding module, input data and an ECC code are checked, and output comprises normal data and check bits. The DA is an ECC cache module and is responsible for caching the ECC code and the corresponding address. The WD channel and the RD channel are both provided with DA modules which are a write operation ECC code cache module and a read operation ECC code cache module respectively.
For a write command, the CMD module receives the write command and cooperates with the WD channel, if the write operation is not a full bit wide write operation (defined by hsize and actual data width), the operation related to DATA MERGE is that data first enters a buffered FIFO, the CMD module generates a corresponding read ECC command according to the received write command, the received data is temporarily stored in the ECC code buffer module, and sequentially enters a DEC module for checking together with data read back by a subsequent read data command, the read data is combined with write data temporarily stored in the FIFO (checking errors can be returned by RESP or put by an error flag bit), so as to form full bit wide transmission data, entering ENC through MUX to carry out ECC coding, sending out normal data through MUX, temporarily storing ECC code in ECC cache, after data sending is finished, and starting ECC (error correction code) writing operation, writing the ECC code into a corresponding address space to finish the current writing operation, and operating the CMD (cross-machine direction) module to receive a new writing command. And if the write operation is the write operation with the full bit width, the write data enters the ENC module through the MUX to be subjected to ECC encoding, the normal data is sent out through the MUX, the ECC code is temporarily stored in the ECC cache, after the data is sent, the ECC write operation is started, the ECC code is written into the corresponding address space, the current write operation is completed, and the CMD module operates to receive a new write instruction. For a read operation, the CMD module receives a read instruction, generates and sends out a read ECC instruction, stores the received ECC code in an ECC cache of an RD channel, the CMD receives the read instruction and normally sends out the read instruction after the ECC code is received, read-back data and the temporarily stored ECC code sequentially enter the DEC module for checking, the data read back after checking is normally returned to an AHB bus at the upper end, a check error can be responded by an RESP (representational state protocol) or an error indication position is placed, and the CMD can receive a new read operation after the read operation is completed. When the virus injection function is started, the virus injection function is required to be set to be started, the position where the virus injection is required and the data volume polluted by the virus injection are set, the module injects the virus to the corresponding position transmitted by each pen, and the virus injection is stopped after the total virus injection data volume reaches the configuration data volume.
The bus bridge device needs to configure a base address stored corresponding to the data and a base address stored corresponding to the ECC code, and the data and the ECC code are respectively received and transmitted through a host interface in a form of adding an offset address to the corresponding base address. There are two typical ways of using a bus bridge arrangement. As shown in fig. 2, the point-to-point bridging uses a host interface directly mounting the memory module with the AHB interface to the bus bridge device, and the space for mounting the memory module is required to satisfy the requirements of data storage and ECC code storage at the same time. As shown in fig. 3, the bus cascade bridge may store data and ECC codes in different slaves, and the AHB bus is used to connect the plurality of memory modules, for example, the data storage base address corresponds to the storage 1 base address, the ECC code storage base address corresponds to the storage 2 base address, and the data may be stored in the slave storage 1, and the ECC codes may be stored in the slave storage 2.
Example 2
The embodiment discloses an AXI bus bridge device with ECC function, as shown in fig. 4, an instruction processing module, a WD channel and a RD channel.
In this embodiment, the instruction processing module includes a write instruction processing module WA and a read instruction processing module RA.
The WD channel comprises a bit width judging module, a write channel data caching module FIFO, a data combination module D MERGE, a branch control and gating module I, ECC encoding module ENC, a write operation ECC code caching module DA, a transmission POISON injection module POISON and a branch control and gating module II.
One path of the bit width judging module is directly connected to the branch control and gating module I, and the other path of the bit width judging module is connected to the branch control and gating module I through the write channel data cache module FIFO and the data combination module D MERGE. The branch control and gating module I, ECC comprises an encoding module ENC, a write operation ECC code buffer module DA and a branch control and gating module II which are connected in sequence, and a transmission injection module POISON is connected between the ECC encoding module ENC and the branch control and gating module II.
The RD channel comprises an ECC decoding module and a read operation ECC code caching module which are connected in sequence.
The ENC is an ECC encoding module, encodes input data and outputs normal data and ECC; DEC is an ECC decoding module, which checks the input data and the ECC code and outputs normal data and check bits; the DA is an ECC cache module and is responsible for caching the ECC code and the corresponding address. The WD channel and the RD channel are both provided with DA modules which are a write operation ECC code cache module and a read operation ECC code cache module respectively.
For a write instruction, a WA module receives the write instruction and cooperates with a WD channel, if the write operation is not a full bit width write operation (namely & wstrb is false), the operation related to DATA MERGE is that data firstly enters a cached FIFO, the WA module generates a corresponding ECC read instruction and a corresponding data read instruction to an RA module according to the received write instruction, the ECC read instruction is firstly sent out through the RA module, the received data is temporarily stored in an ECC cache and sequentially enters a DEC module together with the data read by a subsequent instruction for verification, the read data is combined with the write data temporarily stored in the FIFO (the verification error can reply an error response or place an error indication bit through BRESP), transmission data with a full bit width is formed and enters an ENC for ECC encoding through MUX, normal data is sent out through MUX, the ECC code is temporarily stored in the ECC cache, after the data is sent out, the ECC write operation is started, the ECC code is written into a corresponding address space, completing the current writing operation, and operating and receiving a new writing instruction by the WA module; if the write operation is the write operation with the full bit width (namely that wstrb is true), the write data enters the ENC module through the MUX to be subjected to ECC encoding, normal data is sent out through the MUX, the ECC code is temporarily stored in the ECC cache, after the data is sent out, the ECC write operation is started, the ECC code is written into a corresponding address space, the write operation of the time is completed, and the WA module operates to receive a new write instruction. For reading operation, the RA module receives a reading instruction, generates and sends out an ECC reading instruction, stores the received ECC code in an ECC cache of an RD channel, the reading instruction received by the RA is normally sent out after the ECC code is received, read-back data and the temporarily stored ECC code sequentially enter the DEC module for verification, the read-back data after verification is normally returned to an AXI bus at the upper end, a verification error can be replied by a RRESP to respond to an error response or place an error indication position, and the RA can receive new reading operation after the reading operation is completed. When the virus injection function is started, the virus injection function is required to be set to be started, the position where the virus injection is required and the data volume polluted by the virus injection are set, the module injects the virus to the corresponding position transmitted by each pen, and the virus injection is stopped after the total virus injection data volume reaches the configuration data volume.
The bus bridge device needs to configure a base address stored corresponding to the data and a base address stored corresponding to the ECC code, and the data and the ECC code are respectively received and transmitted through a host interface in a form of adding an offset address to the corresponding base address. There are two typical ways of using a bus bridge arrangement. As shown in fig. 5, the point-to-point bridging uses a host interface directly mounting the memory module with the AXI interface on the bus bridge device, and the space for mounting the memory module can satisfy the requirements of data storage and ECC code storage at the same time. As shown in fig. 6, the bus cascade bridge system connects a plurality of memories through the AXI bus, and can store data and ECC codes in different slaves, for example, a data storage base address corresponds to a storage 1 base address, an ECC code storage base address corresponds to a storage 2 base address, and data can be stored in the slave storage 1 and ECC codes can be stored in the slave storage 2.
The invention realizes the ECC function in the bus transmission channel and realizes the ECC protection of data; the module is designed and exists in a bridge mode, and the embedding position is flexible; the data storage address and the ECC code storage address are flexible and configurable; has the function of injecting poison and can be used for the reverse test of the system.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art according to the present invention are included in the protection scope of the present invention.
Claims (8)
1. A bus bridge device with ECC function is characterized in that: the system comprises an instruction processing module, a WD channel and a RD channel;
the WD channel comprises an ECC coding module and a write operation ECC code caching module, the ECC coding module codes input data and outputs normal data and ECC codes, and the write operation ECC code caching module is responsible for caching the ECC codes and corresponding addresses; when the instruction processing module receives a write instruction, writing data enters the ECC encoding module for ECC encoding, normal data is sent out, an ECC code is temporarily stored in the write operation ECC code cache module, after the data is sent, ECC write operation is started, the ECC code is written into a corresponding address space, and the current write operation is completed;
the RD channel comprises an ECC decoding module and a read operation ECC code caching module, the ECC decoding module checks input data and an ECC code and outputs normal data and check bits, and the read operation ECC code caching module is responsible for caching the ECC code and a corresponding address; when the instruction processing module receives the read instruction, the read ECC instruction is generated and sent out, the received ECC code is stored in the read operation ECC code cache module, the read instruction is normally sent out after the ECC code is received, the read back data and the temporarily stored ECC code enter the ECC decoding module together for verification, the read back normal data after the verification is returned to the AXI bus at the upper end, and the error response is replied or an error marking position is placed by the verification error RRESP.
2. The ECC-capable bus bridge apparatus according to claim 1, wherein: the WD channel also comprises a bit width judging module, a write channel data caching module and a data combination module, wherein the bit width judging module is used for judging whether the write operation corresponding to the write instruction is full bit wide write operation or not, if the write operation is not full bit wide write operation, the data firstly enters the write channel data caching module, the instruction processing module generates corresponding read ECC (error correction code) instructions and read data instructions according to the received write instruction, the received data is temporarily stored in the read operation ECC caching module and sequentially enters the ECC decoding module together with the data read by the subsequent instruction for checking, the read data is combined with the write data temporarily stored in the write channel data caching module to form transmission data with full bit width, the combined data enters the ECC encoding module for ECC encoding, the normal data is sent, the ECC code is temporarily stored in the write operation ECC encoding module, and the write ECC operation is started after the data are sent completely, writing the ECC code into the corresponding address space to complete the current writing operation; if the data is the write operation with the full bit width, the write data enters the ECC encoding module to carry out ECC encoding, the normal data is sent out, the ECC code is temporarily stored in the write operation ECC code cache module, after the data is sent, the ECC write operation is started, the ECC code is written into the corresponding address space, and the current write operation is completed.
3. The bus bridge apparatus with ECC function according to claim 1 or 2, wherein: the ECC coding module is connected with the transmission injection module, when the injection function is needed, the transmission injection module is clamped and sets the position needing injection and the data volume polluted by injection, the transmission injection module injects the injection to the corresponding position of the normal data coded by the ECC coding module, and the injection is stopped when the total injection data volume reaches the configuration data volume.
4. The bus bridge apparatus with ECC function according to claim 1 or 2, wherein: a branch control and gating module I is arranged in front of the ECC coding module, and the data written by the full bit width or the data combined by the non-full bit width are transmitted to the ECC coding module through the branch control and gating module I; and the write instruction ECC cache module is connected with the branch control and gating module II, and normal data generated after ECC encoding is sent out through the branch control and gating module II.
5. The ECC-capable bus bridge apparatus according to claim 1, wherein: the bus bridge device is used in point-to-point bridging, a storage module with a bus interface is directly mounted on a host interface of the bus bridge device, and the space for mounting the storage module simultaneously meets the requirements of data storage and ECC code storage.
6. The ECC-capable bus bridge apparatus according to claim 1, wherein: the bus bridge device is used in a bus cascade bridging mode, and the bus bridge device is used for mounting a plurality of memory modules through a bus and storing data and ECC codes in different slaves.
7. The ECC-capable bus bridge apparatus according to claim 1, wherein: the bus bridge device is suitable for an AXI bus and an AHB bus.
8. The ECC-capable bus bridge apparatus according to claim 1, wherein: the instruction processing module comprises a write instruction processing module and a read instruction processing module.
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| CN118400223A (en) * | 2024-06-25 | 2024-07-26 | 深圳市速腾聚创科技有限公司 | Bus bridge, chip and laser radar thereof |
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| CN112380157A (en) * | 2020-11-26 | 2021-02-19 | 北京工业大学 | IIC bus communication device with FIFO cache and check function |
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