CN112530509A

CN112530509A - Method for providing ECC for storage device, ECC module and storage device

Info

Publication number: CN112530509A
Application number: CN202011452622.XA
Authority: CN
Inventors: 王时; 林岗
Original assignee: Shanghai Yixin Industry Co Ltd
Current assignee: Shanghai Yixin Industry Co Ltd
Priority date: 2018-12-26
Filing date: 2019-07-05
Publication date: 2021-03-19
Also published as: CN110310693A; CN110310693B

Abstract

The application relates to a method for providing ECC by a storage device, an ECC module and the storage device. The method comprises the following steps: in response to receiving a write command, if the data to be written by the write command belongs to the address range of the first data unit, writing the data to be written by the write command into a single-beat cache, wherein the single-beat cache can accommodate one data unit; calculating check data for the data units stored in the single-beat cache, and obtaining a first ECC unit corresponding to the first data unit; calculating the address of the first ECC unit according to the address of the first data unit; a write command is generated indicating an address of the first ECC unit to write the first ECC unit to the DRAM.

Description

Method for providing ECC for storage device, ECC module and storage device

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method for providing ECC for a memory device, an ECC module, and a memory device.

Background

Error Checking and Correction (ECC) functionality is provided in some memory subsystems to detect data errors in the memory and, optionally, to correct erroneous data. The memory providing the ECC function stores data and check data calculated based on the data. The data and its check data constitute a data protection unit. For example, in one data protection unit, the size of the check data is 12.5% of the data.

There are various ECC codes for generating check data for data in the memory, such as generating check data by XOR (exclusive or) calculation, generating check data by hamming code, generating check data by BCH (Bose-Chaudhuri-Hocquenghem) code, and the like.

Disclosure of Invention

The memory providing the ECC function is relatively expensive. It is desirable to use a relatively inexpensive ordinary memory and provide the ECC function at the same time. And accessing the check data would introduce additional overhead in terms of bandwidth and latency for memory accesses, which is desirably reduced to ensure memory performance.

According to a first aspect of the present application, there is provided a method of providing ECC for a memory device according to the first aspect of the present application, comprising: in response to receiving the write command, if the data to be written by the write command belongs to the address range of the first data unit, writing the data to be written by the write command into the single-beat cache; calculating check data for the data units stored in the single-beat cache, and obtaining a first ECC unit corresponding to the first data unit; calculating the address of the first ECC unit according to the address of the first data unit; a write command is generated indicating an address of the first ECC unit to write the first ECC unit to the DRAM.

A first method of providing ECC for a memory device according to the first aspect of the present application, a second method of providing ECC for a memory device according to the first aspect of the present application, further comprising: and responding to the write command that the data to be written belongs to the address range of the first data unit, and if available single-beat cache exists, allocating the single-beat cache for storing the first data unit.

A second method of providing ECC for a memory device according to the first aspect of the present application, and a third method of providing ECC for a memory device according to the first aspect of the present application, wherein data to be written in response to a write command belongs to an address range of a first data unit, and if there is no available one-beat buffer, a full data buffer is allocated for storing the first data unit.

According to one of the first to third methods of providing ECC for a memory device of the first aspect of the present application, there is provided a fourth method of providing ECC for a memory device of the first aspect of the present application, wherein a size of the full data cache is equal to a maximum transfer length of the bus.

According to one of the first to fourth methods of providing ECC for a memory device of the first aspect of the present application, there is provided a fifth method of providing ECC for a memory device of the first aspect of the present application, wherein the single beat buffer is sized to accommodate one data unit.

According to one of the first to fifth methods for providing ECC for a memory device of the first aspect of the present application, there is provided a sixth method for providing ECC for a memory device of the first aspect of the present application, wherein if the data to be written by the write command exceeds the address range of the first data unit, the data to be written by the write command is written into the full data cache.

According to a sixth aspect of the present application, there is provided one of the methods for providing ECC for a memory device, according to the seventh aspect of the present application, the method further comprising: calculating check data for a plurality of data units in the complete data cache, and obtaining a plurality of ECC units corresponding to the plurality of data units; generating a write command indicating the plurality of ECC unit storage addresses to write the plurality of ECC units to the DRAM.

According to one of the first to seventh methods of providing ECC for a memory device of the first aspect of the present application, there is provided a method of providing ECC for a memory device of the eighth aspect of the present application, further comprising: in response to receiving a write command, identifying whether the write command causes a partial write operation; in response to recognizing that the write command causes a partial write operation, calculating an address of an ECC unit stored in the DRAM corresponding to data accessed by the partial write operation; generating a read command indicating an address of the ECC unit stored in a DRAM to read the ECC unit from the DRAM; and combining the read data unit corresponding to the ECC unit and the data to be written by the write command to obtain the data unit to be written stored in the single-beat cache or the complete data cache.

According to an eighth method for providing ECC for a memory device of the first aspect of the present application, there is provided a ninth method for providing ECC for a memory device of the first aspect of the present application, wherein whether the write command causes a partial write operation is identified according to an address of the write command and a length of a data unit.

A ninth method of providing ECC for a memory device according to the first aspect of the present application, and a tenth method of providing ECC for a memory device according to the first aspect of the present application, wherein if a start address of an address space accessed by a write command is not aligned with a boundary of a data unit, a partial write operation is caused at the start address of the write command.

A method of providing ECC for a memory device according to the ninth or tenth aspect of the present application provides a method of providing ECC for a memory device according to the eleventh aspect of the present application, wherein if an ending address of an address space accessed by a write command is not aligned with a boundary of a data unit, a partial write operation is caused at the ending address of the write command.

According to an eighth method for providing ECC for a memory device of the first aspect of the present application, there is provided the twelfth method for providing ECC for a memory device of the first aspect of the present application, wherein if a part of data in the first beat of data of the bus transfer indicated by the write command is invalid data, the first beat of the bus transfer indicated by the write command causes a partial write operation; or if partial data in the last beat of data transmitted by the bus indicated by the write command is invalid data, the last beat of data transmitted by the bus indicated by the write command causes partial write operation.

According to an eighth method of providing ECC for a memory device according to the first aspect of the present application, there is provided a method of providing ECC for a memory device according to the thirteenth aspect of the present application, wherein if one of the first beat of data of the bus transfer indicated by the write command is invalid data, the first beat of the bus transfer indicated by the write command causes a partial write operation; or if one part of data in the last beat of data transmitted by the bus indicated by the write command is invalid data, the last beat of data transmitted by the bus indicated by the write command causes partial write operation.

According to an eighth method of providing ECC for a memory device according to the first aspect of the present application, there is provided the fourteenth method of providing ECC for a memory device according to the first aspect of the present application, wherein the first beat of the bus transfer indicated by the write command causes a partial write operation if a start address of the first beat of data of the bus transfer indicated by the write command is an integer multiple of a bus transfer unit, and not an integer multiple of a data unit.

According to an eighth method of providing ECC for a memory device according to the first aspect of the present application, there is provided the fifteenth method of providing ECC for a memory device according to the first aspect of the present application, wherein the last beat of the bus transfer indicated by the write command causes a partial write operation if a starting address of the last beat of data of the bus transfer indicated by the write command is an integer multiple of a bus transfer unit, and not an integer multiple of a data unit.

According to one of the first to fifteenth methods of providing ECC for a memory device of the first aspect of the present application, there is provided a sixteenth method of providing ECC for a memory device according to the first aspect of the present application, wherein the check data is appended to the specified locations of the data units to form ECC units.

According to one of the first to sixteenth methods of providing ECC for a memory device of the first aspect of the present application, there is provided a method of providing ECC for a memory device of the seventeenth aspect of the present application, wherein the designated location is after the data unit.

According to one of the first or seventeenth methods of providing ECC for a memory device of the first aspect of the present application, there is provided a method of providing ECC for a memory device of the eighteenth aspect of the present application, wherein,according to the formula

Calculating the memory address of an ECC cell, wherein each operation is an integer operation, Addr_eccIs the starting address, Addr, of the ECC cell_orgThe address of the data unit, N is the data length of the ECC unit, M is the size of the storage space occupied by the data unit in the ECC block, and S is the number of bytes skipped over every 4K.

According to a second aspect of the present application, there is provided a method of providing ECC for a memory device according to the first aspect of the present application, comprising: calculating the address of an ECC unit corresponding to the data unit according to the address of the data unit corresponding to the data to be read by the read command; generating a read command indicating an address of the ECC unit to read the ECC unit from the DRAM; splitting the ECC unit to obtain check data and a data unit; and if the number of the data units to be read by the read command is less than the threshold value, acquiring the data to be read by the read command from the read data units and storing the data in the single-beat cache.

The first method for providing ECC for a memory device according to the second aspect of the present application provides the second method for providing ECC for a memory device according to the second aspect of the present application, wherein if the number of data units to be read by the read command is not less than the threshold value, the data to be read by the read command obtained from the read data units is stored in the complete data cache.

A method of providing ECC for a memory device according to the first or second aspect of the present application, a method of providing ECC for a memory device according to the third aspect of the present application is provided, further comprising: and responding to the reading command, wherein the number of the data units to be read is smaller than a threshold value, and if available single-beat cache exists, distributing the single-beat cache for storing the data to be read by the reading command.

A third method of providing ECC for a memory device according to the second aspect of the present application provides a fourth method of providing ECC for a memory device according to the second aspect of the present application, wherein if the number of data units to be read in response to a read command is less than a threshold, a full data buffer is allocated if there is no available single beat buffer, the number of data units to be read in response to the read command being less than the threshold.

According to one of the first to fourth methods of providing ECC for a memory device of the second aspect of the present application, there is provided a fifth method of providing ECC for a memory device according to the second aspect of the present application, wherein the size of the complete data buffer is equal to the maximum transfer length of the bus.

According to one of the first to fifth methods of providing ECC for a memory device of the second aspect of the present application, there is provided a sixth method of providing ECC for a memory device of the second aspect of the present application, wherein the size of the single beat buffer can accommodate one data unit.

According to one of the first to sixth methods of providing a memory device with ECC according to the second aspect of the present application, there is provided a method of providing a memory device with ECC according to the seventh aspect of the present application, wherein, in response to receiving a read command, an ECC unit read out from a DRAM is determined according to a start address and a length of a memory space accessed by the read command.

A seventh method of providing ECC for a memory device according to the second aspect of the present application, a method of providing ECC for a memory device according to the eighth method of the second aspect of the present application is provided, wherein ECC units are read out from a DRAM through a bus transfer unit.

A seventh method of providing ECC for a memory device according to the second aspect of the present application, a ninth method of providing ECC for a memory device according to the second aspect of the present application, wherein a start address of a memory space of data to be read by a read command is modulo a size of a data unit; and taking the result of the modulus as the initial address of the data unit corresponding to the data to be read by the read command.

According to one of the first to ninth methods of providing ECC for a memory device of the second aspect of the present application, there is provided a method of providing ECC for a memory device of the tenth aspect of the present application, wherein Addr is according to the formula_ecc＝Addr_org+Addr_org>>N+(Addr_orgStorage address of/M) multiplied by 16 calculation ECC unitWherein each operation is an integer operation, Addr_eccIs the starting address, Addr, of the ECC cell_orgThe starting address of the data unit, N is the shift number, and M is the size of the storage space occupied by the data unit.

According to one of the first to tenth methods of providing ECC for a memory device of the second aspect of the present application, there is provided a method of providing ECC for a memory device of the eleventh aspect of the present application, further comprising: and performing ECC (error correction code) check on the check data and the data unit obtained by splitting the ECC unit, and sending information of memory access abnormity to the main equipment in response to failure of the check.

One of the methods of providing a memory device with ECC according to the first to eleventh aspects of the present application provides a method of providing a memory device with ECC according to the twelfth aspect of the present application, wherein the check data is appended to the specified locations of the data units to form ECC units.

A twelfth method of providing a memory device with ECC in accordance with the second aspect of the present application provides a thirteenth method of providing a memory device with ECC in accordance with the second aspect of the present application, wherein the designated location is after the data unit.

According to one of the first to thirteenth methods of providing ECC for a memory device of the second aspect of the present application, there is provided a method of providing ECC for a memory device of the fourteenth aspect of the present application, wherein the method is performed according to a formula

According to a third aspect of the present application, there is provided a first ECC module according to the third aspect of the present application, comprising: the device comprises a single-beat cache, an ECC encoder, an ECC insertion unit and an address calculator; the single-beat cache stores data to be written by a write command belonging to the address range of the first data unit; the ECC encoder calculates check data for the data unit stored in the single-beat cache; the ECC insertion unit generates a first ECC unit corresponding to the first data unit by using the check data and the data unit stored in the single-beat cache; the address calculator calculates an address storing the first ECC unit according to the address of the first data unit.

The first ECC module according to the third aspect of the present application provides the second ECC module according to the third aspect of the present application, further comprising: caching complete data; the complete data cache stores data to be written by a write command accessing an address range exceeding a single data unit; the ECC encoder calculates a plurality of check data for a plurality of data units stored in the complete data cache; the ECC insertion unit generates a plurality of ECC units by the plurality of check data and the plurality of data units stored in the complete data cache; the address calculator calculates addresses of a plurality of ECC units according to the addresses of the plurality of data units.

The first or second ECC module according to the third aspect of the present application provides the third ECC module according to the third aspect of the present application, wherein a size of the complete data buffer is equal to a maximum transfer length of the bus.

According to one of the first to third ECC modules of the third aspect of the present application, there is provided the fourth ECC module of the third aspect of the present application, wherein the single beat buffer is sized to accommodate one data unit.

According to one of the first to fourth ECC modules of the third aspect of the present application, there is provided a fifth ECC module according to the third aspect of the present application, further comprising: a partial write detector and a read-modify-write controller; the partial write detector identifies whether the write command causes a partial write operation; in response to recognizing that the write command causes a partial write operation, the address calculator calculates an address of an ECC unit corresponding to data accessed by the partial write operation; the read-modify-write controller generates a read command indicating an address of the ECC unit to read the ECC unit from the DRAM, and combines the data unit corresponding to the read ECC unit with the data to be written by the write command to obtain the data unit to be written stored in the single-beat buffer or the complete data buffer.

According to a fifth ECC module of the third aspect of the present application, there is provided the sixth ECC module of the third aspect of the present application, wherein the partial write detector identifies whether the write command causes the partial write operation, based on an address of the write command and a length of the data unit.

According to a sixth ECC module of the third aspect of the present application, there is provided the seventh ECC module of the third aspect of the present application, wherein the partial write detector causes the partial write operation at the start address of the write command according to a misalignment of a start address of an address space accessed by the write command and a boundary of the data unit.

According to a sixth or seventh ECC module of the third aspect of the present application, there is provided the eighth ECC module of the third aspect of the present application, wherein the partial write detector causes the partial write operation at an end address of the write command according to a misalignment of an end address of an address space accessed by the write command and a boundary of the data unit.

According to a fifth ECC module of the third aspect of the present application, there is provided the ninth ECC module of the third aspect of the present application, wherein the partial write detector obtains, for the invalid data, the partial data in the first beat of data of the bus transfer indicated by the write command, and causes the partial write operation; or if partial data in the last beat of data transmitted by the bus indicated by the write command is invalid data, obtaining that the last beat of data transmitted by the bus indicated by the write command causes partial write operation.

According to a fifth ECC unit of the third aspect of the present application, there is provided the tenth ECC module of the third aspect of the present application, wherein the partial write detector obtains the partial write operation from the first beat of the bus transfer indicated by the write command, the start address of the first beat of the data of the bus transfer indicated by the write command being an integer multiple of the bus transfer unit, not an integer multiple of the data unit.

According to a fifth ECC module of the third aspect of the present application, there is provided the eleventh ECC module of the third aspect of the present application, wherein the partial write detector is configured to obtain that the last beat of the bus transfer indicated by the write command causes the partial write operation, in accordance with a start address of the last beat of data of the bus transfer indicated by the write command being an integer multiple of a bus transfer unit, not an integer multiple of a data unit.

According to one of the first to eleventh ECC modules of the third aspect of the present application, there is provided the twelfth ECC module according to the third aspect of the present application, further comprising: an ECC decoder and an ECC splitting unit; the address calculator calculates the address of an ECC unit corresponding to the data unit according to the address of the data unit corresponding to the data to be read out by the read command; the ECC splitting unit splits the ECC unit read out from the ECC unit address to obtain check data and a data unit; the ECC decoder checks the data unit through the check data; the single-beat cache stores and verifies the data to be read by the read command acquired from the data unit accessed by the read command with the number of the data unit to be read by the read command smaller than the threshold value; and the complete data cache stores and verifies the data to be read by the read command acquired from the data unit accessed by the read command with the number of the data unit to be read by the read command not less than the threshold value.

According to a twelfth ECC module of the third aspect of the present application, there is provided the thirteenth ECC module of the third aspect of the present application, wherein the address calculator obtains the start address of the data unit corresponding to the data to be read by the read command by modulo the size of the data unit by the start address of the storage space of the data to be read by the read command.

According to a thirteenth ECC unit of the third aspect of the present application, there is provided the fourteenth ECC module according to the third aspect of the present application, wherein the address calculator is according to a formula Addr_ecc＝Addr_org+Addr_org>>N+(Addr_orgthe/M) x 16 calculation of the memory address of an ECC cell, where each operation is an integer operation, Addr_eccIs the starting address, Addr, of the ECC cell_orgThe starting address of the data unit, N is the shift number, and M is the size of the storage space occupied by the data unit.

According to one of the twelfth to fourteenth ECC modules of the third aspect of the present application, there is provided the fifteenth ECC module of the third aspect of the present application, wherein the ECC decoder performs ECC check on the check data and the data unit, and in response to a failure of the check, the ECC decoder sends information of the memory access abnormality to the host device.

According to one of the twelfth to fifteenth ECC units of the third aspect of the present application, there is provided a sixteenth ECC module according to the third aspect of the present application, further comprising: a slave device interface and a master device interface; the slave device interface is coupled with the complete data cache, the single beat cache, the address calculator and the partial write detector, and interacts with the bus in a manner of a slave device conforming to a bus protocol; a master interface is coupled to the ECC insertion unit, the ECC splitting unit, the address calculator, and the read-modify-write controller, and interacts with the DRAM controller in a manner compliant with a master protocol of the bus protocol.

According to one of the first to sixteenth ECC units of the third aspect of the present application, there is provided the seventeenth ECC module according to the third aspect of the present application, wherein the address calculator is according to a formula

According to a fourth aspect of the present application, there is provided a method of providing ECC for a memory device according to the first aspect of the present application, comprising: calculating check data for a data unit to be written by the write command, and adding the check data to the data unit to obtain an ECC unit; calculating the storage address of an ECC unit corresponding to the data unit according to the data unit address indicated by the write command; a write command is generated indicating a memory address of the ECC unit to write the ECC unit to the DRAM.

A first method of providing a memory device with ECC according to a fourth aspect of the present application, a second method of providing a memory device with ECC according to the fourth aspect of the present application is provided, wherein parity data is appended to designated locations of data cells to generate ECC cells.

A second method of providing a memory device with ECC in accordance with the fourth aspect of the present application provides a third method of providing a memory device with ECC in accordance with the fourth aspect of the present application, wherein the designated location is after the data unit.

According to one of the first to third methods of providing ECC for a memory device of the fourth aspect of the present application, there is provided a method of providing ECC for a memory device of the fourth aspect of the present application, further comprising: in response to receiving the write command, caching a data unit to be written by the write command into a data cache; and calculating the check data of the data units cached to the data cache.

A fourth method of providing ECC for a memory device according to the fourth aspect of the present application provides a fifth method of providing ECC for a memory device according to the fourth aspect of the present application, wherein the size of the data cache is equal to the maximum transfer length of the bus.

According to one of the first to fifth methods of providing ECC for a memory device of the fourth aspect of the present application, there is provided a method of providing ECC for a memory device of the sixth aspect of the present application, further comprising: in response to writing the ECC unit to the DRAM, information that the write command processing is complete is sent to the master device that issued the write command.

A seventh method of providing ECC for a memory device according to the fourth aspect of the present application is provided, wherein a portion of a specified size of an ECC cell is filled with an arbitrary value after a data cell is appended with check data, wherein the ECC cell is a byte-aligned memory cell to which the data cell is appended with check data.

According to one of the first to seventh methods of providing ECC for a memory device of the fourth aspect of the present application, there is provided a method of providing ECC for a memory device of the eighth aspect of the present application, wherein Addr is given according to the formula_ecc＝Addr_org+Addr_org>>N+(Addr_orgthe/M) x 16 calculation of the memory address of an ECC cell, where each operation is an integer operation, Addr_eccIs the starting address, Addr, of the ECC cell_orgIs a data unitN is the shift number and M is the size of the memory space occupied by the data unit.

According to one of the first to eighth methods of providing ECC for a memory device according to the fourth aspect of the present application, there is provided a ninth method of providing ECC for a memory device according to the fourth aspect of the present application, wherein ECC units are arranged end to end from a start address of an ECC block in the ECC block, wherein the ECC block is a storage space of a size specified in a DRAM.

A ninth method of providing ECC for a memory device according to the fourth aspect of the present application, and a tenth method of providing ECC for a memory device according to the fourth aspect of the present application, wherein a memory space not occupied by an ECC unit at the end of an ECC block is filled with specified data or random data.

A method of providing ECC for a memory device according to the ninth or tenth aspect of the present application, a method of providing ECC for a memory device according to the eleventh aspect of the present application is provided, wherein ECC units of an ECC block are written to a DRAM through a bus transfer unit.

A method of providing ECC for a memory device according to an eleventh aspect of the present application, a method of providing ECC for a memory device according to a twelfth aspect of the present application, wherein a size of the specified number of bus transfer units is the same as a size of one ECC block.

A method of providing ECC for a memory device according to the eleventh or twelfth aspect of the present application, a method of providing ECC for a memory device according to the thirteenth aspect of the present application, wherein, in one clock cycle, a bit width of writing data to a DRAM is one bus transfer unit.

A thirteenth method of providing ECC for a memory device according to the fourth aspect of the present application provides a method of providing ECC for a memory device according to the fourteenth aspect of the present application, wherein validity of each data transferred by the bus transfer unit is signaled in one clock cycle.

According to a thirteenth or fourteenth aspect of the present application, there is provided a method for providing ECC for a memory device, wherein the method for providing ECC for a memory device according to the fifteenth aspect of the present application, wherein the number of bus transfer units for a full bus transfer is determined by a configuration of the size of a data unit, the size of an ECC unit, and the bus bit width, wherein all bus transfer unit sizes for a full bus transfer are equal to the size of all ECC units transferred in a full bus transfer, and each piece of data of each bus transfer unit of all bus transfer units is valid.

According to one of the methods of providing ECC for a memory device of the fourth aspect of the present application, there is provided a method of providing ECC for a memory device of the sixth aspect of the present application, wherein the method is based on a formula

According to a fifth aspect of the present application, there is provided a method of providing ECC for a memory device according to the first aspect of the present application, comprising: calculating the storage address of an ECC unit corresponding to the data unit according to the data unit address indicated by the read command; generating a read command for indicating the storage address of the ECC unit, and reading the ECC unit from the DRAM; splitting the ECC unit to obtain check data and a data unit, and checking the data unit through the check data; and if the checking is passed, reading the data unit corresponding to the ECC unit.

A first method of providing ECC for a memory device according to the fifth aspect of the present application provides a second method of providing ECC for a memory device according to the fifth aspect of the present application, further comprising: and if the verification fails, sending information of memory access abnormity to the main equipment.

The first method for providing the memory device with the ECC according to the fifth aspect of the present application provides a method for providing the memory device with the ECC according to the third aspect of the present application, wherein in response to the verification passing, the data unit corresponding to the ECC unit is stored in the data cache, and the data unit is read out from the data cache.

A third method of providing ECC for a memory device according to the fifth aspect of the present application, a fourth method of providing ECC for a memory device according to the fifth aspect of the present application is provided, wherein a size of the data cache is equal to a maximum transfer length of the bus.

According to one of the first to fourth methods of providing the memory device with ECC of the fifth aspect of the present application, there is provided the method of providing the memory device with ECC of the fifth aspect of the present application, wherein the designated portion of the ECC unit is taken as the data unit, and the other portion of the ECC unit is taken as the check data, so as to split the ECC unit.

According to one of the first to fifth methods of providing ECC for a memory device of the fifth aspect of the present application, there is provided a method of providing ECC for a memory device of the sixth aspect of the present application, wherein Addr is given according to the formula_ecc＝Addr_org+Addr_org>>N+(Addr_orgthe/M) x 16 calculation of the memory address of an ECC cell, where each operation is an integer operation, Addr_eccIs the starting address, Addr, of the ECC cell_orgThe address of the data unit, N is the shift number, and M is the size of the storage space occupied by the data unit.

According to one of the first to sixth methods of providing a memory device with ECC according to the fifth aspect of the present application, there is provided a method of providing a memory device with ECC according to the seventh aspect of the present application, wherein ECC units are arranged end-to-end from a start address of an ECC block in the ECC block, wherein the ECC block is a storage space of a size specified in a DRAM.

A seventh method of providing ECC for a memory device according to the fifth aspect of the present application, a eighth method of providing ECC for a memory device according to the fifth aspect of the present application is provided, wherein a memory space at the end of an ECC block not occupied by an ECC cell is filled with specified data or random data.

A seventh or eighth method of providing ECC for a memory device according to the fifth aspect of the present application, a ninth method of providing ECC for a memory device according to the fifth aspect of the present application is provided, wherein ECC units of an ECC block are read out from a DRAM through a bus transfer unit.

A ninth method of providing ECC for a memory device according to the fifth aspect of the present application, and a tenth method of providing ECC for a memory device according to the fifth aspect of the present application, wherein a size of the specified number of bus transfer units is the same as a size of one ECC block.

A ninth or tenth method of providing ECC for a memory device according to the fifth aspect of the present application, there is provided the eleventh method of providing ECC for a memory device according to the fifth aspect of the present application, wherein a bit width of data read out from the DRAM in one clock cycle is one bus transfer unit.

A method of providing ECC for a memory device according to the eleventh aspect of the present application, and a method of providing ECC for a memory device according to the twelfth aspect of the present application, wherein validity of each data transferred by the bus transfer unit is signaled in one clock cycle.

A method of providing ECC for a memory device according to the eleventh or twelfth aspect of the present application, wherein the number of bus transfer units for a full bus transfer is determined by a configuration of a size of a data unit, a size of an ECC unit, and a bus bit width, wherein all bus transfer unit sizes for a full bus transfer are equal to the size of all ECC units transferred in a full bus transfer, and each piece of data of each bus transfer unit of all bus transfer units is valid.

According to one of the methods of providing ECC for a memory device of the first to thirteenth aspects of the present application, there is provided a method of providing ECC for a memory device of the fourteenth aspect of the present application, wherein the method is based on a formula

According to a sixth aspect of the present application, there is provided a first ECC module according to the sixth aspect of the present application, comprising: an ECC encoder, an ECC insertion unit and an address calculator; the address calculator calculates the storage address of the ECC unit corresponding to the data unit according to the data unit address indicated by the write command; the ECC encoder calculates check data for a data unit to be written by the write command; the ECC insertion unit adds the check data to the data unit to obtain an ECC unit to be stored to the ECC unit storage address.

The first ECC module according to a sixth aspect of the present application provides the second ECC module according to the sixth aspect of the present application, wherein the ECC insertion unit appends the check data to a designated location of the data unit to generate the ECC unit.

The first or second ECC module according to the sixth aspect of the present application provides the third ECC module according to the sixth aspect of the present application, further comprising: an ECC decoder and an ECC splitting unit; the address calculator calculates the storage address of the ECC unit corresponding to the data unit according to the data unit address indicated by the read command; the ECC splitting unit splits the ECC unit read from the storage address of the ECC unit to obtain check data and a data unit; and the ECC decoder checks the data unit through the check data, and if the check is passed, the data unit corresponding to the ECC unit is output.

The third ECC unit according to the sixth aspect of the present application provides the fourth ECC module according to the sixth aspect of the present application, wherein the ECC decoder sends information of the memory access abnormality to the master device if the check fails.

According to a third or fourth ECC unit of a sixth aspect of the present application, there is provided the fifth ECC module of the sixth aspect of the present application, wherein the ECC splitting unit splits the ECC unit by using a designated portion of the ECC unit as a data unit and using other portions of the ECC unit as check data.

According to one of the first to fifth ECC units of the sixth aspect of the present application, there is provided a sixth ECC module according to the sixth aspect of the present application, further comprising: a data buffer coupled to the ECC encoder and/or the ECC decoder; the data cache stores data units to be written in by the write command, and the ECC encoder calculates check data for the data units cached to the data cache; and/or the data cache buffers the data units read out after the check passes.

According to one of the first to sixth ECC units of the sixth aspect of the present application, there is provided the seventh ECC module according to the sixth aspect of the present application, wherein the address calculator is according to the formula Addr_ecc＝Addr_org+Addr_org>>N+(Addr_orgthe/M) x 16 calculation of the memory address of an ECC cell, where each operation is an integer operation, Addr_eccIs the starting address, Addr, of the ECC cell_orgThe address of the data unit, N is the shift number, and M is the size of the storage space occupied by the data unit.

According to a sixth or seventh ECC unit of the sixth aspect of the present application, there is provided an eighth ECC module according to the sixth aspect of the present application, further comprising: a slave device interface and a master device interface; a slave interface coupled to the data cache and the address calculator and interacting with the bus in a slave manner compliant with a bus protocol; a master interface is coupled to the ECC insertion unit, the ECC splitting unit, and the address calculator, and interacts with the DRAM controller in a manner that conforms to a master protocol of the bus protocol.

According to one of the first to eighth ECC units of the sixth aspect of the present application, there is provided the ninth ECC module according to the sixth aspect of the present application, wherein the address calculator is according to a formula

Calculating the memory address of an ECC cell, wherein each operation is an integer operation, Addr_eccIs the starting address, Addr, of the ECC cell_orgIs the address of the data unit, N is the data length of the ECC unit, M is the size of the storage space occupied by the data unit in the ECC block, S is 4K for eachThe number of bytes skipped.

According to a seventh aspect of the present application, there is provided a first storage device according to the seventh aspect of the present application, comprising: the system comprises a bus, a master device, an ECC module and a DRAM controller; the master device is coupled to the bus, and the ECC module couples the DRAM controller to the bus; the ECC module receives a read command/write command of the host device and executes one of the methods for providing ECC for the electronic device, and the ECC module further instructs the DRAM controller to write data into the DRAM or read data from the DRAM.

According to a first memory device of a seventh aspect of the present application, there is provided a second memory device of the seventh aspect of the present application, wherein the ECC module interacts with the bus according to a bus protocol, and the ECC module interacts with the DRAM controller according to the bus protocol.

According to a first or second memory device of a seventh aspect of the present application, there is provided a third memory device of the seventh aspect of the present application, wherein the ECC module includes a slave interface and a master interface, the slave interface interacting with the bus in a slave manner compliant with the bus protocol, and the master interface interacting with the DRAM controller in a master manner compliant with the master protocol of the bus protocol.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 illustrates a block diagram of an electronic system in accordance with an embodiment of the present application;

FIG. 2 illustrates a block diagram of an ECC module in accordance with an embodiment of the present application;

FIG. 3 illustrates a schematic diagram of data organization according to an embodiment of the application;

FIG. 4 shows a schematic diagram of an ECC block and a bus transfer unit according to an embodiment of the present application;

FIG. 5 illustrates a timing diagram of a bus transfer according to an embodiment of the present application;

FIG. 6 is a flow chart of processing a write command and a read command according to an embodiment of the present application;

FIG. 7 illustrates a block diagram of an ECC module in accordance with yet another embodiment of the present application;

FIG. 8 illustrates a schematic diagram of processing a read command according to an embodiment of the present application;

FIG. 9 illustrates a timing diagram of a bus transfer according to yet another embodiment of the present application;

FIG. 10 illustrates a schematic diagram of processing a read command according to yet another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

FIG. 1 is a block diagram of an electronic system according to an embodiment of the present application.

An electronic device, such as a SoC (System On Chip), includes a bus and a device coupled to the bus. Devices that are typically coupled to a bus include two types of devices, a master and a slave. In FIG. 1, CPU 110 and DMA unit 115 are coupled to the bus as masters, and DRAM controller 140 is coupled to the bus as a slave. Bus 120 is, for example, an axi (advanced Extensible interface) bus.

A DRAM (dynamic Random Access memory) controller 140 couples DRAM150 to the bus. Neither DRAM controller 140 nor DRAM150 has ECC functionality. ECC module 130 couples DRAM controller 140 to bus 120 and bridges bus 120 and DRAM controller 140. The ECC module 130 interacts with the bus 120 in, for example, an AXI bus protocol, while the ECC module 130 and the DRAM controller 140 also interact in the bus protocol, thereby eliminating the need to modify the DRAM controller 140 that would otherwise be directly coupled to the bus. Optionally, the ECC module 130, the DRAM controller 140, and the DRAM150 interact with each other according to the same or different bus protocols.

The ECC module 130 adds check data to the data unit written into the DRAM150 by the master device to obtain an ECC unit. By way of example, the data unit size is 32 bytes, and the ECC unit size is 34 bytes. It is understood that although the ECC unit generated for the data unit is 34 bytes, the size of the check data generated for the data unit by the ECC module 130 may be between 0-2 bytes. The data unit is filled with any value, and the data unit is not larger than the ECC unit (34 bytes) after the check data is added.

The access and transmission between the ECC module 130 and the bus 120 are performed in units of data, and the access and transmission between the ECC module 130 and the DRAM controller 140 are performed in units of ECC. Thus, the memory space used by the bus master is filled by the data units, and the memory space used by the ECC module 130 is filled by the ECC units. This results in different sizes of the memory spaces used by the bus master and the ECC module 130, and different addresses of the data unit and the ECC unit corresponding to the data unit in the memory spaces. The ECC module 130 also performs address translation for the data unit and the ECC unit.

The data units correspond to the ECC units one by one.

Fig. 2 illustrates a block diagram of an ECC module according to an embodiment of the present application.

The ECC module 130 couples the DRAM controller 140 to the bus 120 (see also fig. 1).

The ECC module 130 includes a slave interface 210 and a master interface 270. The ECC module 130 is coupled to the bus 120 as a slave, and the slave interface 210 interacts with the bus 120 in a manner compliant with a slave protocol of the bus protocol. The ECC module 130 accesses the DRAM controller 140 as a master, the DRAM controller 140 as a slave, and the master interface 270 interacts with the DRAM controller 140 in a manner that conforms to a master protocol of the bus protocol.

The slave interface 210 receives read and/or write commands to the memory from the bus 120 and processes the read and/or write commands by other units of the ECC module 130. Master interface 270 sends read and/or write commands to DRAM controller 140 for memory and receives responses from DRAM controller 140 to the read and/or write commands.

The ECC module 130 further includes an address calculator 230 for calculating an address of a corresponding ECC unit according to an address of a data unit accessed by the read command and/or the write command received and provided from the device interface 210. For example, Addr_ecc＝Addr_org+Addr_org>>4+(Addr_org3840). times.16, wherein Addr_eccIs the calculated starting address of the ECC cell, and Addr_orgIs the address of the data unit provided from the device interface 210 and wherein each operation is an integer number operation.

The complete data buffer 220 is used for buffering data corresponding to a write command received from the bus 120 by the device interface 210 or read data received from the host interface 270. The complete data cache 220 stores one or more data units without including parity data corresponding to the data units. The full data cache 220 is, for example, plural, and each full data cache 220 has a size of, for example, 128 bytes or 256 bytes. Still alternatively, the size of the full data cache 220 is equal to the maximum transfer length of the bus 120 (e.g., 128 bytes or 256 bytes).

The ECC encoder 240 and the ECC decoder 242 are coupled to the full data cache 220. The ECC encoder 240 performs error correction encoding on the data units in the full data buffer 220 and generates check data. The ECC encoder 240 provides the data unit and the generated check data to the ECC insertion unit 260. The ECC insertion unit 260 appends the verification data to the specified location of the data unit (e.g., after appending to the data unit) and provides to the host interface 270.

The ECC unit received by master interface 270 from DRAM controller 140 is split into data units and check data by ECC split unit 262. The ECC split unit 262 treats a designated portion of the ECC unit (e.g., the first 32 bytes) as a data unit and other portions of the ECC unit (e.g., the last 2 bytes, or a number of bits starting from the 31 st byte) as check data. ECC split unit 262 provides the split data unit and the check data to ECC decoder 242. ECC decoder 242 performs a check on the data cells based on the check data. If the check passes, ECC decoder 242 stores the data unit in one of the full data caches 220 (and discards the check data); if the check fails, ECC decoder 242 indicates a memory access exception (e.g., an ECC check exception) to the master device of bus 120 via slave interface 210.

FIG. 3 illustrates a schematic diagram of data organization according to an embodiment of the application.

According to the embodiment of the present application, the ECC units are sequentially placed in the storage space provided by the DRAM150, and the next ECC unit is stored at the end of the previous ECC unit. The ECC unit comprises a data unit and check data. Thus, if the master uses Addr_orgAs the starting address of the data unit, and aligned by the size of the data unit (e.g., 32 bytes), the starting address of the ECC unit is Addr_eccWherein Addr_ecc＝Addr_org+Addr_org>>N+(Addr_orgWhere N is 4 (corresponding to a shift of 4 bits to the right indicating that each 32 bytes is filled with 2 bytes of check data), M is 3840 (indicating that only 3840 bytes of space are used in the memory space of the host-aware data unit (4080 bytes are used in the DRAM memory space) per 4KB of memory space, and the remaining 16 bytes are not sufficient to store the complete ECC unit).

According to an embodiment of the present application, the 4KB storage space of DRAM150 is referred to as an ECC block. Each ECC block stores 120 ECC cells (for example, each ECC cell is 34 bytes in size), and ECC cells are arranged end to end in the ECC block, starting from the start address of the ECC block, and the last 16 bytes of the ECC block are not occupied by ECC cells, and can be filled with specified data, a random number, or remain empty.

Generally, according to

Calculating the memory address of an ECC cell, wherein each operation is an integer operation, Addr_eccIs the starting address, Addr, of the ECC cell_orgThe address of the data unit, N is the data length of the ECC unit, M is the size of the storage space occupied by the data unit in the ECC block, S is the space not occupied by the ECC unit in each ECC blockThe size of the address space of (a). The ECC block has a memory space of, for example, 4KB, 8KB, or other size.

Fig. 4 shows a schematic diagram of an ECC block and a bus transfer unit according to an embodiment of the present application.

The bus transfer unit is data transferred by the bus in one beat (beat). In the example of fig. 4, the size of the bus transfer unit is 16 bytes. A plurality of bus transfer units (420, 422, 424, 426 … …) are shown in fig. 4 for transferring data between the DRAM controller 140 and the ECC module 130.

Also shown in fig. 4, the ECC block 410 includes a plurality of ECC cells (450, 452 … …) and a padding cell 460. The size of each ECC unit is, for example, 34 bytes, and the size of the padding unit is 16 bytes. In the example of fig. 4, the data organization of the ECC block is the same as that of fig. 3.

FIG. 4 also shows that ECC units are placed at addresses in ECC block 410, e.g., ECC unit 450 is placed in the storage space from address 0 to address 33, and ECC unit 452 is placed in the storage space from address 34 to address 67.

And the bus transfer unit corresponds to a specified address range. In the example of fig. 4, the bus transfer units are 16-byte aligned, i.e., the data transferred by the bus transfer units always comes from or is written into the memory space provided by the 16-byte aligned DRAM. Referring to FIG. 4, the data transferred by the bus transfer unit 420 comes from address spaces 0:15, and the data transferred by the bus transfer unit 422 comes from address spaces 16: 31. Thus, if data in address space 5:10 is to be read, the portion of bus transfer unit 420 corresponding to address space 5:10 carries data, whereas the portions thereof corresponding to address spaces 0:4 and 11:15 hold data that is not valid, but the amount of data carried by bus transfer unit 420 is to hold 16 bytes. In this case, the bus utilization rate is lowered due to the presence of the invalid data.

FIG. 5 shows a timing diagram of a bus transfer according to an embodiment of the application.

From left to right is the direction of time lapse. AXI _ CLK represents the bus clock, with the bus transferring one beat per clock cycle, for example, 16 bytes of data. Taking the clock cycle 510 as an example, in the clock cycle, the data W0 to W7 transferred by the AXI _ wdata signal represent 16 bytes of data in one beat transferred, wherein the size of each of the data W0 to W7 is 2 bytes. The AXI _ wstrb signal indicates which of the data transferred in the current beat are valid. In clock cycle 510, the AXI _ wstrb signal is 0xff (each of the 8 bits is 1), indicating that 8 copies of the data for W0 through W7 for the current beat are all valid.

Since an ECC unit includes 34 bytes, in the example of fig. 5, 32 bytes of data, which are transferred in 2 beats in clock cycle 510 and clock cycle 512, are data units, while clock cycle 514 transfers an "ECC" indication check unit in 15:0 bits of the AXI _ wdata signal, and the data unit and the check unit constitute one ECC unit. While other data than "ECC" transferred in clock cycle 514 belongs to another ECC unit.

The bit width of the AXI _ wdata signal is 128 bits (16 bytes). Portions of the AXI _ wdata signal correspond to the memory space provided by the DRAM. For example, the 15:0 bits of the AXI _ wdata signal are dedicated to transfer the first 2 bytes of a 16 byte aligned cell in DRAM address space, the starting address of the 2 bytes being an integer multiple of 16. And 31:16 bits of the AXI wdata signal, the remainder of the transmitted 2 bytes of data, starting address modulo 16, in the DRAM address space is 2.

In the example of fig. 5, 272 bytes of data, including 16 bytes of parity data, are transferred in 17 beats, and all bits of the AXI _ wdata signal in each beat are transferred as valid data. In this case, the bus utilization is maximized, and the bus transfer efficiency caused by the parity data is 256/272-94.12%. Thus, the completion of the transfer of 256 bytes of data of 8 data units as a whole by 17 beats (including 16 bytes of check data required for 8 ECC units) on the bus is a configuration that maximizes the bus transfer efficiency in the embodiment according to the present application. This transfer is referred to as a full bus transfer. It will be appreciated that other configurations for the size of the data unit, the size of the ECC unit, and the width of the bus bit will be known to those skilled in the art to maximize bus transfer efficiency.

FIG. 6 is a flow chart of processing a write command and a read command according to an embodiment of the present application.

The host (e.g., CPU 110, DMA unit 115, see also fig. 1) accesses the memory space filled by the data units, and the ECC module 130 receives the host's memory space access command and converts it into an access command to the memory space filled by the ECC unit. The ECC module 130 performs address translation on the memory access command from the host device. For a write command, check data is also generated for the data to be written to get the ECC unit and instruct DRAM controller 140 to write the ECC unit to DRAM 150. For a read command, the ECC module 130 performs data check on the ECC unit read from the DRAM controller 140 and extracts a data unit in the ECC unit as a response to the read command of the host device 110.

As an example, the ECC module 130 processes write commands provided by the master device 110. The ECC module 130 receives and buffers the write command from the master (1). The ECC module 130 calculates a storage address of the corresponding ECC unit according to the address indicated by the write command. The ECC module 130 calculates check data for data to be written by the write command, and the data to be written by the write command and the check data constitute an ECC unit.

The ECC module 130 generates a write command for writing the ECC unit into the DRAM, and sends the write command to the DRAM controller 140(2), where the write command indicates a storage address of the ECC unit generated by the ECC module 130. Since the data cells of the ECC cells are contiguous with the check data over the memory space, the ECC cells are written to the DRAM by a single command provided to the DRAM controller 140.

In response to writing the ECC unit to the DRAM, the DRAM controller 140 informs the ECC module 130 that the write command processing is complete (3). In turn, the ECC module 130 informs the master 110 that the write command processing is complete (4).

As yet another example, the ECC module 130 processes read commands provided by the master device 110. The ECC module 130 receives a read command from the host device 101 (5). The ECC module 130 then calculates the memory address of the ECC unit containing the data to be read, according to the address indicated by the read command. The ECC module 130 generates a read command for reading out the ECC unit from the DRAM, and transmits the read command to the DRAM controller 140(6), the read command indicating a memory address of the ECC unit generated by the ECC module 130.

The DRAM controller 140 supplies the read ECC unit to the ECC module (7) as a response to the read command. The ECC unit accommodates data to be read by a read command of the host device and check data. The ECC module 130 performs error checking on the ECC unit, and if no error is found or an existing error is corrected, the ECC unit 130 provides the data to the master device 110 as a response to a read command of the master device 110 (8).

FIG. 7 illustrates a block diagram of an ECC module in accordance with yet another embodiment of the present application.

The ECC module 130 includes a bus slave interface 210 and a master interface 270. The ECC module 130 is coupled to the bus 120 as a slave, and the slave interface 210 interacts with the bus 120 in a manner compliant with a slave protocol of the bus protocol. The ECC module 130 accesses the DRAM controller 140 as a master, the DRAM controller 140 as a slave, and the master interface 270 interacts with the DRAM controller 140 in a manner that conforms to a master protocol of the bus protocol.

The ECC module 130 further includes an address calculator 730 for calculating an address of a corresponding ECC unit according to an address of a data unit accessed by the read/write command received and provided from the device interface 210.

The ECC module 130 further includes a full data buffer 720 and a single beat buffer 725.

The complete data buffer 720 is used for buffering data corresponding to a write command received from the bus 120 by the device interface 210 or read data received from the host interface 270. Complete data cache 720 stores one or more data units without including parity data corresponding to the data units. There are, for example, multiple full data buffers 720, each full data buffer 720 having a size of, for example, 128 bytes or 256 bytes. Still alternatively, the size of full data cache 720 is equal to the maximum transfer length of bus 120 (e.g., 128 bytes or 256 bytes).

The single beat cache 725 is used to cache data corresponding to write commands received from the bus 120 by the slave device interface 210 or read data received from the master device interface 270. The single beat cache 725 can hold one data unit and does not store check data. The single-beat cache 725 has, for example, a plurality, and each single-beat cache 725 has a size of, for example, 16 bytes. Still alternatively, the size of the single-beat cache 725 is equal to two beats of bits (e.g., 32 bytes) of the bus 120.

The CPU 110, as a master, accesses to the memory space typically access smaller size data, e.g., 1 byte, 2 bytes, or 4 bytes. The single beat cache 725 is used to accommodate data accessed by read/write commands from the host device that access smaller sized data. Thereby reducing waste of cache space. The DMA unit 115, acting as a master, accesses to memory space typically access data of a larger size, for example 512 bytes or 4 KB. One or more full data buffers are used to accommodate data accessed by read/write commands from the master device that access data of larger size.

The ECC module 130 allocates the single beat buffer 725 and/or the full data buffer 720 according to the size of data accessed by a read command or a write command received from the device interface 210. For a read/write command to access small-sized data, the single-beat cache 725 is preferentially allocated, and in the case where the single-beat cache 725 is exhausted, the complete data cache 720 is allocated. For read/write commands that access large size data (the size of the data being accessed exceeds the capacity of a single beat buffer), the full data buffer 720 is preferentially allocated. Still alternatively, the one-shot cache 725 may be preferentially allocated for read/write commands from the CPU 110, while the full data cache 720 may be preferentially allocated for read/write commands from the DMA unit 115. It will be appreciated that other masters on the bus may be assigned a preferred cache for use as either the beat cache 725 or the full data cache 720 depending on the size characteristics of their data accesses.

ECC encoder 240 and ECC decoder 242 are coupled to full data buffer 720 and single beat buffer 725.

ECC module 130 also includes a "partial write" detector 780 and a "read-modify-write" controller 785.

A "partial write" is a write command where the memory space accessed by the write command is part, but not all, of the data unit (aligned by 32 bytes). For example, a write command that accesses a 0:5 byte address space will cause a "partial write" operation. As yet another example, a write command accessing a 28:40 byte address space provided by two data units (0: 31 bytes and 32:63 bytes, respectively), would cause two "partial write" operations.

The "partial write" detector 780 identifies whether the write command will cause a "partial write" operation based on the address and length of the write command that the bus obtained from the device interface 210. For example, if the start address of the address space accessed by the write command is not at a 32-bit aligned boundary (the quotient of modulo 32 is not 0), then a "partial write" operation will be caused at the start address. As another example, if the trailing address of the address space accessed by the write command is not before the 32-bit aligned boundary (the quotient of modulo 32 is not 31), then a "partial write" operation will be caused at the trailing address.

In response to the partial write detector 780 recognizing the partial write, the read-modify-write controller 785 processes the partial write operation. The "read-modify-write" controller 785 calculates the starting address of the (32 byte aligned) data unit accessed by the "partial write" operation, calculates the corresponding ECC unit address via the address calculator 730, generates a read command requesting the DRAM controller 140 to read the ECC unit, and stores the data unit of the ECC unit in the allocated full data buffer 720 or the "read" portion of the "read-modify-write" buffer 725. The "read-modify-write" controller 785 updates the read data unit with the data corresponding to the "partial write" operation, and the updated data unit remains stored in the allocated full data buffer 720 or the single-beat buffer 725 (the "modify" portion of the "read-modify-write"). And a "read-modify-write" controller 785 instructs ECC encoder 240 to generate check data for the updated data unit and to generate an ECC unit via ECC insertion unit 260 and to write the ECC unit to DRAM (the "write" portion of "read-modify-write"). The address of DRAM150 to which the ECC unit is written is the same address as the address at which the ECC unit was read from the DRAM for the partial write operation.

Alternatively, upon receiving a write command, the slave device interface 210 buffers data to be written by the write command in the full data buffer 720 or the single-beat buffer 725, and in the processing of the "partial write" operation, data of a data unit corresponding to an ECC unit read from the DRAM controller 140 is used to fill a partial data missing from a data unit in the full data buffer 720 or the single-beat buffer 725 corresponding to the "partial write" operation.

Still alternatively, the "partial write" detector 780 detects whether there is a partial write operation in beats 1 and last 1 of the data corresponding to the received write command from the device interface 210. In one example, for data transferred by multiple beats of the bus, a "partial write" condition may exist only for beat 1 or the last beat 1. For example, if the bus AXI _ wstrb signal is not 0xff at beat 1 or the last beat 1, it is recognized that there is a "partial write". In yet another example, if the bus AXI _ wstrb signal is 0xff for beat 1 or the last beat 1, but the starting address of the transferred data is an integer multiple of 16 bytes but not an integer multiple of 32 bytes (e.g., see fig. 5, if beat 1 corresponds to clock cycle 512), then a "partial write" condition is identified.

The ECC module 130 also handles "non-aligned read" operations. By way of example, the size of an ECC unit is 34 bytes, and the size of a bus transfer unit is 16 bytes (one beat), so that to read one ECC unit, 3 bus transfer units are used. And since the size of an ECC unit is 34 bytes, not a multiple of 16 bytes, the storage space of an ECC unit is often not 16 byte aligned. The ECC module 130 determines, for a read command provided by the host device, an ECC unit required to be retrieved from the DRAM150 in response to the read command according to the starting address and the length of the memory space accessed by the read command.

FIG. 8 illustrates a schematic diagram of processing a read command according to an embodiment of the present application.

By way of example, the address range of the data to be accessed is 5:40 bytes, and the data of the address range is provided by two data units (the address ranges are 0:31 bytes and 32:63 bytes, respectively). These two data units correspond to ECC unit 810 and ECC unit 812, respectively. To read ECC unit 810 and ECC unit 812 (68 bytes total), 5 bus transfer units (820, 822, … … 830) are required.

The address calculator calculates a start address of the ECC unit 810. The size (32) of the data unit is modulo according to the starting address "5" of the address range in which the data is to be accessed, resulting in a result "0" as the starting address of the data unit corresponding to the starting address "5". And obtaining the starting address addrec of the ECC unit 810 corresponding to the data unit according to addrec ═ addrrg + addrrg > > N + (addrrg/M) × 16, wherein N is 4, and M is 3840. And according to the size of the address range of the data to be accessed is 35 bytes, it is obtained that the address range is provided by 2 data units (the address range of the data to be accessed is modulo the data unit size, the result is rounded up), it is obtained that the address range is provided by 2 ECC units, and thus the length of the data to be read out from the DRAM is the size of 2 ECC units. So that the read command issued by the ECC module 130 to the DRAM controller 140 is to read data of 2 ECC units in length starting from the start address addrec of the ECC unit 810.

As an example, data of 2 ECC units length is read starting from the start address Addrecc of the ECC unit 810, using 5 bus transfer units. And the address range (ECC unit address space) of the data carried by the last bus transfer unit 830 is 64:79 bytes. And the portion of the address range occupied by ECC cells 812 is 64:67 bytes. So that only the part of the bus transfer unit 830 used to carry the 64:67 byte address range is valid data and the other part does not need to be filled with valid data.

Referring also to FIG. 9, clock cycle 910 transfers a portion of data that is not valid data (indicated by grid shading) in the beat corresponding to clock cycle 912.

The address range of data to be read by a read command is 5:10 bytes, and the data of the address range is supplied by one data unit (the address range is 0:31 bytes). The data unit corresponds to the ECC unit 1010. To read ECC unit 1010, 3 bus transfer units (1020, 1022, and 1024) are required. Through these three bus transfer units, the ECC unit 1010 is read out from the DRAM 150. And performing error correction on the data unit and the check data of the ECC unit 1010 to obtain a data unit. And retrieves from the data unit a portion of the address range in the address space of the data unit of 5:10 bytes, stores in a one-shot buffer, and responds to the read command.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for providing ECC for a memory device, comprising:

in response to receiving a write command, if the data to be written by the write command belongs to the address range of the first data unit, writing the data to be written by the write command into a single-beat cache, wherein the single-beat cache can accommodate one data unit;

calculating check data for the data units stored in the single-beat cache, and obtaining a first ECC unit corresponding to the first data unit; calculating the address of the first ECC unit according to the address of the first data unit;

a write command is generated indicating an address of the first ECC unit to write the first ECC unit to the DRAM.

2. The method of claim 1, wherein the method further comprises:

if the initial address of the address space accessed by the write command is not aligned with the boundary of the data unit, causing partial write operation at the initial address of the write command; alternatively, the first and second electrodes may be,

and if the tail address of the address space accessed by the write command is not aligned with the boundary of the data unit, causing partial write operation at the tail address of the write command.

3. The method of claim 1, wherein if a portion of the first beat of data of the bus transfer indicated by the write command is invalid data, the first beat of the bus transfer indicated by the write command causes a partial write operation;

or if partial data in the last beat of data transmitted by the bus indicated by the write command is invalid data, the last beat of data transmitted by the bus indicated by the write command causes partial write operation.

4. The method of claim 1, wherein the first beat of the bus transfer indicated by the write command causes a partial write operation if a starting address of the first beat of data of the bus transfer indicated by the write command is an integer multiple of a unit of the bus transfer and not an integer multiple of a unit of data; alternatively, the first and second electrodes may be,

if the starting address of the last beat of data of the bus transfer indicated by the write command is an integer multiple of the bus transfer unit, rather than an integer multiple of the data unit, then the last beat of the bus transfer indicated by the write command causes a partial write operation.

5. An ECC module, comprising: the device comprises a single-beat cache, an ECC encoder, an ECC insertion unit and an address calculator;

the single-beat cache stores data to be written by a write command belonging to the address range of the first data unit; the ECC encoder calculates check data for the data unit stored in the single-beat cache;

the ECC insertion unit generates a first ECC unit corresponding to the first data unit by using the check data and the data unit stored in the single-beat cache; the address calculator calculates an address storing the first ECC unit according to the address of the first data unit.

6. The ECC module of claim 5, further comprising: a partial write detector and a read-modify-write controller; the partial write detector identifies whether the write command causes a partial write operation; in response to recognizing that the write command causes a partial write operation, the address calculator calculates an address of an ECC unit corresponding to data accessed by the partial write operation; the read-modify-write controller generates a read command indicating an address of the ECC unit to read the ECC unit from the DRAM, and combines the data unit corresponding to the read ECC unit with the data to be written by the write command to obtain the data unit to be written stored in the single-beat buffer or the complete data buffer.

7. The ECC module of claim 6, wherein the partial write detector causes a partial write operation at a start address of a write command based on a misalignment of a start address of an address space accessed by the write command and a boundary of a data unit;

or the partial write detector obtains the position of the tail address of the write command according to the misalignment of the tail address of the address space accessed by the write command and the boundary of the data unit to cause the partial write operation.

8. The ECC module of claim 6 or 7, wherein the ECC module further comprises: an ECC decoder and an ECC splitting unit;

the address calculator calculates the address of an ECC unit corresponding to the data unit according to the address of the data unit corresponding to the data to be read out by the read command;

the ECC splitting unit splits the ECC unit read out from the ECC unit address to obtain check data and a data unit; the ECC decoder checks the data unit through the check data;

the single-beat cache stores and verifies the data to be read by the read command acquired from the data unit accessed by the read command with the number of the data unit to be read by the read command smaller than the threshold value;

and the complete data cache stores and verifies the data to be read by the read command acquired from the data unit accessed by the read command with the number of the data unit to be read by the read command not less than the threshold value.

9. The ECC module of claim 6, wherein the ECC module further comprises: a slave device interface and a master device interface;

the slave device interface is coupled with the complete data cache, the single beat cache, the address calculator and the partial write detector, and interacts with the bus in a manner of a slave device conforming to a bus protocol;

a master interface is coupled to the ECC insertion unit, the ECC splitting unit, the address calculator, and the read-modify-write controller, and interacts with the DRAM controller in a manner compliant with a master protocol of the bus protocol.

10. A storage device, comprising: the system comprises a bus, a master device, an ECC module and a DRAM controller; the master device is coupled to the bus, and the ECC module couples the DRAM controller to the bus; the ECC module receives a read command/write command of the main equipment and executes one of the methods for providing the ECC for the electronic equipment, and the ECC module also instructs the DRAM controller to write data into the DRAM or read data from the DRAM; the ECC module is as claimed in any one of claims 6-9.