CN101799678B - Three-way asynchronous serial-port data real-time synchronous transmitting system - Google Patents
Three-way asynchronous serial-port data real-time synchronous transmitting system Download PDFInfo
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- CN101799678B CN101799678B CN2009102432723A CN200910243272A CN101799678B CN 101799678 B CN101799678 B CN 101799678B CN 2009102432723 A CN2009102432723 A CN 2009102432723A CN 200910243272 A CN200910243272 A CN 200910243272A CN 101799678 B CN101799678 B CN 101799678B
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Abstract
The invention relates to a three-way asynchronous serial-port data real-time synchronous transmitting system. The invention realizes the multiway synchronization of high-rate serial ports in a hardware timing mode based on an FPGA, the three-way serial ports can synchronously or asynchronously transmit, the starting time intervals of data transmission in each way and among the three ways can be set by oneself, and the time precision for synchronous and asynchronous transmission reaches microsecond. Due to the high communication rate of the three-way serial ports, the invention realizes caching of the multiway serial ports by combining a cache region in an FPGA controller with an SDRAM, thereby avoiding loss of high-rate large-capacity data. In order to inspect the effect of the three-way asynchronous serial-port data real-time synchronous transmitting method, the invention uses an oscillograph to examine the electrical level feature and the synchronizing precision of the serial-port transmitted data. The test result indicates every way of the serial ports can normally receive and transmit data, the synchronizing precision error of the three-way serial ports is lower than 100 ns, and the serial-port communication rate reaches 2 Mbps.
Description
Technical field
The present invention relates to a kind of three-way asynchronous serial-port data real-time synchronous transmitting system, belong to the space flight measurement and control field.
Background technology
Serial communication is good with its technology maturation, reliability height, real-time, applying flexible, characteristics easy to use have obtained widespread use in the space flight measurement and control field, along with the development of carrier rocket of new generation and strategic arms and the development of world integrated technique, the rate of information throughput and the reliability of electrical system are had higher requirement.Under this background, high code check transmission, the multi-channel redundant communication technology are rapidly developed.Multi-channel redundant communication relates to the data synchronization problems between each passage, under to the not high situation of accuracy requirement lock in time, adopts common single-chip microcomputer or industrial computer promptly can realize.If but the requirement of time precision is reached microsecond or higher, and just be difficult to realize with aforesaid way, because the single-chip microcomputer execution command is serial, can not carries out multichannel data and transmit simultaneously; Though and commercial industrial computer multi-serial-port card has multi-channel serial port, the transmission of every road serial ports all needs independent control, do not possess multichannel sending function simultaneously, and the time precision of employing single channel order send mode depends on the timing accuracy of industrial computer operating system.Generally speaking, Windows operating system adopts the mode of medium timer can reach the Millisecond timing accuracy, and Vxworks operating system can reach 10 microsecond level timing accuracies, wants further to improve very difficulty of timing accuracy.
A new generation's carrier rocket pins down the triple redundance telemetry that the data source simulation project that discharges TT﹠C system need send simulation by 3 road RS-422 serial ports of a serial communication card, require three road serial ports can be synchronously or asynchronous transmission, the zero-time that sends data between data that every road sends and the Ge Lu can freely be set at interval, require synchronous and asynchronous time precision all to reach the microsecond level, serial ports highest communication speed is not less than 1Mbps.The precise synchronization that is difficult to realize multi-channel serial port in view of traditional approach.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of three-way asynchronous serial-port data real-time synchronous transmitting system is proposed, solved the data synchronization problems between each passage in the multichannel communication, three road serial ports can be synchronously or asynchronous transmission, the zero-time of the data that every road sends can freely be set, improved timing accuracy, time precision synchronous and asynchronous transmission reaches the microsecond level.
Technical solution of the present invention is: a kind of three-way asynchronous serial-port data real-time synchronous transmitting system, comprise the CPCI interface chip, the FPGA control circuit, No. three buffer circuits, three level shifting circuits, three interface protective circuits, crystal oscillator, SDRAM, EEPROM, the configuration information of EEPROM storage CPCI interface chip, after powering on, reads the CPCI interface chip configuration information of EEPROM storage CPCI interface chip, the parallel port data that host computer will send write in the internal data buffer memory of FPGA control circuit by the CPCI interface chip, SDRAM stores the parallel data in the FPGA control circuit internal data buffer memory, the timer of host computer in the FPGA control circuit sends enable signal, timer picks up counting according to the clock frequency that crystal oscillator produces, parallel-to-serial converter among the timer control FPGA carries out the parallel data taking-up and go here and there to change to form three road TTL signals from SDRAM, when the timer timing then, three road TTL signals after timer control parallel-to-serial converter will be changed are sent to three buffer circuits isolates, carry out level conversion through the TTL signal after isolating, export with the serial ports form by interface protective circuit at last;
Described FPGA control circuit comprises three timers, three parallel-to-serial converters, three write buffer area and three and read buffer area, the parallel data that is write by the CPCI interface chip writes three and writes in the buffer area, SDRAM stores three parallel datas that write in the buffer area, three timers receive the enable signal that host computer sends at the same time or separately, three clock frequency timing respectively that timer produces according to crystal oscillator after receiving enable signal, three parallel-to-serial converters are taken out to three with parallel data and read in the buffer area from SDRAM, three parallel-to-serial converters of three timer control carry out three parallel datas that read in the buffer area and go here and there to change forming three road TTL signals, when the timing of three timers then, three road TTL signal Synchronization or asynchronous output after three timer control parallel-to-serial converters will be changed.
Described buffer circuit adopts photoelectrical coupler to carry out the photoelectricity isolation; Level shifting circuit becomes the TTL conversion of signals rs 232 serial interface signal of difference; Interface protective circuit adopts four voltage stabilizing diodes to form, the positive pole butt joint of per two voltage stabilizing diodes, negative pole one end ground connection, another termination one tunnel difference rs 232 serial interface signal.
The present invention's advantage compared with prior art is: the present invention is by having realized that based on the hardware timing mode of FPGA the multichannel of high speed serial ports is synchronous, three road serial ports can be synchronously or asynchronous transmission, the zero-time that sends data between data that every road sends and the Ge Lu can freely be set at interval, time precision synchronous and asynchronous transmission reaches the microsecond level, because the traffic rate of three road serial ports is higher, host computer can not respond separately frame data, the mode that the present invention combines with SDRAM by the buffer area in the FPGA controller has realized the high-speed cache of multi-channel serial port, has avoided at a high speed, losing of Large Volume Data.In order to check the effect of the real-time method for synchronously sending of three-way asynchronous serial-port data, the present invention has adopted Driver studio software programming based on the driver of Windows operating system, use oscillograph to check that serial ports sends the level nature and the synchronization accuracy of data, test findings shows, every road serial ports is normal transceive data all, the synchronization accuracy error of three road serial ports reaches below the 100ns, and serial communication speed reaches 2Mbps.
Description of drawings
Fig. 1 is a composition structural drawing of the present invention;
Fig. 2 is the theory of constitution figure of FPGA control circuit of the present invention;
Fig. 3 is the cut-away view of being made up of isolation module, level shifting circuit and interface protective circuit;
Fig. 4 is the oscillogram of single channel rs 232 serial interface signal of the present invention.
Embodiment
The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:
As shown in Figure 1; a kind of three-way asynchronous serial-port data real-time synchronous transmitting system; comprise the CPCI interface chip; the FPGA control circuit; No. three buffer circuits; three level shifting circuits; three interface protective circuits; crystal oscillator; SDRAM; EEPROM; the configuration information of EEPROM storage CPCI interface chip; after powering on, reads the CPCI interface chip configuration information of EEPROM storage CPCI interface chip; the parallel port data that host computer will send write in the internal data buffer memory of FPGA control circuit by the CPCI interface chip; SDRAM stores the parallel data in the FPGA control circuit internal data buffer memory; the timer of host computer in the FPGA control circuit sends enable signal; timer picks up counting according to the clock frequency that crystal oscillator produces; parallel-to-serial converter among the timer control FPGA carries out the parallel data taking-up and go here and there to change to form three road TTL signals from SDRAM; when the timer timing then; three road TTL signals after timer control parallel-to-serial converter will be changed are sent to three buffer circuits isolates; carry out level conversion through the TTL signal after isolating, export with the serial ports form by interface protective circuit at last.
As shown in Figure 2, the FPGA control circuit comprises three timers, three parallel-to-serial converters, three write buffer area and three and read buffer area, the parallel data that is write by the CPCI interface chip writes three and writes in the buffer area, SDRAM stores three parallel datas that write in the buffer area, three timers receive the enable signal that host computer sends at the same time or separately, three clock frequency timing respectively that timer produces according to crystal oscillator after receiving enable signal, three parallel-to-serial converters are taken out to three with parallel data and read in the buffer area from SDRAM, three parallel-to-serial converters of three timer control carry out three parallel datas that read in the buffer area and go here and there to change forming three road TTL signals, when the timing of three timers then, three road TTL signal Synchronization or asynchronous output after three timer control parallel-to-serial converters will be changed.
As shown in Figure 3, buffer circuit adopts photoelectrical coupler to carry out the photoelectricity isolation; Level shifting circuit becomes the TTL conversion of signals rs 232 serial interface signal of difference; Interface protective circuit adopts four voltage stabilizing diodes to form, the positive pole butt joint of per two voltage stabilizing diodes, negative pole one end ground connection, another termination one tunnel difference rs 232 serial interface signal.
Between CPCI host computer and the CPCI interface chip with the parallel mode swap data, the CPCI interface chip constitutes bus interface circuit, transform signal sequence and address and data time-sharing multiplex signal that cpci bus provides, be convenient to rear end equipment and directly use, finish the data communication of FPGA and cpci bus.When serial data sent, the data that host computer will send write the FPGA inner buffer by the CPCI interface chip, can be by enabling to control 3 road synchronized transmissions.Can set baud rate, parity check bit and the position of rest of transmission.The TTL signal of FPGA output is isolated and level conversion through photoelectricity, exports with serial ports (as RS-422) form.
When serial data receives, the rs 232 serial interface signal of input is converted to the TTL signal through level transferring chip, isolates by photoelectricity, is responsible for receiving and handling by FPGA, use high capacity SDRAM that the data that receive are carried out buffer memory, host computer can read the data that receive by the CPCI interface chip.
Realize that by FPGA but it is the hardware timer that makes up a plurality of synchro control that the multi-channel serial port accurate timing sends key, if realize the synchronization accuracy of microsecond level, the frequency of FPGA crystal oscillator will be more than 1M, and the present invention has selected the 24M crystal oscillator for use, and theoretical synchronization accuracy can reach 42ns.The timing of hardware timer can carry out dynamic-configuration, realizes that 3 road serial ports synchronized transmissions need 3 hardware timers, enables the controller unification by 1 and controls, and has selected 3 25 bit timing devices here for use, and the transmitting time difference between its every road can reach 1.4s.
The communication standard that UART serial line interface EIA (EIA) formulates, serial line interface commonly used at present mainly contains RS-232, RS-422, RS-485 interface, the Physical layer electrical specification difference of distinct interface, but the data frame format of their link layer is identical, is check bit, 1～2 position of rest composition by 1 start bit (logical zero is represented), 5～8 bit data positions (low level is preceding), 1.Parallel data is the byte mode storage the preceding of an employing high position, and-string changes and string-also the implementation of conversion is similar, and just operating process is opposite.And the process of string conversion is: rolling counters forward begins, and parallel-to-serial converter detects three parallel data level that read in the buffer area, all occurs in data bit time middle part with the bits per inch that guarantees this frame according to detecting, and reduces to detect the bit error rate; Data shift: convert the parallel data little-endian to serial data by displacement mode, deposit in the temporary variable; Parity checking: parity checking is carried out in the setting of data based parity checking after the displacement, when the timer timing to data are sent.
Can realize high-speed cache by the mode of program construction FIFO in fpga chip, need take resource on a large amount of sheets but make up FIFO, that generally can not do is very big, can't realize jumbo high-speed cache.And SDRAM can realize the memory capacity of tens M even M up to a hundred, but its access speed is relatively slow, and the mode that this paper combines with SDRAM by FIFO in the sheet has realized the high-speed cache of multi-channel serial port.
SDRAM has the advantages that the space memory space is big, read or write speed is fast, price is relatively cheap.But its steering logic complexity needs periodic refresh operation, line management, different delayed time and command sequence etc.The memory address of SDRAM is divided into page or leaf (bank) address, row (row) address and row (column) address.For example the SDRAM of a 8MByte is divided into 4 bank, and promptly 1 bank is 2Mbyte, and each bank comprises 12 row, 8 row.A series of instructions of SDRAM are as shown in table 1, and each instruction finally all is to realize by control RAS, CAS, WE signal, common operating process such as table 1 to SDRAM.
Table 1SDRAM operational order
| Order | Abbreviation | RAS | CAS | WE |
| Blank operation | NOP | H | H | H |
| Page or leaf activates | ACT | L | H | H |
| Read operation | RD | H | L | H |
| Write operation | WR | H | L | L |
| Burst operation stops | BT | H | H | L |
| Precharge | PCH | L | H | L |
| Refresh | ARF | L | L | H |
| The configuration mode register | LMR | L | L | L |
The main operation that SDRAM is conducted interviews is exactly to read RD and write the WR operation.SDRAM must carry out page or leaf earlier and activate the ACT operation when carrying out read-write operation, opens to guarantee storage unit, so that therefrom read the address or write the address, closes storage unit and realizes by precharge PHC order.When carrying out write operation, inner column address and data will be deposited; When carrying out read operation, home address is deposited, and behind wait CAS time delay (being generally 1～3 clock period), the data of reading appear on the data bus, and concrete sequential sees the SDRAM databook for details, repeats no more herein.The present invention is for for simplicity, SDRAM is divided into the space of 3 regular lengths, store the data that 3 road serial ports receive respectively, FPGA internal build 3 tunnel writes FIFO and 3 tunnel and reads FIFO, and parallel data at first is kept at and writes among the FIFO, and FPGA detects input FIFO in each clock period, finding wherein has data just data to be transferred among the SDRAM, whether be full, discontented then the SDRAM data are transferred to read among the FIFO if detecting and read FIFO, the confession primary control program reads.
The CPCI interface card is selected the PCI9030 of PLX company for use, and this chip adopts the 3.3V core voltage, compatible 5V signal level, and low in energy consumption, flexible configuration is simple, is easy to finish the data communication of FPGA and cpci bus; FPGA selects the XC3S400PQ208-4I chip in the Spartan3 of the Xilinx company series for use, and this chip comprises the GATES of 400K, and the RAM of 344K and 141 available I/O pins can satisfy the functional requirement of system.
Full duplex serial ports level transferring chip is selected the MAX485 chip for use, and its highest communication speed is 10Mbps, has the esd protection characteristic of 2KV.The interface protection chip is selected the PSM712 of ProTek Devices company for use, and this chip is a RS-422/485 interface TVS array commonly used, can effectively protect interface chip.Rs 232 serial interface signal adopts photoelectricity to isolate, and selects the HCPL0631 of FAIRCHILD company for use, and this chip is the high-speed photoelectric coupler spare of 10Mbps, can satisfy the system speed demand.
The operating system of test is used Windows operating system, the driver of integrated circuit board that adopted Driver studio software programming, the mode of receiving and dispatching mutually with data between each road of serial port board self is tested the transmission and the receiving function of serial ports, uses oscillograph to check that serial ports sends the level nature and the synchronization accuracy of data.After tested, every road serial ports is normal transceive data all, and the synchronization accuracy error of three road serial ports reaches below the 100ns, can satisfy the synchronization accuracy demand of system, and the waveform of single channel serial ports as shown in Figure 4.
The present invention not detailed description is a technology as well known to those skilled in the art.
Claims (5)
1. three-way asynchronous serial-port data real-time synchronous transmitting system, it is characterized in that: comprise the CPCI interface chip, the FPGA control circuit, No. three buffer circuits, three level shifting circuits, three interface protective circuits, crystal oscillator, SDRAM, EEPROM, the configuration information of EEPROM storage CPCI interface chip, after powering on, reads the CPCI interface chip configuration information of EEPROM storage CPCI interface chip, the parallel data that host computer will send writes in the internal data buffer memory of FPGA control circuit by the CPCI interface chip, SDRAM stores the parallel data in the FPGA control circuit internal data buffer memory, the timer of host computer in the FPGA control circuit sends enable signal, timer picks up counting according to the clock frequency that crystal oscillator produces, parallel-to-serial converter in the timer control FPGA control circuit carries out the parallel data taking-up and go here and there to change to form three road TTL signals from SDRAM, when the timer timing then, three road TTL signals after timer control parallel-to-serial converter will be changed are sent to No. three buffer circuits isolates, carry out level conversion through the TTL signal after isolating, export with the serial ports form by interface protective circuit at last;
Described FPGA control circuit comprises three timers, three parallel-to-serial converters, three write buffer area and three and read buffer area, the parallel data that is write by the CPCI interface chip writes three and writes in the buffer area, SDRAM stores three parallel datas that write in the buffer area, three timers receive the enable signal that host computer sends at the same time or separately, three clock frequency timing respectively that timer produces according to crystal oscillator after receiving enable signal, three parallel-to-serial converters are taken out to three with parallel data and read in the buffer area from SDRAM, three parallel-to-serial converters of three timer control carry out three parallel datas that read in the buffer area and go here and there to change forming three road TTL signals, when the timing of three timers then, three road TTL signal Synchronization or asynchronous output after three timer control parallel-to-serial converters will be changed.
2. a kind of three-way asynchronous serial-port data real-time synchronous transmitting system according to claim 1 is characterized in that: described buffer circuit adopts photoelectrical coupler to carry out the photoelectricity isolation.
3. a kind of three-way asynchronous serial-port data real-time synchronous transmitting system according to claim 1 is characterized in that: described level shifting circuit becomes the TTL conversion of signals rs 232 serial interface signal of difference.
4. a kind of three-way asynchronous serial-port data real-time synchronous transmitting system according to claim 1; it is characterized in that: described interface protective circuit adopts four voltage stabilizing diodes to form; the positive pole butt joint of per two voltage stabilizing diodes, negative pole one end ground connection, another termination one tunnel difference rs 232 serial interface signal.
5. a kind of three-way asynchronous serial-port data real-time synchronous transmitting system according to claim 1 is characterized in that: described crystal oscillator is the 24M crystal oscillator.
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