CN112540942B - Multichannel synchronous serial communication circuit and method - Google Patents
Multichannel synchronous serial communication circuit and method Download PDFInfo
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- CN112540942B CN112540942B CN202011309712.3A CN202011309712A CN112540942B CN 112540942 B CN112540942 B CN 112540942B CN 202011309712 A CN202011309712 A CN 202011309712A CN 112540942 B CN112540942 B CN 112540942B
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
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Abstract
The invention discloses a multichannel synchronous serial communication circuit and a method, which belong to the field of digital interface communication and comprise a main control FPGA and modules 1 to n, wherein the modules 1 to n have the same composition form and mainly comprise an isolation circuit and a control FPGA. The invention has three working modes of JTAG debugging, JTAG program downloading and three-wire serial communication; the three working modes, the lead functions are multiplexed and do not interfere with each other; in the main control FPGA, an independent three-wire serial communication wire is adopted to communicate with each module so as to realize multichannel control; the full duplex data transmission can be realized by adopting three-wire serial communication, so as to improve the transmission efficiency; setting 64 clock cycles as 1 frame, and setting a frame synchronization signal; setting a format indication bit to ensure the integrity of the transmission data; and a handshake mechanism is adopted for data communication between the main control FPGA and the control FPGA so as to ensure the correctness of data transmission.
Description
Technical Field
The invention belongs to the field of digital interface communication, and particularly relates to a multichannel synchronous serial communication circuit and a multichannel synchronous serial communication method.
Background
In the modularized instrument, the design thought of a host and a module is adopted, and the data communication between the host and the module is generally not adopted, mainly because the parallel communication needs more leads, and when the number of the modules is more, the number of the data communication leads of the host is not enough. Therefore, in the modularized instrument, a serial communication mode is generally selected to complete the data communication between the host and the module.
In the serial communication scheme, common serial communication includes: i 2 C、SPI, RS232, etc., where I 2 The C bus has only two leads, but can only work in a single duplex working mode, so that the efficiency is low; SPI bus, in order to realize full duplex operation mode, four leads are needed; the baud rate of the RS232 bus is generally around 19200, which is slow. Thus, these several serial buses are difficult to meet in a modular instrument, where the host has fast control over multiple modules.
In the modularized program-controlled direct-current power supply, the design thought of a host and modules is adopted, on one hand, the host independently controls each power module, and the multichannel program-controlled direct-current power supply can be realized; in another aspect, a plurality of power modules are connected in parallel or in series, and each power module is synchronously controlled through a host computer so as to expand the output range of voltage, current and power and realize a high-power program-controlled direct-current power supply. In the design of the modularized program-controlled direct-current power supply, no matter what working mode, the host is required to realize the simultaneous control of a plurality of modules, and synchronously read the measurement data of the plurality of modules, including voltage, current, temperature and the like, so as to be used for voltage readback, current readback, overvoltage detection, overcurrent detection, overtemperature detection and the like. In the design of a power supply module, an FPGA is generally selected as a controller, and the module is required to have functions of FPGA program downloading, JTAG debugging and the like, so that the module FPGA program is convenient to upgrade and maintain, and the module FPGA program can be placed in a host, so that configuration chips of the module FPGA can be reduced, the product cost is reduced, and the product cost performance is improved.
Therefore, new serial communication methods need to be studied, and data transmission speeds are required to be faster; in order to improve the data transmission efficiency, a double-full-work working mode is needed; because the pin resources of the host controller are limited, in order to realize multi-module control, and the number of modules is easy to expand, fewer leads of serial communication are required; the program downloading function of the module FPGA is required to be realized through a serial communication line. Therefore, new multi-channel synchronous serial communication circuits and implementation methods need to be studied.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a multichannel synchronous serial communication circuit and a multichannel synchronous serial communication method, which are reasonable in design, overcome the defects in the prior art and have good effects.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a multichannel synchronous serial communication circuit comprises a master control FPGA and modules 1 to n;
the main control FPGA is configured to realize data communication with the module 1 through three-wire serial communication 1; data communication with the module 2 is realized through three-wire serial communication 2; realizing data communication with the module n through three-wire serial communication n;
the modules 1 to n have the same composition form and comprise an isolation circuit and a control FPGA;
an isolation circuit configured to effect electrical isolation between the master FPGA and the control FPGA;
the control FPGA is configured to be used for realizing data communication with the master control FPGA through the isolation circuit.
Preferably, the device has three working modes of JTAG debugging, JTAG program downloading and three-wire serial communication, and the lead functions of the three working modes are multiplexed and do not interfere with each other; in a JTAG debugging working mode, the on-line debugging function of the JTAG simulator on the control FPGA can be realized; in a JTAG program downloading working mode, the program downloading function of the main control FPGA to the control FPGA can be realized; in the three-wire serial communication working mode, the data communication function between the main control FPGA and the control FPGA can be realized.
Preferably, the three-wire serial communication realizes full duplex data transmission through three communication wires of a clock wire, a data transmission wire and a data receiving wire.
Preferably, in the three-wire serial communication operation mode, a frame structure operation mode is adopted, 64 clock periods are 1 frame, and the frame is provided with a synchronous signal.
Preferably, a handshake mechanism is adopted for data communication between the main control FPGA and the control FPGA, so that the accuracy of data transmission is ensured.
Preferably, when the data communication is performed between the main control FPGA and the control FPGA, data is sent at the rising edge of the clock line, and the data is received at the falling edge of the clock line, so that the synchronism of data transmission is ensured.
Preferably, when data communication is performed between the main control FPGA and the control FPGA, format indication bits are set on the transmitted data, so that the type of the transmitted data is improved, and the integrity of the transmitted data is ensured.
In addition, the invention also relates to a multichannel synchronous serial communication realization method, which adopts the multichannel synchronous serial communication circuit, and specifically comprises the following steps:
step 1: executing the initialization related operations of the master control FPGA and the control FPGA;
step 2: the master control FPGA sends a frame communication starting signal, sets a high-level signal which is generated for 100 clock cycles on a data sending line M_TX, and sets the data sending line M_TX as a low-level signal;
step 3: controlling an FPGA to detect a frame communication starting signal;
if: detecting a high-level signal with a clock period greater than or equal to 100 on the data receiving line S_RX, generating a falling edge, starting frame communication, and executing step 4;
otherwise, not considering the frame communication to start, and continuing to execute the step 3;
step 4: the FPGA is controlled to send data with handshake information on a data sending line S_TX, and the handshake information is set to X 'A5';
step 5: the master control FPGA detects the M_RX upper handshake information of the data receiving line;
if: if the handshake information is detected to be equal to X 'A5' on the data receiving line M_RX, executing step 6;
or if the handshake information is detected to be not equal to X 'A5', returning to the step 2;
step 6: the master control FPGA sends data with handshake information on a data sending line M_TX, wherein the handshake information is set as X '5A';
step 7: controlling the FPGA to detect the S_RX upper handshake information of the data receiving line;
if: step 8 is executed if the handshake information is detected to be equal to X "5A" on the data receiving line s_rx;
or if the handshake information is detected to be not equal to X '5A', returning to the step 2;
step 8: frame communication starts.
Preferably, in the data communication design of the master control FPGA, the sending data is in an address+data+handshake format; determining a received data format according to the format indicator bit, and when the format indicator bit is low, determining the received data format according to a 'measured value + state value + handshake' format; when the format indicator bit is high, the received data format is in the format of 'address + data + handshake', which comprises the following steps:
step 1: performing an initialization related operation;
step 2: performing frame start occurrence and detection operations;
step 3: generating a frame synchronization signal;
step 4: simultaneously executing data sending and data receiving operations;
step 4.1: executing a data sending operation;
step 4.1.1: setting format information, occupying 1bit, fixedly setting high level, and using low level as later expansion;
step 4.1.2: setting address information, accounting for 20 bits;
step 4.1.3: setting data information, wherein the data information occupies 16 bits;
step 4.1.4: setting read-write information, which occupies 1bit;
step 4.1.5: setting reserved 1 information, accounting for 15 bits, and fixedly setting the reserved 1 information to be low level for later expansion use;
step 4.1.6: setting handshake information, accounting for 8 bits, and fixedly setting X '5A';
step 4.1.7: setting reserved 2 information which occupies 3 bits, fixedly setting the reserved 2 information to be low level for later expansion use, and executing the step 5;
step 4.2: executing data receiving operation, judging the format bit level, and occupying 1bit;
if: if the result is that the format bit is low level, executing step 4.2.1;
or if the result is that the format bit is high level, executing step 4.2.5;
step 4.2.1: detecting remote voltage information, wherein the remote voltage information occupies 12 bits;
step 4.2.2: detecting local voltage information, wherein the local voltage information occupies 12 bits;
step 4.2.3: detecting current information, wherein the current information occupies 12 bits;
step 4.2.4: detecting state information, accounting for 16 bits, and executing the step 4.2.8;
step 4.2.5: detecting address information, accounting for 8 bits;
step 4.2.6: detecting data information, wherein the data information occupies 8 bits;
step 4.2.7: detecting reserved 1 information, accounting for 36 bits, fixing to be low level, and executing the step 4.2.8;
step 4.2.8: detecting and judging handshake information, wherein the handshake information occupies 8 bits;
if: if the handshake information is equal to X "A5", step 4.2.9 is executed;
or if the handshake information is not equal to X 'A5', executing the step 2;
step 4.2.9: detecting indication information, wherein the indication information occupies 1bit;
step 4.2.10: detecting and reserving 2 information, occupying 2 bits, fixing to be low level, and executing the step 5;
step 5: and (3) ending the three-wire synchronous serial communication 1 frame, returning to the step (3), and executing the next 1 frame.
Preferably, in the control FPGA data communication design, the transmission data format is determined according to the format indicator bit, and when the format indicator bit is low, the transmission data format is in accordance with the format of "measurement value+state value+handshake"; when the format indicator bit is high, the transmitted data format is in an 'address + data + handshake' format; the received data is in the format of address + data + handshake, which comprises the following steps:
step 1: performing an initialization related operation;
step 2: performing a frame start detection operation;
step 3: generating a frame synchronization signal;
step 4: simultaneously executing data sending and data receiving operations;
step 4.1: performing a data transmission operation, and judging a measurement data enabling signal;
if: if the judgment result is that the measurement data enabling signal is at a high level, executing the step 4.1.1;
or if the measurement data enable signal is at low level, executing step 4.1.6;
step 4.1.1: setting format bit as low level, accounting for 1bit;
step 4.1.2: setting far-end voltage information, which occupies 12 bits;
step 4.1.3: setting local voltage information, which occupies 12 bits;
step 4.1.4: setting current information, which is 12 bits;
step 4.1.5: setting state information, accounting for 16 bits, and executing the step 4.1.10;
step 4.1.6: setting format bit as high level, accounting for 1bit;
step 4.1.7: setting address information, accounting for 8 bits;
step 4.1.8: setting data information, accounting for 8 bits;
step 4.1.9: setting reserved 1 information, fixedly setting the reserved 1 information to be low level, occupying 36 bits for later expansion use, and executing the step 4.1.10;
step 4.1.10: setting handshake information, accounting for 8 bits, and fixedly setting X 'A5';
step 4.1.11: setting indication information, accounting for 1bit;
step 4.1.12: setting reserved 2 information, fixedly setting the reserved 2 information to be low level, occupying 2 bits for later expansion use, and executing the step 5;
step 4.2: performing a receive data operation;
step 4.2.1: detecting format information, occupying 1bit, and fixing the format information as high level;
step 4.2.2: detecting address information, wherein the address information occupies 20 bits;
step 4.2.3: detecting data information, wherein the data information occupies 16 bits;
step 4.2.4: detecting read-write information, wherein the read-write information occupies 1bit;
step 4.2.5: detecting reserved 1 information, accounting for 15 bits, and fixing the reserved 1 information as a low level;
step 4.2.6: detecting and judging handshake information, wherein the handshake information occupies 8 bits;
if: if the handshake information is equal to X "5A", step 4.2.7 is executed;
or if the handshake information is not equal to X '5A', executing the step 2;
step 4.2.7: detecting and reserving 2 information, occupying 3 bits, fixing to be low level, and executing the step 5;
step 5: and (3) ending the three-wire synchronous serial communication 1 frame, returning to the step (3), and executing the next 1 frame.
The principle of the invention is as follows:
the multichannel synchronous serial communication circuit mainly comprises a main control FPGA and modules 1 to n, wherein the modules 1 to n have the same composition form and mainly comprise an isolation circuit and a control FPGA. And the isolation circuit is adopted to realize signal isolation between the main control FPGA and the control FPGA, so that the safety is improved.
The invention has three working modes of JTAG debugging, JTAG program downloading and three-wire serial communication; the three working modes are that the lead functions are multiplexed and do not interfere with each other.
In JTAG debugging working mode, JTAG simulator can be used to complete on-line debugging function of module control FPGA, the working mode is simple in design, JTAG port of FPGA is controlled, and besides power and ground signals, four signals of TCK, TDI, TDO and TMS are mainly included. In the circuit design, the JTAG port signal line, JTAG program downloading working mode and three-wire serial communication working mode of the FPGA are required to be controlled, the functions can be multiplexed, communication conflict can not be generated, and the communication reliability is ensured. JTAG debug mode of operation is typically only used during JTAG debug, and is not used during normal operation.
In a JTAG program downloading working mode, after each time of starting up, a three-wire serial communication lead of the main control FPGA passes through an isolation circuit to a JTAG port of the control FPGA, so that the automatic program downloading function of the control FPGA is completed. In this mode of operation, because there are four wires controlling the JTAG port of the FPGA, and three wires are only used for three-wire serial communication, it is necessary to implement the function of four wires of JTAG port with three communication wires. A D trigger with a preset function and an inverter are designed, TDI data and TMS data are simultaneously transmitted by using a data transmission line TX, and the pin functions are multiplexed, so that the function of downloading four lines by using three serial communication lines to realize JTAG port programs is achieved.
In the three-wire serial communication working mode, functions are multiplexed and independent on the basis of a JTAG program downloading working mode. The master control FPGA sends a clock line M_CLK to a clock line S_CLK of the control FPGA through the isolation circuit; the data transmitting line M_TX of the main control FPGA is transmitted to the data receiving line S_RX of the control FPGA through the isolating circuit; the data transmitting line S_TX of the control FPGA is transmitted to the data receiving line M_RX of the master control FPGA through the isolating circuit, so that the hardware design of three-wire serial communication is realized. In the design, a frame structure mode is adopted, the clock line frequency is 12.5MHz, 64 clock cycles are used as 1 frame, full duplex data transmission can be realized between a master control FPGA and a control FPGA, and a frame synchronizing signal is set. In the master control FPGA and the control FPGA, data is sent at the rising edge of a clock line, and the data is received at the falling edge of the clock line, so that the synchronism of data transmission is ensured. Each frame contains a large amount of data and format indicator bits are set to ensure the integrity of the transmitted data.
The three-wire serial communication has only a clock wire, a data transmitting wire and a data receiving wire, and can complete the generation and detection functions of the beginning of the frame communication without using a chip selection enabling signal. The main control FPGA initiates a frame start communication signal, and after a high-level signal with 100 clock cycles is generated on a data transmission line, a low-level signal is transmitted, when a data receiving line of the control FPGA detects more than or equal to 100 high-level signals, and when a falling edge occurs, the frame communication is detected to start.
The three-wire serial communication working mode adopted by the invention can realize the read-write control of one module by only three communication wires. In the design of the main control FPGA, independent three-wire serial communication is adopted for each module, so that synchronous control of multiple modules can be realized by one host computer, the working efficiency is improved, and the number of modules is easy to expand.
The invention has the beneficial technical effects that:
compared with the prior art, the invention adopts the isolation circuit to realize signal isolation of the main control FPGA and the control FPGA, thereby improving the safety; the device has three working modes of JTAG debugging, JTAG program downloading and three-wire serial communication; the three working modes, the lead functions are multiplexed and do not interfere with each other; in the main control FPGA, an independent three-wire serial communication line is adopted to communicate with each module, so that multichannel control is realized; the full duplex data transmission can be realized by adopting three-wire serial communication, so as to improve the transmission efficiency; setting 64 clock cycles as 1 frame, each frame containing a large amount of data, and setting a frame synchronization signal; because of the three-wire serial communication mode, no enabling signal is generated, a starting signal is sent by the main control FPGA, and the starting signal is detected by the control FPGA; in the master control FPGA and the control FPGA, data is sent at the rising edge of a clock line, and the data is received at the falling edge of the clock line, so that the synchronism of data transmission is ensured; setting a format indication bit to ensure the integrity of the transmission data; the data communication between the main control FPGA and the control FPGA adopts a handshake mechanism to ensure the correctness of data transmission; all the modules are realized in the FPGA, so that the speed is high and the portability is high.
Drawings
FIG. 1 is a block diagram of a multi-module serial communication circuit.
Fig. 2 is a schematic block diagram of a circuit for three modes of operation.
Fig. 3 is a schematic diagram of a three-wire serial communication implementation JTAG port lead multiplexing.
Fig. 4 is a three-wire serial communication frame structure diagram.
Fig. 5 is a frame communication start diagram.
Fig. 6 is a flow chart of a frame communication initiation and detection scheme.
Fig. 7 is a master FPGA three-wire synchronous serial communication protocol.
Fig. 8 is a flow chart of a master FPGA three-wire synchronous serial communication design.
Fig. 9 is a control FPGA three-wire synchronous serial communication protocol.
Fig. 10 is a flow chart of a control FPGA three-wire synchronous serial communication design.
Detailed Description
The invention is described in further detail below with reference to the attached drawings and detailed description:
example 1:
as shown in FIG. 1, the multichannel synchronous serial communication circuit comprises a master control FPGA and modules 1 to n. The main control FPGA can realize data communication with the module 1 through three-wire serial communication 1; data communication with the module 2 is realized through three-wire serial communication 2; and through three-wire serial communication n, data communication with the module n is realized, namely, the master control FPGA can simultaneously perform data communication with a plurality of modules. The modules 1 to n have the same composition form and mainly comprise an isolation circuit and a control FPGA, and the isolation circuit mainly realizes electric isolation between the main control FPGA and the control FPGA; and the control FPGA can realize data communication with the main control FPGA through the isolation circuit.
The three-wire serial communication can realize the read-write control of one module only by three communication wires, namely a clock wire, a data transmitting wire and a data receiving wire. In the design of the main control FPGA, independent three-wire serial communication is adopted for each module, so that synchronous control of multiple modules can be realized by one host computer, the working efficiency is improved, and the number of modules is easy to expand.
Example 2:
as shown in FIG. 2, the multichannel synchronous serial communication circuit provided by the invention has three working modes of JTAG debugging, JTAG program downloading and three-wire serial communication, and the lead functions of the three working modes are multiplexed and do not interfere with each other.
In JTAG debugging working mode, JTAG simulator can be used to complete on-line debugging function of module control FPGA, the working mode is simple in design, JTAG port of FPGA is controlled, and besides power and ground signals, four signals of TCK, TDI, TDO and TMS are mainly included. In the circuit design, the JTAG port signal line, JTAG program downloading working mode and three-wire serial communication working mode of the FPGA are required to be controlled, the functions can be multiplexed, communication conflict can not be generated, and the communication reliability is ensured. JTAG debug mode of operation is typically only used during JTAG debug, and is not used during normal operation.
In a JTAG program downloading working mode, after each time of starting up, a three-wire serial communication lead of the main control FPGA passes through an isolation circuit to a JTAG port of the control FPGA, so that the automatic program downloading function of the control FPGA is completed. In this mode of operation, because there are four wires controlling the JTAG port of the FPGA, and three wires are only used for three-wire serial communication, it is necessary to implement the function of four wires of JTAG port with three communication wires. As shown in fig. 3, a D flip-flop with a preset function and an inverter are designed, TDI data and TMS data are simultaneously transmitted by using a data transmission line TX, and the pin functions are multiplexed, so that the function of downloading four lines by using three serial communication lines to realize JTAG port programs is achieved.
In three working modes of three-wire serial communication, functions are multiplexed and independent on the basis of a JTAG program downloading working mode. The master control FPGA sends a clock line M_CLK to a clock line S_CLK of the control FPGA through the isolation circuit; the data transmitting line M_TX of the main control FPGA is transmitted to the data receiving line S_RX of the control FPGA through the isolating circuit; the data transmitting line S_TX of the control FPGA is transmitted to the data receiving line M_RX of the master control FPGA through the isolating circuit, so that the hardware design of three-wire serial communication is realized. As shown in fig. 4, in the design, a frame structure mode is adopted, the clock line frequency is 12.5MHz, 64 clock cycles are used as 1 frame, full duplex data transmission can be realized between the master control FPGA and the control FPGA, and a frame synchronizing signal is set. In the master control FPGA and the control FPGA, data is sent at the rising edge of a clock line, and the data is received at the falling edge of the clock line, so that the synchronism of data transmission is ensured. Each frame contains a large amount of data and format indicator bits are set to ensure the integrity of the transmitted data.
Example 3:
on the basis of the embodiment 2, the invention also provides a multichannel synchronous serial communication method, wherein the three-wire serial communication can complete the generation and detection functions of the frame communication start only by a clock wire, a data transmission wire and a data receiving wire without using a chip selection enabling signal.
As shown in fig. 5, a main control FPGA initiates a frame communication start signal, sets a high level signal with 100 clock cycles on a data transmission line m_tx, then sends a low level signal, and when a data reception line s_rx of a control FPGA detects more than or equal to 100 high level signals, when a falling edge occurs, starts communication; the control FPGA sends data with handshake signals through a data sending line S_TX, after detecting corresponding handshake signals on a data receiving line M_RX of the main control FPGA, the main control FPGA sends data with handshake signals on the data sending line M_TX again, after detecting corresponding handshake signals again, the control FPGA indicates that the handshake between the main control FPGA and the control FPGA is successful, namely the generation and detection functions of frame communication start are completed, and then three-wire serial communication starts to work normally.
In the design process of the main control FPGA and the control FPGA, the frame communication starts to occur and the design flow is detected as shown in fig. 6, and the specific steps are as follows:
step 1: executing the initialization related operations of the master control FPGA and the control FPGA;
step 2: the master control FPGA sends a frame communication starting signal, sets a high-level signal which is generated for 100 clock cycles on a data sending line M_TX, and sets the data sending line M_TX as a low-level signal;
step 3: controlling an FPGA to detect a frame communication starting signal;
if: detecting a high-level signal with a clock period greater than or equal to 100 on the data receiving line S_RX, generating a falling edge, starting frame communication, and executing step 4;
otherwise, not considering the frame communication to start, and continuing to execute the step 3;
step 4: the FPGA is controlled to send data with handshake information on a data sending line S_TX, and the handshake information is set to X 'A5';
step 5: the master control FPGA detects the M_RX upper handshake information of the data receiving line;
if: if the handshake information is detected to be equal to X 'A5' on the data receiving line M_RX, executing step 6;
or if the handshake information is detected to be not equal to X 'A5', returning to the step 2;
step 6: the master control FPGA sends data with handshake information on a data sending line M_TX, wherein the handshake information is set as X '5A';
step 7: controlling the FPGA to detect the S_RX upper handshake information of the data receiving line;
if: step 8 is executed if the handshake information is detected to be equal to X "5A" on the data receiving line s_rx;
or if the handshake information is detected to be not equal to X '5A', returning to the step 2;
step 8: frame communication starts.
Example 4:
on the basis of the above embodiment 3, the multi-channel synchronous serial communication method provided by the invention requires that one master control FPGA can communicate with a plurality of control FPGAs at the same time, so as to realize the multi-channel control function.
As shown in fig. 7, in the data communication design between the master FPGA and the control FPGA, a handshake mechanism is adopted in the master FPGA three-wire serial synchronous communication protocol, so that the accuracy of data transmission can be ensured. In order to ensure the decoding accuracy of each data bit, the handshake signals sent by the master control FPGA occupy 8 bits and are set as X '5A'.
In the design of the master control FPGA, data is sent at the rising edge of a clock line, and received at the falling edge of the clock line, so that the synchronism of data transmission is ensured, synchronous serial communication is realized, and format indication bits are set, so that the type of the transmitted data is improved, and the integrity of the transmitted data is ensured. In the data format, a reserved bit is set, so that the expansion of the three-wire serial communication function in the later stage can be met.
In the main control FPGA design, the transmitted data is in a format of 'indication+address+data+read/write+reserved 1+handshake+reserved 2'. Wherein, the format indication occupies 1bit and is fixed to be high level; address 20 bits, data 16 bits, read/write 1bit, reserved 1 15 bits, handshake 8 bits, reserved 23 bits, and a total of 64 bits.
In the design of a master control FPGA, a received data format is determined according to a format indication bit, when format indication 1 is low, the received data is in a format of 'indication 1+ far-end voltage + local voltage + current + state + handshake + indication 2+ reservation', wherein the format indication 1 occupies 1bit, the far-end voltage occupies 12 bits, the local voltage occupies 12 bits, the current occupies 12 bits, the state occupies 16 bits, handshake occupies 8 bits, indication 2 occupies 1bit, reservation occupies 2 bits, and the total number of 64 bits; when the format indication 1 is high, the received data is in a format of 'indicated 1+address+data+reserved 1+handshake+indicated 2+reserved 2', wherein the format indication 1 occupies 1bit, the address occupies 8 bits, the data occupies 8 bits, the reserved 1 occupies 36 bits, the handshake occupies 8 bits, the indication 2 occupies 1bit, the reserved 2 occupies 2 bits, and the total is 64 bits.
In the design process of the master control FPGA, the design flow is shown in fig. 8, and the method specifically comprises the following steps:
step 1: performing an initialization related operation;
step 2: performing frame start occurrence and detection operations;
step 3: generating a frame synchronization signal;
step 4: simultaneously executing data sending and data receiving operations;
step 4.1: executing a data sending operation;
step 4.1.1: setting format information, occupying 1bit, fixedly setting high level, and enabling low level to be used as later expansion;
step 4.1.2: setting address information, accounting for 20 bits;
step 4.1.3: setting data information, wherein the data information occupies 16 bits;
step 4.1.4: setting read-write information, which occupies 1bit;
step 4.1.5: setting reserved 1 information, accounting for 15 bits, and fixedly setting the reserved 1 information to be low level, so that the reserved 1 information can be used as later expansion;
step 4.1.6: setting handshake information, accounting for 8 bits, and fixedly setting X '5A';
step 4.1.7: setting reserved 2 information which occupies 3 bits, and fixedly setting the reserved 2 information as low level which can be used as later expansion use, and executing the step 5;
step 4.2: executing data receiving operation, judging the format bit level, and occupying 1bit;
if: if the result is that the format bit is low level, executing step 4.2.1;
or if the result is that the format bit is high level, executing step 4.2.5;
step 4.2.1: detecting remote voltage information, wherein the remote voltage information occupies 12 bits;
step 4.2.2: detecting local voltage information, wherein the local voltage information occupies 12 bits;
step 4.2.3: detecting current information, wherein the current information occupies 12 bits;
step 4.2.4: detecting state information, accounting for 16 bits, and executing the step 4.2.8;
step 4.2.5: detecting address information, accounting for 8 bits;
step 4.2.6: detecting data information, wherein the data information occupies 8 bits;
step 4.2.7: detecting reserved 1 information, accounting for 36 bits, fixing to be low level, and executing the step 4.2.8;
step 4.2.8: detecting and judging handshake information, wherein the handshake information occupies 8 bits;
if: if the handshake information is equal to X "A5", step 4.2.9 is executed;
or if the handshake information is not equal to X 'A5', executing the step 2;
step 4.2.9: detecting indication information, wherein the indication information occupies 1bit;
step 4.2.10: detecting and reserving 2 information, occupying 2 bits, fixing to be low level, and executing the step 5;
step 5: and (3) ending the three-wire synchronous serial communication 1 frame, returning to the step (3), and executing the next 1 frame.
Example 5:
on the basis of the above embodiment 3, the multi-channel synchronous serial communication method provided by the invention requires that a plurality of control FPGAs can communicate with a master control FPGA at the same time, so as to realize the multi-channel control function.
As shown in fig. 9, in the data communication design between the control FPGA and the master FPGA, a handshake mechanism is used to ensure the correctness of data transmission. In order to ensure the decoding accuracy of each data bit, the handshake signals sent by the control FPGA occupy 8 bits and are set as X 'A5'.
In the control FPGA design, data is sent at the rising edge of a clock line, and received at the falling edge of the clock line, so that the synchronism of data transmission is ensured, synchronous serial communication is realized, and format indication bits are set, so that the type of the transmitted data is improved, and the integrity of the transmitted data is ensured. In the data format, a reserved bit is set, so that the expansion of the three-wire serial communication function in the later stage can be met.
In the control FPGA design, a transmission data format is determined according to a format indication bit, when the format indication 1 is low, the transmission data is in a format of 'indication 1+ far-end voltage + local voltage + current + state + handshake + indication 2+ reservation', wherein the format indication 1 occupies 1bit, the far-end voltage occupies 12 bits, the local voltage occupies 12 bits, the current occupies 12 bits, the state occupies 16 bits, handshake occupies 8 bits, indication 2 occupies 1bit, reservation occupies 2 bits, and the total number of 64 bits; when the format indication 1 is high, the transmitted data is in a format of 'indicated 1+address+data+reserved 1+handshake+indicated 2+reserved 2', wherein the format indication 1 occupies 1bit, the address occupies 8 bits, the data occupies 8 bits, the reserved 1 occupies 36 bits, the handshake occupies 8 bits, the indication 2 occupies 1bit, the reserved 2 occupies 2 bits, and the total is 64 bits.
In the control FPGA design, the received data is in the format of "indication+address+data+read/write+hold 1+handshake+hold 2". Wherein, the format indication occupies 1bit and is fixed to be high level; address 20 bits, data 16 bits, read/write 1bit, reserved 1 15 bits, handshake 8 bits, reserved 23 bits, and a total of 64 bits.
In the process of controlling the design of the FPGA, the design flow is shown in fig. 10, and specifically comprises the following steps:
step 1: performing an initialization related operation;
step 2: performing a frame start detection operation;
step 3: generating a frame synchronization signal;
step 4: simultaneously executing data sending and data receiving operations;
step 4.1: performing a data transmission operation, and judging a measurement data enabling signal;
if: if the judgment result is that the measurement data enabling signal is at a high level, executing the step 4.1.1;
or if the measurement data enable signal is at low level, executing step 4.1.6;
step 4.1.1: setting format bit as low level, accounting for 1bit;
step 4.1.2: setting far-end voltage information, which occupies 12 bits;
step 4.1.3: setting local voltage information, which occupies 12 bits;
step 4.1.4: setting current information, which is 12 bits;
step 4.1.5: setting state information, accounting for 16 bits, and executing the step 4.1.10;
step 4.1.6: setting format bit as high level, accounting for 1bit;
step 4.1.7: setting address information, accounting for 8 bits;
step 4.1.8: setting data information, accounting for 8 bits;
step 4.1.9: setting reserved 1 information, fixedly setting the reserved 1 information to be low level, occupying 36 bits, and executing the step 4.1.10, wherein the reserved 1 information can be used as later expansion;
step 4.1.10: setting handshake information, accounting for 8 bits, and fixedly setting X 'A5';
step 4.1.11: setting indication information, accounting for 1bit;
step 4.1.12: setting reserved 2 information, fixedly setting the reserved 2 information to be low level, occupying 2 bits, and executing the step 5, wherein the reserved 2 information can be used as later expansion use;
step 4.2: performing a receive data operation;
step 4.2.1: detecting format information, occupying 1bit, and fixing the format information as high level;
step 4.2.2: detecting address information, wherein the address information occupies 20 bits;
step 4.2.3: detecting data information, wherein the data information occupies 16 bits;
step 4.2.4: detecting read-write information, wherein the read-write information occupies 1bit;
step 4.2.5: detecting reserved 1 information, accounting for 15 bits, and fixing the reserved 1 information as a low level;
step 4.2.6: detecting and judging handshake information, wherein the handshake information occupies 8 bits;
if: if the handshake information is equal to X "5A", step 4.2.7 is executed;
or if the handshake information is not equal to X '5A', executing the step 2;
step 4.2.7: detecting and reserving 2 information, occupying 3 bits, fixing to be low level, and executing the step 5;
step 5: and (3) ending the three-wire synchronous serial communication 1 frame, returning to the step (3), and executing the next 1 frame.
The invention relates to a multichannel synchronous serial communication circuit and a method, comprising a main control FPGA and modules 1-n, wherein the modules 1-n have the same composition form and mainly comprise an isolation circuit and a control FPGA, the program downloading of the control FPGA and the data communication between the main control FPGA and the control FPGA are completed, the data communication between the main control FPGA and the control FPGA adopts a three-wire serial communication mode, and the data communication between the main control FPGA and the control FPGA comprises three communication wires, namely a clock wire, a data transmission wire and a data receiving wire, and adopts the isolation circuit to carry out signal isolation, thereby improving the safety. The invention has three working modes of JTAG debugging, JTAG program downloading and three-wire serial communication; the three working modes, the lead functions are multiplexed and do not interfere with each other; in the main control FPGA, an independent three-wire serial communication line is adopted to communicate with each module, so that multichannel control is realized; the full duplex data transmission can be realized by adopting three-wire serial communication, so as to improve the transmission efficiency; setting 64 clock cycles as 1 frame, each frame containing a large amount of data, and setting a frame synchronization signal; because of the three-wire serial communication mode, no enabling signal is generated, a starting signal is sent by the main control FPGA, and the starting signal is detected by the control FPGA; in the master control FPGA and the control FPGA, data is sent at the rising edge of a clock line, and the data is received at the falling edge of the clock line, so that the synchronism of data transmission is ensured; setting a format indication bit to ensure the integrity of the transmission data; the data communication between the main control FPGA and the control FPGA adopts a handshake mechanism to ensure the correctness of data transmission; all the modules are realized in the FPGA, so that the speed is high and the portability is high.
It should be understood that the above description is not intended to limit the invention to the particular embodiments disclosed, but to limit the invention to the particular embodiments disclosed, and that the invention is not limited to the particular embodiments disclosed, but is intended to cover modifications, adaptations, additions and alternatives falling within the spirit and scope of the invention.
Claims (3)
1. A method for realizing multichannel synchronous serial communication is characterized in that: a multichannel synchronous serial communication circuit is adopted, and the circuit comprises a master control FPGA and modules 1 to n;
the main control FPGA is configured to realize data communication with the module 1 through three-wire serial communication 1; data communication with the module 2 is realized through three-wire serial communication 2; realizing data communication with the module n through three-wire serial communication n;
the modules 1 to n have the same composition form and comprise an isolation circuit and a control FPGA;
an isolation circuit configured to effect electrical isolation between the master FPGA and the control FPGA;
the control FPGA is configured to be used for realizing data communication with the master control FPGA through the isolation circuit;
the device has three working modes of JTAG debugging, JTAG program downloading and three-wire serial communication, and the lead functions of the three working modes are multiplexed and do not interfere with each other; in a JTAG debugging working mode, the on-line debugging function of the JTAG simulator on the control FPGA can be realized; in a JTAG program downloading working mode, the program downloading function of the main control FPGA to the control FPGA can be realized; in a three-wire serial communication working mode, the data communication function between the main control FPGA and the control FPGA can be realized;
the three-wire serial communication realizes full duplex data transmission through three communication wires, namely a clock wire, a data transmission wire and a data receiving wire;
the method specifically comprises the following steps:
step 1: executing the initialization related operations of the master control FPGA and the control FPGA;
step 2: the master control FPGA sends a frame communication starting signal, sets a high-level signal which is generated for 100 clock cycles on a data sending line M_TX, and sets the data sending line M_TX as a low-level signal;
step 3: controlling an FPGA to detect a frame communication starting signal;
if: detecting a high-level signal with a clock period greater than or equal to 100 on the data receiving line S_RX, generating a falling edge, starting frame communication, and executing step 4;
otherwise, not considering the frame communication to start, and continuing to execute the step 3;
step 4: the FPGA is controlled to send data with handshake information on a data sending line S_TX, and the handshake information is set to X 'A5';
step 5: the master control FPGA detects the M_RX upper handshake information of the data receiving line;
if: if the handshake information is detected to be equal to X 'A5' on the data receiving line M_RX, executing step 6;
or if the handshake information is detected to be not equal to X 'A5', returning to the step 2;
step 6: the master control FPGA sends data with handshake information on a data sending line M_TX, wherein the handshake information is set as X '5A';
step 7: controlling the FPGA to detect the S_RX upper handshake information of the data receiving line;
if: step 8 is executed if the handshake information is detected to be equal to X "5A" on the data receiving line s_rx;
or if the handshake information is detected to be not equal to X '5A', returning to the step 2;
step 8: frame communication starts.
2. The multi-channel synchronous serial communication method according to claim 1, wherein: in the data communication design of the main control FPGA, sending data according to an address + data + handshake format; determining a received data format according to the format indicator bit, and when the format indicator bit is low, determining the received data format according to a 'measured value + state value + handshake' format; when the format indicator bit is high, the received data format is in the format of 'address + data + handshake', which comprises the following steps:
step 1: performing an initialization related operation;
step 2: performing frame start occurrence and detection operations;
step 3: generating a frame synchronization signal;
step 4: simultaneously executing data sending and data receiving operations;
step 4.1: executing a data sending operation;
step 4.1.1: setting format information, occupying 1bit, fixedly setting high level, and using low level as later expansion;
step 4.1.2: setting address information, accounting for 20 bits;
step 4.1.3: setting data information, wherein the data information occupies 16 bits;
step 4.1.4: setting read-write information, which occupies 1bit;
step 4.1.5: setting reserved 1 information, accounting for 15 bits, and fixedly setting the reserved 1 information to be low level for later expansion use;
step 4.1.6: setting handshake information, accounting for 8 bits, and fixedly setting X '5A';
step 4.1.7: setting reserved 2 information which occupies 3 bits, fixedly setting the reserved 2 information to be low level for later expansion use, and executing the step 5;
step 4.2: executing data receiving operation, judging the format bit level, and occupying 1bit;
if: if the result is that the format bit is low level, executing step 4.2.1;
or if the result is that the format bit is high level, executing step 4.2.5;
step 4.2.1: detecting remote voltage information, wherein the remote voltage information occupies 12 bits;
step 4.2.2: detecting local voltage information, wherein the local voltage information occupies 12 bits;
step 4.2.3: detecting current information, wherein the current information occupies 12 bits;
step 4.2.4: detecting state information, accounting for 16 bits, and executing the step 4.2.8;
step 4.2.5: detecting address information, accounting for 8 bits;
step 4.2.6: detecting data information, wherein the data information occupies 8 bits;
step 4.2.7: detecting reserved 1 information, accounting for 36 bits, fixing to be low level, and executing the step 4.2.8;
step 4.2.8: detecting and judging handshake information, wherein the handshake information occupies 8 bits;
if: if the handshake information is equal to X "A5", step 4.2.9 is executed;
or if the handshake information is not equal to X 'A5', executing the step 2;
step 4.2.9: detecting indication information, wherein the indication information occupies 1bit;
step 4.2.10: detecting and reserving 2 information, occupying 2 bits, fixing to be low level, and executing the step 5;
step 5: and (3) ending the three-wire synchronous serial communication 1 frame, returning to the step (3), and executing the next 1 frame.
3. The multi-channel synchronous serial communication method according to claim 1, wherein: in the control FPGA data communication design, determining a transmission data format according to a format indication bit, and when the format indication bit is low, the transmission data format is in a format of 'measured value + state value + handshake'; when the format indicator bit is high, the transmitted data format is in an 'address + data + handshake' format; the received data is in the format of address + data + handshake, which comprises the following steps:
step 1: performing an initialization related operation;
step 2: performing a frame start detection operation;
step 3: generating a frame synchronization signal;
step 4: simultaneously executing data sending and data receiving operations;
step 4.1: performing a data transmission operation, and judging a measurement data enabling signal;
if: if the judgment result is that the measurement data enabling signal is at a high level, executing the step 4.1.1;
or if the measurement data enable signal is at low level, executing step 4.1.6;
step 4.1.1: setting format bit as low level, accounting for 1bit;
step 4.1.2: setting far-end voltage information, which occupies 12 bits;
step 4.1.3: setting local voltage information, which occupies 12 bits;
step 4.1.4: setting current information, which is 12 bits;
step 4.1.5: setting state information, accounting for 16 bits, and executing the step 4.1.10;
step 4.1.6: setting format bit as high level, accounting for 1bit;
step 4.1.7: setting address information, accounting for 8 bits;
step 4.1.8: setting data information, accounting for 8 bits;
step 4.1.9: setting reserved 1 information, fixedly setting the reserved 1 information to be low level, occupying 36 bits for later expansion use, and executing the step 4.1.10;
step 4.1.10: setting handshake information, accounting for 8 bits, and fixedly setting X 'A5';
step 4.1.11: setting indication information, accounting for 1bit;
step 4.1.12: setting reserved 2 information, fixedly setting the reserved 2 information to be low level, occupying 2 bits for later expansion use, and executing the step 5;
step 4.2: performing a receive data operation;
step 4.2.1: detecting format information, occupying 1bit, and fixing the format information as high level;
step 4.2.2: detecting address information, wherein the address information occupies 20 bits;
step 4.2.3: detecting data information, wherein the data information occupies 16 bits;
step 4.2.4: detecting read-write information, wherein the read-write information occupies 1bit;
step 4.2.5: detecting reserved 1 information, accounting for 15 bits, and fixing the reserved 1 information as a low level;
step 4.2.6: detecting and judging handshake information, wherein the handshake information occupies 8 bits;
if: if the handshake information is equal to X "5A", step 4.2.7 is executed;
or if the handshake information is not equal to X '5A', executing the step 2;
step 4.2.7: detecting and reserving 2 information, occupying 3 bits, fixing to be low level, and executing the step 5;
step 5: and (3) ending the three-wire synchronous serial communication 1 frame, returning to the step (3), and executing the next 1 frame.
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| CN111666248A (en) * | 2020-06-16 | 2020-09-15 | 中国北方车辆研究所 | RS422 serial port communication control system and method based on FPGA |
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