CN111666248A - RS422 serial port communication control system and method based on FPGA - Google Patents
RS422 serial port communication control system and method based on FPGA Download PDFInfo
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The invention belongs to the technical field of serial port communication control, and particularly relates to an RS422 serial port communication control system and method based on FPGA, which comprises the following steps: master controller, RS422 serial ports communication control unit, interface unit, RS422 serial ports communication control unit is realized by FPGA, contains: the device comprises a register module, a baud rate generation module, an interrupt module, a transmission FIFO module, a transmission interface module, a reception FIFO module and a reception interface module. The method disclosed by the invention can receive data in a query mode and can also receive data in an interrupt mode, and the data is sent in a timed interrupt mode. The invention combines the high parallelism, high energy efficiency ratio and reconfigurability of the FPGA to realize the software of the hardware interface, improve the real-time performance of communication, simplify the circuit board and reduce the cost.
Description
Technical Field
The invention belongs to the technical field of serial port communication control, and particularly relates to an RS422 serial port communication control system and method based on an FPGA.
Background
At present in armoured vehicle communication control system, RS422 serial port bus is an important bus of control information interaction between each part, different systems are different to RS422 serial port bus's demand, in order to realize RS422 communication control core unit's universalization, traditional method adopts outer multichannel RS422 controller that expands to carry out the maximize design, as shown in figure 1, wherein the master controller generally adopts DSP, all instructions are serial execution, can't guarantee the real-time of communication, and the density of circuit board has been increased, the reliability of circuit board has been reduced, development cost has been increased.
Field Programmable Gate Arrays (FPGAs) are emerging as semi-custom Integrated circuits in the Field of Application Specific Integrated Circuits (ASICs). The FPGA combines the high performance and the high integration of the ASIC and the flexibility of a user programmable device, and is characterized by reconfigurability, higher performance and integration and large hardware upgrading space. Some FPGAs are provided with RS422 controller IP cores, but the IP cores are intellectual property cores and need to be purchased additionally, and project cost is greatly increased. Therefore, at present, a design scheme for controlling RS422 serial communication is urgently needed to be developed, so that the real-time performance of communication is improved, a circuit board is simplified, and the research and development cost is reduced.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to provide an RS422 serial port communication control scheme based on FPGA, combine high parallelism, high energy efficiency ratio and reconfigurability of FPGA with the modularization of hardware interface function, improve the real-time of communication, simplify the circuit board, reduce cost, shorten hardware development cycle, realize that the hardware can be configured.
(II) technical scheme
In order to solve the above technical problem, the present invention provides an RS422 serial port communication control system based on an FPGA, wherein the RS422 serial port communication control system comprises: the device comprises a main controller 1, an RS422 serial port communication control unit 2 and an interface unit 3;
the main controller 1 is used for performing read-write operation on the RS422 serial port communication control unit 2 through a data line signal, an address line signal and a read-write enabling signal;
RS422 serial port communication control unit 2 is realized by FPGA, includes: the device comprises a register module 2.1, a baud rate generation module 2.2, an interrupt module 2.3, a transmission FIFO module 2.4, a transmission interface module 2.5, a reception FIFO module 2.6 and a reception interface module 2.7;
the register module 2.1 comprises: the device comprises an address decoding module, a register and a register reading and writing module; all configuration and communication of the RS422 serial port bus are realized by operating a register, and the address decoding module is used for receiving an address line signal of the main controller 1 and allocating an address to the register;
the baud rate generating module 2.2 is used for generating a communication baud rate by utilizing a DLL register and a DLM register and combining an external clock;
the interrupt module 2.3 is used for generating and receiving interrupt to the main controller 1 by utilizing the IIR register;
the transmission FIFO module 2.4 is used for caching data transmitted to other RS422 equipment by the master controller 1;
the sending interface module 2.5 is used for performing parallel-serial conversion on data to be sent by the master controller 1 and sending the data to the interface unit 3 through the THR register;
the receiving FIFO module 2.6 is configured to cache data sent to the master controller 1 by other RS422 devices, that is, cache data that needs to be received by the master controller 1;
the receiving interface module 2.7 is used for receiving the data received by the interface unit 3 through the RBR register and performing serial-parallel conversion;
the interface unit 3, which includes: isolator 3.1 and transceiver 3.2; the isolator 3.1 is used for isolating serial data received and transmitted by the RS422 serial port communication control unit 2, and the transceiver 3.2 is used for interconnecting with other equipment and receiving and transmitting data.
The RS422 serial port communication control unit 2 is realized by FPGA.
Wherein the registers in the register module 2.1 comprise: DLL register, DLM register, IIR register, THR register, RBR register.
In addition, the invention also provides an RS422 serial port communication control method based on FPGA, which is implemented based on the RS422 serial port communication control system, and the RS422 serial port communication control method comprises the following steps in the process of receiving data:
step 11: the transceiver 3.2 receives differential serial data and converts it to single-ended serial data;
step 12: the isolator 3.1 isolates the received single-ended serial data and sends the isolated single-ended serial data to a receiving IO port of the RS422 serial port communication control unit 2;
step 13: the baud rate generating module 2.2 generates the required communication baud rate by utilizing a DL register and a DLM register and combining an external clock;
step 14: the receiving interface module 2.7 receives data of a receiving IO port of the RS422 serial port communication control unit 2 through the RBR register, and performs serial-parallel conversion;
step 15: the receiving FIFO module 2.6 caches the parallel data converted by the receiving interface module 2.7;
step 16: the master 1 obtains the data in the receive FIFO module 2.6.
In step 16, the master 1 queries the data in the receiving FIFO module 2.6 by means of a query.
In step 16, the receiving FIFO module 2.6 generates a receiving interrupt through the interrupt module 2.3 after receiving the data, and the master controller 1 reads the data from the receiving FIFO module 2.6 after receiving the interrupt signal.
The method comprises the following steps in the data sending process:
step 21: the main controller 1 sends data to the transmission FIFO module 2.4 through a data address line;
step 22: the transmission FIFO module 2.4 receives and caches the parallel data transmitted by the main controller 1;
step 23: the sending interface module 2.5 performs parallel-to-serial conversion on the parallel data cached by the sending FIFO module 2.4, and sends the parallel data to a sending IO port of the RS422 serial port communication control unit 2 through the THR register;
step 24: the isolator 3.1 isolates data of an IO port sent by the RS422 serial port communication control unit 2 and then sends the data to the transceiver 3.2;
step 25: the transceiver 3.2 converts the single-ended serial data into differential serial data for further communication devices.
The RS422 serial port communication control unit 2 is realized by FPGA.
Wherein the registers in the register module 2.1 comprise: DLL register, DLM register, IIR register, THR register, RBR register.
In step 21, the master controller 1 sends data to the FIFO sending module 2.4 via the data address line according to a timed interrupt mode.
(III) advantageous effects
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention adopts the FPGA to realize the RS422 serial port communication control unit, and combines the high parallelism, the high energy efficiency ratio and the reconfigurability of the FPGA to modularize the hardware interface function, thereby improving the real-time performance of communication, simplifying a circuit board and reducing the cost.
(2) The RS422 serial port communication control method based on the FPGA provided by the invention can receive data in an inquiry mode and can also receive data in an interruption mode.
Drawings
Fig. 1 is a schematic diagram of a conventional external-expansion multi-RS 422 communication interface.
Fig. 2 is a schematic diagram of an architecture of an external-expansion multi-path RS422 communication interface implemented by the present invention.
FIG. 3 is a schematic diagram of an RS422 serial port communication control unit implemented by FPGA according to the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
In order to solve the above technical problem, the present invention provides an RS422 serial port communication control system based on an FPGA, as shown in fig. 2 to 3, the RS422 serial port communication control system includes: the device comprises a main controller 1, an RS422 serial port communication control unit 2 and an interface unit 3;
the main controller 1 is used for performing read-write operation on the RS422 serial port communication control unit 2 through a data line signal, an address line signal and a read-write enabling signal;
RS422 serial port communication control unit 2 is realized by FPGA, includes: the device comprises a register module 2.1, a baud rate generation module 2.2, an interrupt module 2.3, a transmission FIFO module 2.4, a transmission interface module 2.5, a reception FIFO module 2.6 and a reception interface module 2.7;
the register module 2.1 comprises: the device comprises an address decoding module, a register and a register reading and writing module; all configuration and communication of the RS422 serial port bus are realized by operating a register, and the address decoding module is used for receiving an address line signal of the main controller 1 and allocating an address to the register;
the baud rate generating module 2.2 is used for generating a communication baud rate by utilizing a DLL register and a DLM register and combining an external clock;
the interrupt module 2.3 is used for generating and receiving interrupt to the main controller 1 by utilizing the IIR register;
the transmission FIFO module 2.4 is used for caching data transmitted to other RS422 equipment by the master controller 1;
the sending interface module 2.5 is used for performing parallel-serial conversion on data to be sent by the master controller 1 and sending the data to the interface unit 3 through the THR register;
the receiving FIFO module 2.6 is configured to cache data sent to the master controller 1 by other RS422 devices, that is, cache data that needs to be received by the master controller 1;
the receiving interface module 2.7 is used for receiving the data received by the interface unit 3 through the RBR register and performing serial-parallel conversion;
the interface unit 3, which includes: isolator 3.1 and transceiver 3.2; the isolator 3.1 is used for isolating serial data received and transmitted by the RS422 serial port communication control unit 2, and the transceiver 3.2 is used for interconnecting with other equipment and receiving and transmitting data.
The RS422 serial port communication control unit 2 is realized by FPGA.
Wherein the registers in the register module 2.1 comprise: DLL register, DLM register, IIR register, THR register, RBR register.
In addition, the present invention also provides an RS422 serial port communication control method based on FPGA, as shown in fig. 2 to fig. 3, the method is implemented based on the RS422 serial port communication control system, and the RS422 serial port communication control method includes the following steps in a data receiving process:
step 11: the transceiver 3.2 receives differential serial data and converts it to single-ended serial data;
step 12: the isolator 3.1 isolates the received single-ended serial data and sends the isolated single-ended serial data to a receiving IO port of the RS422 serial port communication control unit 2;
step 13: the baud rate generating module 2.2 generates the required communication baud rate by utilizing a DL register and a DLM register and combining an external clock;
step 14: the receiving interface module 2.7 receives data of a receiving IO port of the RS422 serial port communication control unit 2 through the RBR register, and performs serial-parallel conversion;
step 15: the receiving FIFO module 2.6 caches the parallel data converted by the receiving interface module 2.7;
step 16: the master 1 obtains the data in the receive FIFO module 2.6.
In step 16, the master 1 queries the data in the receiving FIFO module 2.6 by means of a query.
In step 16, the receiving FIFO module 2.6 generates a receiving interrupt through the interrupt module 2.3 after receiving the data, and the master controller 1 reads the data from the receiving FIFO module 2.6 after receiving the interrupt signal.
The method comprises the following steps in the data sending process:
step 21: the main controller 1 sends data to the transmission FIFO module 2.4 through a data address line;
step 22: the transmission FIFO module 2.4 receives and caches the parallel data transmitted by the main controller 1;
step 23: the sending interface module 2.5 performs parallel-to-serial conversion on the parallel data cached by the sending FIFO module 2.4, and sends the parallel data to a sending IO port of the RS422 serial port communication control unit 2 through the THR register;
step 24: the isolator 3.1 isolates data of an IO port sent by the RS422 serial port communication control unit 2 and then sends the data to the transceiver 3.2;
step 25: the transceiver 3.2 converts the single-ended serial data into differential serial data for further communication devices.
The RS422 serial port communication control unit 2 is realized by FPGA.
Wherein the registers in the register module 2.1 comprise: DLL register, DLM register, IIR register, THR register, RBR register.
In step 21, the master controller 1 sends data to the FIFO sending module 2.4 via the data address line according to a timed interrupt mode.
Example 1
The embodiment provides an RS422 serial port communication control method based on an FPGA, which mainly comprises three parts: the first part is a master controller; the second part is RS422 serial port communication control unit, is realized by FPGA, includes: a register module, a baud rate generation module, an interrupt module, a transmission FIFO module, a transmission interface module, a reception FIFO module, and a reception interface module, as shown in fig. 3; the third part is an interface unit comprising an isolator and a transceiver.
The RS422 serial port communication control method comprises the following steps:
(1) receiving data:
step 1: the transceiver 3.2 receives the differential serial data and converts it into single-ended serial data;
step 2: the isolator 3.1 isolates the received single serial data and then sends the isolated single serial data to a receiving IO port of the FPGA;
and step 3: the baud rate generating module 2.2 generates the required communication baud rate by utilizing a DLL (delay locked loop) and a DLM (digital Living model) register and combining an external clock;
and 4, step 4: the receiving interface module 2.7 receives the data of the IO port received by the FPGA through the RHR register and carries out serial-parallel conversion;
and 5: the receiving FIFO module 2.6 caches the parallel data converted by the receiving interface module 2.7;
step 6: the main controller 1 queries the receiving FIFO module 2.6 by a query manner, or the receiving FIFO module 2.6 generates a receiving interrupt by the interrupt module 2.3 after receiving data, and the main controller 1 reads data from the receiving FIFO module 2.6 after receiving an interrupt signal.
(2) And a data sending step:
step 1: the main controller 1 sends data to the transmission FIFO module 2.4 through a data address line in a timing interruption mode;
step 2: the transmission FIFO module 2.4 receives the parallel data transmitted by the main controller 1 for caching;
and step 3: the transmission interface module 2.5 is used for carrying out parallel-serial conversion on the parallel data cached by the transmission FIFO module 2.4 and transmitting the parallel data to the FPGA to an IO port through the THR register;
and 4, step 4: the isolator 3.1 isolates the data of the IO port sent by the FPGA and then sends the data to the transceiver 3.2;
and 5: the transceiver 3.2 converts the single-ended serial data into differential serial data for further communication devices.
In the specific embodiment of the invention, the master controller preferably selects DSPTMS320F28335 of TI company, the FPGA preferably selects XC6SLX45T of xilinx company, the function of the RS422 serial port communication control unit is realized to be the same as ST16C550, the isolator preferably selects ISO7221, and the transceiver preferably selects MAX 490.
In summary, the RS422 serial port communication control unit is realized by using the FPGA, and the hardware interface is software-based by combining the high parallelism, the high energy efficiency ratio and the reconfigurability of the FPGA, so that the real-time performance of communication is improved, the circuit board is simplified, and the cost is reduced. And the RS422 serial port communication control unit realized based on the FPGA can receive data in an inquiry mode and also can receive data in an interruption mode.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. The utility model provides a RS422 serial ports communication control system based on FPGA which characterized in that, RS422 serial ports communication control system includes: the device comprises a main controller (1), an RS422 serial port communication control unit (2) and an interface unit (3);
the main controller (1) is used for performing read-write operation on the RS422 serial port communication control unit (2) through a data line signal, an address line signal and a read-write enabling signal;
the RS422 serial port communication control unit (2) is realized by FPGA, and comprises: the device comprises a register module (2.1), a baud rate generation module (2.2), an interrupt module (2.3), a transmission FIFO module (2.4), a transmission interface module (2.5), a reception FIFO module (2.6) and a reception interface module (2.7);
the register module (2.1) comprises: the device comprises an address decoding module, a register and a register reading and writing module; all configuration and communication of the RS422 serial port bus are realized by operating a register, and the address decoding module is used for receiving an address line signal of the main controller (1) and allocating an address to the register;
the baud rate generating module (2.2) is used for generating a communication baud rate by utilizing a DLL register and a DLM register and combining an external clock;
the interrupt module (2.3) is used for generating and receiving an interrupt to the master controller (1) by utilizing the IIR register;
the transmission FIFO module (2.4) is used for caching data transmitted to other RS422 equipment by the master controller (1);
the sending interface module (2.5) is used for performing parallel-serial conversion on data needing to be sent by the main controller (1) and sending the data to the interface unit (3) through the THR register;
the receiving FIFO module (2.6) is used for caching data sent by other RS422 equipment to the master controller (1), namely caching the data required to be received by the master controller (1);
the receiving interface module (2.7) is used for receiving the data received by the interface unit (3) through the RBR register and performing serial-parallel conversion;
the interface unit (3) comprising: an isolator (3.1) and a transceiver (3.2); the isolator (3.1) is used for isolating serial data transmitted and received by the RS422 serial port communication control unit (2), and the transceiver (3.2) is used for being interconnected with other equipment to transmit and receive data.
2. The FPGA-based RS422 serial port communication control system of claim 1, characterized in that the RS422 serial port communication control unit (2) is realized by FPGA.
3. The FPGA-based RS422 serial port communication control system of claim 1, wherein the register in the register module (2.1) comprises: DLL register, DLM register, IIR register, THR register, RBR register.
4. An RS422 serial port communication control method based on FPGA is characterized in that the method is implemented based on the RS422 serial port communication control system, and the RS422 serial port communication control method comprises the following steps in the data receiving process:
step 11: the transceiver (3.2) receives differential serial data and converts it into single-ended serial data;
step 12: the isolator (3.1) isolates the received single-ended serial data and then sends the single-ended serial data to a receiving IO port of the RS422 serial port communication control unit (2);
step 13: the baud rate generating module (2.2) generates the required communication baud rate by utilizing a DL register and a DLM register and combining an external clock;
step 14: the receiving interface module (2.7) receives data of a receiving IO port of the RS422 serial port communication control unit (2) through the RBR register, and performs serial-parallel conversion;
step 15: the receiving FIFO module (2.6) buffers the parallel data converted by the receiving interface module (2.7);
step 16: the master (1) obtains data in a receive FIFO module (2.6).
5. The RS422 serial port communication control method based on FPGA of claim 4, characterized in that in step 16, the master controller (1) inquires the data in the receiving FIFO module (2.6) by inquiry.
6. The FPGA-based RS422 serial port communication control method of claim 4, wherein in the step 16, the receiving FIFO module (2.6) generates a receiving interrupt through the interrupt module (2.3) after receiving the data, and the master controller (1) reads the data from the receiving FIFO module (2.6) after receiving the interrupt signal.
7. The RS422 serial port communication control method based on FPGA of claim 4, wherein in the data sending process, the method comprises the following steps:
step 21: the main controller (1) sends data to the transmission FIFO module (2.4) through a data address line;
step 22: the transmission FIFO module (2.4) receives and caches the parallel data transmitted by the main controller (1);
step 23: the sending interface module (2.5) performs parallel-serial conversion on the parallel data cached by the sending FIFO module (2.4), and sends the parallel data to a sending IO port of the RS422 serial port communication control unit (2) through the THR register;
step 24: the isolator (3.1) isolates data of an IO port sent by the RS422 serial port communication control unit (2) and then sends the data to the transceiver (3.2);
step 25: the transceiver (3.2) converts the single-ended serial data into differential serial data for other communication equipment.
8. The RS422 serial port communication control method based on FPGA of claim 7, characterized in that the RS422 serial port communication control unit (2) is realized by FPGA.
9. The FPGA-based RS422 serial port communication control system of claim 7, wherein the registers in the register module (2.1) include: DLL register, DLM register, IIR register, THR register, RBR register.
10. The FPGA-based RS422 serial port communication control system of claim 7, wherein in step 21, the master controller (1) sends data to the transmission FIFO module (2.4) through the data address line according to a timed interrupt mode.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112540942A (en) * | 2020-11-20 | 2021-03-23 | 中电科仪器仪表(安徽)有限公司 | Multi-channel synchronous serial communication circuit and method |
| CN113609067A (en) * | 2021-06-25 | 2021-11-05 | 天津津航计算技术研究所 | Implementation system of 32-channel RS485 interface card |
| CN114615104A (en) * | 2022-03-14 | 2022-06-10 | 鹍骐科技（北京）股份有限公司 | Intelligent serial port communication method and system realized based on domestic FPGA |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760111A (en) * | 2012-06-27 | 2012-10-31 | 浙江大学 | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof |
| CN202870808U (en) * | 2012-07-04 | 2013-04-10 | 四川九洲电器集团有限责任公司 | FPGA realization device of SPI serial port module |
| CN106201946A (en) * | 2016-06-29 | 2016-12-07 | 北京航天自动控制研究所 | A kind of satellite borne electronic system data interface based on FPGA and DSP |
| CN109857685A (en) * | 2018-12-06 | 2019-06-07 | 积成电子股份有限公司 | A kind of implementation method of MPU and FPGA expanding multiple serial ports |
-
2020
- 2020-06-16 CN CN202010548707.1A patent/CN111666248A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102760111A (en) * | 2012-06-27 | 2012-10-31 | 浙江大学 | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof |
| CN202870808U (en) * | 2012-07-04 | 2013-04-10 | 四川九洲电器集团有限责任公司 | FPGA realization device of SPI serial port module |
| CN106201946A (en) * | 2016-06-29 | 2016-12-07 | 北京航天自动控制研究所 | A kind of satellite borne electronic system data interface based on FPGA and DSP |
| CN109857685A (en) * | 2018-12-06 | 2019-06-07 | 积成电子股份有限公司 | A kind of implementation method of MPU and FPGA expanding multiple serial ports |
Non-Patent Citations (1)
| Title |
|---|
| 刘杰等: "一种新型的FPGA实现RS422串口通信方法", 《计算机测量与控制》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112540942A (en) * | 2020-11-20 | 2021-03-23 | 中电科仪器仪表(安徽)有限公司 | Multi-channel synchronous serial communication circuit and method |
| CN112540942B (en) * | 2020-11-20 | 2023-06-02 | 中电科思仪科技(安徽)有限公司 | Multichannel synchronous serial communication circuit and method |
| CN113609067A (en) * | 2021-06-25 | 2021-11-05 | 天津津航计算技术研究所 | Implementation system of 32-channel RS485 interface card |
| CN113609067B (en) * | 2021-06-25 | 2024-03-19 | 天津津航计算技术研究所 | System for realizing 32-channel RS485 interface card |
| CN114615104A (en) * | 2022-03-14 | 2022-06-10 | 鹍骐科技（北京）股份有限公司 | Intelligent serial port communication method and system realized based on domestic FPGA |
| CN114615104B (en) * | 2022-03-14 | 2023-11-28 | 鹍骐科技（北京）股份有限公司 | Intelligent serial port communication method and system based on domestic FPGA |
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