CN113609067A - Implementation system of 32-channel RS485 interface card - Google Patents

Implementation system of 32-channel RS485 interface card Download PDF

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CN113609067A
CN113609067A CN202110712019.9A CN202110712019A CN113609067A CN 113609067 A CN113609067 A CN 113609067A CN 202110712019 A CN202110712019 A CN 202110712019A CN 113609067 A CN113609067 A CN 113609067A
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module
data
serial port
memory
write
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CN113609067B (en
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汤晓磊
胡亮
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Tianjin Jinhang Computing Technology Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846—On-chip cache and off-chip main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The embodiment of the invention discloses a system for realizing a 32-channel RS485 interface card. The system comprises: the FPGA chip comprises 32 serial port modules, a DDR IP core and an AXI bus, wherein each serial port module is connected with the RS485 interface through the RS485 level conversion chip, the DDR IP core is respectively connected with the AXI bus and the memory chip, and the memory chip is used for caching data received and transmitted through the RS485 interface. The embodiment of the invention can solve the problem of packet loss caused by simultaneous communication of multiple RS485 serial interfaces, improve the efficiency of the system and solve the problem of host loss and interruption caused by excessive interruption.

Description

Implementation system of 32-channel RS485 interface card
Technical Field
The invention relates to the technical field of computer interface communication, in particular to a system for realizing a 32-channel RS485 interface card.
Background
In the field of industrial control, an RS485 interface is a common communication interface and is generally implemented by using an RS485 interface chip, and the implementation method has the following problems:
1) the RS485 interface chip generally has at most 4 RS485 serial interfaces, if the number of actually required paths is large, a plurality of interface chips are required to be connected in parallel, and a PCIE switching chip is required to be additionally arranged, so that the occupied printed board area is large, and the cost is high;
2) when RS485 multi-path simultaneous communication is carried out, due to the fact that the processing capacity of a host is limited, reading and writing are not timely, and packet loss is caused.
Disclosure of Invention
The technical problem solved by the invention is as follows: the defects of the prior art are overcome, and a 32-channel RS485 interface card realization system is provided.
In order to solve the above technical problem, an embodiment of the present invention provides a system for implementing a 32-channel RS485 interface card, where the system includes: the FPGA chip comprises 32 serial port modules, a DDR IP core and an AXI bus, wherein each serial port module is connected with the RS485 interface through the RS485 level conversion chip, the DDR IP core is respectively connected with the AXI bus and the memory chip, and the memory chip is used for caching data received and transmitted through the RS485 interface.
Optionally, the FPGA chip further includes: a memory read-write module, an interrupt generation module, a PCIE module and an AXI-LITE bus, wherein,
the memory read-write module is respectively connected with the AXI bus and the serial port module;
the PCIE module is connected with the AXI bus, and the PCIE module is connected with the interrupt generation module through the AXI-LITE bus;
the interrupt generation module is also connected with the memory read-write module.
Optionally, the serial port module includes: a transmission FIFO element, a transmission element, a reception FIFO element, and a reception element, wherein,
the data flow direction of the serial port module comprises a data receiving path and a data sending path;
in a data receiving path, the receiving unit receives a serial port waveform signal through a receiving pin, converts the serial port waveform signal into byte data and sends the byte data to the receiving FIFO unit, and the memory read-write module reads data of the receiving FIFO unit by judging a null signal of the receiving FIFO unit;
in a data sending path, byte data sent by the memory read-write module is written into the sending FIFO unit by the serial port module, and the sending unit converts the byte data in the sending FIFO into a serial port waveform and sends the serial port waveform to the RS485 level conversion chip through a sending pin.
Optionally, the number of the interrupt generating modules is 8, four of the 32 serial port modules are divided into a group, and the serial port modules in each group share one interrupt generating module.
Optionally, a receiving unit in the serial port module implements conversion from byte data to serial port waveforms through a state machine, where the state machine includes an idle state, a receiving start bit, a receiving data bit, a receiving stop bit, and a sending write enable, and a start signal of the state machine is a falling edge of a receiving pin.
Optionally, a sending unit in the serial port module realizes conversion from serial port waveforms to byte data through a state machine, the state machine includes idle, sending read enable, latching sending data, sending start bits, sending data bits, and sending stop bits, and a start signal of the state machine is a null signal of 0.
Optionally, the memory read-write module is configured to implement data transfer control between the transmit FIFO unit and the receive FIFO unit in the serial port module and the memory chip;
the memory read-write module comprises a memory read channel and a memory write channel,
in the memory read path, the memory read-write module sends the sending data in the 32 sending areas of the memory chip through the serial port module;
in the memory write path, the memory read-write module writes data received by the 32 serial port modules into the 32 receiving areas of the memory chip, and generates an interrupt request signal to the interrupt generation module.
Optionally, after the interrupt generation module receives a request signal of any interrupt generation module generated by the memory read-write module, setting an interrupt output signal connected to the PCIE module to 1, so that the PCIE module generates host interrupt;
after the host responds to the interrupt, reading data in a corresponding area of a memory through the AXI bus of the PCIE module, and sending a response signal to an interrupt generation module through the AXI-LITE bus of the PCIE module, wherein the interrupt generation module clears the interrupt output.
Optionally, in the memory read path, sending the sending data in the memory chip through a serial port module;
writing data to be sent into a storage area of the memory chip through an AXI bus of the PCIE module by a host, and changing a write pointer of the storage area;
circularly inquiring the read pointer and the write pointer in 32 sending areas in the memory chip by the FPGA program, if the two pointers are different in position, reading the data in the memory through the AXI bus and writing the data into a sending FIFO in a corresponding serial port module, and updating the read pointer in the memory area;
in the memory write path, circularly inquiring the receiving FIFO units of the 32 serial port modules, if the receiving FIFO units have data, reading the data and writing the data into the corresponding area of the memory through the AXI bus, updating the write pointer of the area of the memory, and generating an interrupt request signal to the interrupt generation module.
Compared with the prior art, the invention has the advantages that:
compared with the traditional special serial port chip method, the method is more flexible and has better expansibility, and the problem of packet loss caused by simultaneous communication of the multiple RS485 serial ports is solved by adopting a two-stage caching method of the multiple RS485 serial ports, namely FIFO and two-stage caching of a memory chip; and moreover, an interrupt processing method of the FPGA and the upper computer is provided, the efficiency of the system is improved, and the problem that the host is lost and interrupted due to excessive interruption is solved.
Drawings
Fig. 1 is a block diagram of an implementation system of a 32-way RS485 interface card according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating an FPGA implementation principle of a 32-channel RS485 interface card according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a serial port module according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a serial port transmitting unit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a serial port receiving unit according to an embodiment of the present invention.
Detailed Description
Example one
Referring to fig. 1, a schematic diagram of an implementation system of a 32-way RS485 interface card according to an embodiment of the present invention is shown, and as shown in fig. 1, the implementation system 100 of the 32-way RS485 interface card may include: an FPGA (Field Programmable Gate Array) chip 110, an RS485 level conversion chip 120, and a memory chip 130, where the FPGA chip 110 includes 32 serial port modules 121, a DDR IP core 122, and an AXI (advanced eXtensible interface) bus 123, where each serial port module 121 is connected to an RS485 interface through the RS485 level conversion chip 120, the DDR IP core 122 is connected to the AXI bus 123 and the memory chip 130, and the memory chip 130 caches data received and transmitted through the RS485 interface.
The embodiment of the invention realizes the RS485 serial interface through FPGA logic, and realizes the reliable communication of the PCIE and the 32-channel RS485 serial interface without packet loss by using two-stage cache of a memory and an FIFO and a packet interrupt mode.
An embodiment of the present invention is described in detail below with reference to fig. 2.
Referring to fig. 2, a schematic diagram of an FPGA implementation principle of a 32-channel RS485 interface card according to an embodiment of the present invention is shown, as shown in fig. 2, an FPGA chip, an RS485 level conversion chip, and a memory chip are main chips of the 32-channel RS485 interface card, and the FPGA chip is a core chip of the interface card, and implements functions of a 32-channel serial port module, a memory read/write module, an interrupt generation module, a PCIE (peripheral component interconnect express) module, a DDR IP core, an AXI bus and an AXI-LITE bus between modules, and the like; the level conversion chip converts the RS485 signal into a serial port waveform of TTL level, accesses the serial port module, and converts the serial port waveform of the TTL level output by the serial port module into an RS485 signal; the memory chip is used for caching the transceiving data of the RS485 interface, the storage area of the memory chip is divided into 32 receiving areas and 32 sending areas, the 32 receiving areas and the 32 sending areas are respectively used for caching the receiving data of the 32-path RS485 interface and the sending data of the 32-path RS485 interface, and the first two bytes of each area store a read pointer and a write pointer of the area; the host is connected with the FPGA chip through a PCIE X1 interface.
In the FPGA chip shown in fig. 2, the serial modules 0 to 31 are 32 identical serial modules, so as to implement 32 RS485 serial communications, and the block diagram of the serial modules is shown in fig. 3.
The DDR IP core shown in fig. 2 realizes communication between the AXI bus and the memory chip, so that the memory read-write module and the PCIE module can read and write the memory chip through the AXI bus.
The memory read-write module shown in fig. 2 completes data transfer control between the transmit FIFO unit and the receive FIFO unit of the serial port module and the memory chip, and implements second-level data caching of the FIFO and the memory. The memory read-write module comprises a memory read channel and a memory write channel.
And the memory reading path sends the sending data in the memory through the serial port module. Writing data to be sent into a storage area of a memory chip through an AXI bus of a PCIE module by a host, and changing a write pointer of the area; the FPGA program circularly inquires the read pointers and the write pointers in 32 sending areas in the memory chip, if the two pointers are different in position, the data in the memory is read through the AXI bus and written into a sending FIFO unit in a corresponding serial port module, and then the read pointers in the memory areas are updated; the memory write path circularly inquires the receiving FIFO units of the serial port modules 0-31, if the receiving FIFO units have data, the data is read out and written into the corresponding area of the memory through the AXI bus, the write pointer of the area of the memory is updated, and an interrupt request signal is generated to the interrupt generation module;
because the number of serial ports is large, if each port can be interrupted, the interruption of the host computer is lost, so that the 32-port serial ports are divided into 8 groups, and 1 group of every 4-port serial ports share one interruption, so that the total number of the interruptions is 8. After receiving a certain interrupt request signal generated by the memory read-write module, the interrupt generation module shown in fig. 2 sets an interrupt output signal connected to the PCIE module to 1, so that the PCIE module generates host interrupt; after the host responds to the interrupt, the host reads the data of the corresponding area of the memory through the AXI bus of the PCIE module, updates the read pointer of the area, sends a response signal to the interrupt generation module through the AXI-LITE bus of the PCIE module, and clears the interrupt output by the interrupt generation module.
The serial port module is described in detail below with reference to fig. 3.
Referring to fig. 3, a schematic diagram of a serial port module according to an embodiment of the present invention is shown, and as shown in fig. 3, the serial port module may be divided into a data receiving path and a data sending path according to a data flow direction: in the data receiving path, a receiving module receives serial port waveform signals through a receiving pin, converts the serial port waveform signals into byte data and sends the byte data to a receiving FIFO unit, and a memory read-write module reads data cached by the receiving FIFO unit by judging empty signals in the receiving FIFO unit; in the data transmission path, byte data transmitted by the memory read-write module is written into the transmission FIFO unit by the serial port module, and the transmission module converts the byte data in the transmission FIFO unit into serial port waveforms and transmits the serial port waveforms to the RS485 level conversion chip through the transmission pin.
Next, the following detailed description is made on the transmitting unit of the serial port module according to the embodiment of the present invention with reference to fig. 4.
Referring to fig. 4, a schematic diagram of a serial port sending unit according to an embodiment of the present invention is shown, as shown in fig. 4, the serial port sending unit implements conversion from serial port waveforms to byte data through a state machine, where the state machine includes idle, sending read enable, latching sending data, sending start bit, sending data bit, and sending stop bit. When the empty signal of the transmission FIFO element is 0, the state machine starts transmission of one byte of data.
Next, the following detailed description is made on the receiving unit of the serial port module according to the embodiment of the present invention with reference to fig. 5.
Referring to fig. 5, a schematic diagram of a serial port receiving unit according to an embodiment of the present invention is shown, as shown in fig. 5, the serial port receiving unit implements conversion from byte data to serial port waveforms by using a state machine, where the state machine includes an idle state, a receiving start bit, a receiving data bit, a receiving stop bit, and a sending write enable. When the receiving pin has a falling edge, the state machine starts the reception of one byte of data.
Compared with the prior art, the implementation system of the 32-channel RS485 interface card provided by the embodiment of the invention has the following beneficial effects:
compared with the traditional special serial port chip method, the method is more flexible and has better expansibility, and a two-stage cache method of the multi-path RS485 serial interface, namely two-stage cache of an FIFO (first in first out) and a memory chip is adopted, so that the problem of packet loss of simultaneous communication of the multi-path RS485 serial interface is solved, and the method is also suitable for multi-path interface circuits of other types; and moreover, an interrupt processing method of the FPGA and the upper computer is provided, the efficiency of the system is improved, and the problem that the host is lost and interrupted due to excessive interruption is solved.
The detailed description set forth herein may provide those skilled in the art with a more complete understanding of the present application, and is not intended to limit the present application in any way. Thus, it will be appreciated by those skilled in the art that modifications or equivalents may still be made to the present application; all technical solutions and modifications thereof which do not depart from the spirit and technical essence of the present application should be covered by the scope of protection of the present patent application.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.

Claims (9)

1. A system for implementing a 32-way RS485 interface card, the system comprising: the FPGA chip comprises 32 serial port modules, a DDRIP core and an AXI bus, wherein each serial port module is connected with the RS485 interface through the RS485 level conversion chip, the DDRIP core is respectively connected with the AXI bus and the memory chip, and the memory chip is used for caching data received and transmitted through the RS485 interface.
2. The system of claim 1, wherein the FPGA chip further comprises: a memory read-write module, an interrupt generation module, a PCIE module and an AXI-LITE bus, wherein,
the memory read-write module is respectively connected with the AXI bus and the serial port module;
the PCIE module is connected with the AXI bus, and the PCIE module is connected with the interrupt generation module through the AXI-LITE bus;
the interrupt generation module is also connected with the memory read-write module.
3. The system of claim 1, wherein the serial module comprises: a transmission FIFO element, a transmission element, a reception FIFO element, and a reception element, wherein,
the data flow direction of the serial port module comprises a data receiving path and a data sending path;
in a data receiving path, the receiving unit receives a serial port waveform signal through a receiving pin, converts the serial port waveform signal into byte data and sends the byte data to the receiving FIFO unit, and the memory read-write module reads data of the receiving FIFO unit by judging a null signal of the receiving FIFO unit;
in a data sending path, byte data sent by the memory read-write module is written into the sending FIFO unit by the serial port module, and the sending unit converts the byte data in the sending FIFO into a serial port waveform and sends the serial port waveform to the RS485 level conversion chip through a sending pin.
4. The system according to claim 1, wherein the number of the interrupt generating modules is 8, and every four of the 32 serial port modules are grouped into one group, and the serial port modules in each group share one interrupt generating module.
5. The system of claim 1, wherein the receiving unit in the serial port module implements conversion from byte data to serial port waveforms by a state machine, the state machine includes an idle state, a receive start bit, a receive data bit, a receive stop bit, and a send write enable, and a start signal of the state machine is a falling edge of a receive pin.
6. The system of claim 1, wherein the sending unit in the serial port module implements conversion from serial port waveforms to byte data through a state machine, the state machine includes idle, send read enable, latch send data, send start bit, send data bit, send stop bit, and the start signal of the state machine is null 0.
7. The system according to claim 2, wherein the memory read/write module is configured to implement data transfer control between the transmit FIFO elements and the receive FIFO elements in the serial port module and the memory chip;
the memory read-write module comprises a memory read channel and a memory write channel,
in the memory read path, the memory read-write module sends the sending data in the 32 sending areas of the memory chip through the serial port module;
in the memory write path, the memory read-write module writes data received by the 32 serial port modules into the 32 receiving areas of the memory chip, and generates an interrupt request signal to the interrupt generation module.
8. The system according to claim 7, wherein after the interrupt generation module receives a request signal of any interrupt generation module generated by the memory read/write module, the interrupt output signal connected to the PCIE module is set to 1, so that the PCIE module generates host interrupt;
after the host responds to the interrupt, reading data in a corresponding area of a memory through the AXI bus of the PCIE module, and sending a response signal to an interrupt generation module through the AXI-LITE bus of the PCIE module, wherein the interrupt generation module clears the interrupt output.
9. The system according to claim 7, wherein in the memory read path, the transmission data in the memory chip is transmitted through a serial module;
writing data to be sent into a storage area of the memory chip through an AXI bus of the PCIE module by a host, and changing a write pointer of the storage area;
circularly inquiring the read pointer and the write pointer in 32 sending areas in the memory chip by the FPGA program, if the two pointers are different in position, reading the data in the memory through the AXI bus and writing the data into a sending FIFO in a corresponding serial port module, and updating the read pointer in the memory area;
in the memory write path, circularly inquiring the receiving FIFO units of the 32 serial port modules, if the receiving FIFO units have data, reading the data and writing the data into the corresponding area of the memory through the AXI bus, updating the write pointer of the area of the memory, and generating an interrupt request signal to the interrupt generation module.
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