CN110781112A - Dual-channel serial RapidIO interface supporting multiple transmission modes - Google Patents
Dual-channel serial RapidIO interface supporting multiple transmission modes Download PDFInfo
- Publication number
- CN110781112A CN110781112A CN201911012232.8A CN201911012232A CN110781112A CN 110781112 A CN110781112 A CN 110781112A CN 201911012232 A CN201911012232 A CN 201911012232A CN 110781112 A CN110781112 A CN 110781112A
- Authority
- CN
- China
- Prior art keywords
- channel
- packet
- data
- dual
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
A dual-lane serial RapidIO interface supporting multiple transmission modes, comprising: the controller is used for exchanging data with the interior of the system, generating a request packet and processing a response packet, and selecting a path used for data transmission; the logic layer and transmission layer circuit is used for taking charge of tasks such as packet format conversion, packet caching and the like and sending an input request to the controller; the physical protocol layer is used for being responsible for CRC check, idle sequence generation, transmission flow control and error management; the PCS layer is used for carrying out synchronization and 8B/10B decoding on the received data on each LANE; the SerDes unit is used for performing data conversion between the parallel code group of the PCS layer and the link serial code stream to complete the function defined by the PMA layer in the RapidIO protocol; and the cross switch is positioned between the PCS layer and the SerDes and used for interconnecting the channels of the PCS layer and the SerDes according to the channel mode. The invention has the advantages of simple structure, capability of improving interconnection flexibility and transmission bandwidth and the like.
Description
Technical Field
The invention mainly relates to the technical field of embedded on-chip high-speed interconnection, in particular to a dual-channel serial RapidIO interface supporting multiple transmission modes.
Background
Most existing serial RapidIO interfaces strictly conform to the RapidIO standard, 4 links are formed by 4 pairs of full-duplex differential signal lines, each link is called a LANE, and a transmission path is formed by a plurality of LANEs according to different transmission modes.
According to the RapidIO2.0 protocol, RapidIO supports 3 transmission modes (1x, 2x and 4x) and 5 transmission rates (1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps and 6.25Gbps), and the combination of different transmission modes and different transmission rates can generate 15 transmission bandwidths.
However, in the practical application process of the conventional interface, in the 1x or 2x mode, only 1 or 2 of 4 LANEs are in data transmission, and the rest of LANEs are idle, which causes great bandwidth waste, and only one-to-one interconnection can be realized, and the transmission mode is few, so that the data transmission lacks flexibility.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides the dual-channel serial RapidIO interface which has a simple structure, can improve the interconnection flexibility and the transmission bandwidth and supports various transmission modes.
In order to solve the technical problems, the invention adopts the following technical scheme:
a dual-lane serial RapidIO interface supporting multiple transmission modes, comprising:
the controller is used for exchanging data with the inside of the system, generating a request packet and processing a response packet, and a path used for data transmission can be selected through a PortID field in a software programming register;
the logic layer and transmission layer circuit is used for being responsible for packet format conversion, packet caching, reordering, packet sending, packet retransmitting, detecting, receiving and caching the received packet of each path at the same time, and sending an input request to the controller;
the physical protocol layer is used for being responsible for CRC check, idle sequence generation, transmission flow control and error management;
the PCS layer is used for synchronizing the received data on each LANE, decoding the received data by 8B/10B, and performing multichannel alignment and link width initialization according to the link transmission condition on each channel; distributing data to be sent of a physical layer to each channel according to the link initialization width, and sending the data after 8B/10B coding;
the SerDes unit is used for performing data conversion between the parallel code group of the PCS layer and the link serial code stream to complete the function defined by the PMA layer in the RapidIO protocol;
and the cross switch is positioned between the PCS layer and the SerDes and used for interconnecting the channels of the PCS layer and the SerDes according to the channel mode.
As a further improvement of the invention: the logic layer plays a role in packet backup and relieving the difference between the transmission rate of a physical link and the transmission rate inside the system, for double-channel transmission, two channels share the logic layer cache, 32 independent caches are used for realizing output cache and input cache, 16 blocks of the output cache and the input cache are respectively used for reserving a private storage space for each channel, and a storage space is reserved for each priority packet.
As a further improvement of the invention: the logic layer accesses a specific cache block through a write address identifier and a read address identifier, and at the same time, the two paths access the cache block only and are different from each other; two paths belong to completely independent physical links, the operations of sending, reordering, retransmitting and the like of packets need to be carried out according to respective actual transmission conditions, a high-priority packet on one path cannot block the transmission of a low-priority packet on the other path, and two independent packet sending/reordering controllers are adopted to respectively control the packet transmission of the path 0 and the path 1.
As a further improvement of the invention: according to the transmission mode classification of the dual-channel RapidIO, the channel 0 needs to be subjected to dual-channel and four-channel alignment and 1x/2x/4x initialization, and the channel 1 needs to be subjected to dual-channel alignment and 1x/2x initialization; when RapidIO works in the single-path mode, the PCS layer is only controlled by a path 0; when RapidIO works in a double-channel mode, the RapidIO is controlled by a channel 0 and a channel 1 together; the two paths have respective lane alignment state machines and link initialization state machines.
As a further improvement of the invention: the controller respectively responds to data transmission on the two paths by using the two responders, so that the responses of the controller to the transmission on the two paths are not interfered with each other.
As a further improvement of the invention:
the crossbar is used to implement 14 transmission modes: a single channel-1 x-LANE0, a single channel-1 x-LANE1, a single channel-1 x-LANE2, a single channel-1 x-LANE3, a single channel-2 x-LANE0-LANE1, a single channel-2 x-LANE2-LANE3, a single channel-4 x-LANE0-LANE1-LANE2-LANE3, a double channel-1 x-LANE0-LANE1, a double channel-1 x-LANE0-LANE2, a double channel-1 x-LANE2-LANE 2, a double channel-2 x-LANE2-LANE 2-LANE 2-LANE 2.
As a further improvement of the invention: a path 0 and a path 1 in an output channel module of the logic layer are completely independent transmission links, and the path 0 and the path 1 can access the cache simultaneously; the output channel feeds back the occupation condition of the cache to the controller, and the controller distributes the available packet to the output channel for packet format conversion, packet head processing, TID distribution and cache writing; the packet sending/rearranging controller selects the packet with the highest priority to carry out packet assembly and cutting, and then sends the packet into the interface FIFO, and the request packet with response also needs to send the packet head into the input response Buffer for caching; when receiving the packet confirmation signal, releasing the buffer space occupied by the packet, and when receiving the packet non-reception signal or the packet retransmission signal, retransmitting the packet.
As a further improvement of the invention: the allocation schemes of the input response buffers and the input cache in the logic layer are completely the same, 16 input response buffers are divided into two parts, a private storage area is reserved for each access, and the two accesses share a public storage area; when a certain path needs to send a request packet with response, the public storage area is occupied first, and the private storage area is occupied after the public storage area is full; when both are full, packet transmission is suspended until there is an input response Buffer available.
As a further improvement of the invention: two paths in the input channel of the logic layer separate a packet header and data from a received data stream, buffer the data, analyze and process the packet header and detect errors; if the false packet header is detected, releasing the cache space occupied by the packet and updating the value of the error management register; if a valid packet header is detected, serializing the packet header; after the packet head passes through the processing module, writing the correct packet head into a packet head cache, and sending an input request and the address identifier of the packet to the controller by the ULI interface; and after receiving the response of the controller, reading the corresponding packet header and data from the packet header cache and the data cache according to the response pointer, and sending the packet header and the data to the controller to finish data transmission.
As a further improvement of the invention: when RapidIO works in a single-path mode, the PCS layer is only controlled by a path 0; when RapidIO works in a dual-channel 2x mode, a channel 0 initializes and caches data of LANE0 and LANE1 according to received data of LANE0 and LANE1, output data is distributed to LANE0 and LANE1 to be sent, and correspondingly, a channel 1 performs the same operation according to the received data of LANE2 and LANE 3; when RapidIO works in a dual-channel 1x mode, due to the existence of the cross switch, the channel 0 only needs to initialize according to the received data of the LANE0, buffer the data of the LANE0, distribute the output data to the LANE0 and send the output data, and correspondingly, the channel 1 carries out the same operation according to the received data of the LANE 1.
Compared with the prior art, the invention has the advantages that: the dual-channel serial RapidIO interface supporting multiple transmission modes has the advantages of simple structure, easy realization and wide application range, 14 transmission modes are realized through the configurable cross switch of the PCS layer, and the dual-channel serial RapidIO interface can be simultaneously interconnected with two serial RapidIO interfaces. The invention can effectively improve the interconnection flexibility and transmission bandwidth of the RapidIO system.
Drawings
Fig. 1 is a schematic of the topology of the present invention.
FIG. 2 is a block diagram of a logic layer output channel module in a specific application example of the present invention.
FIG. 3 is a schematic diagram of a logic layer output channel buffer allocation scheme in an embodiment of the present invention.
FIG. 4 is a schematic diagram of an organization structure of a logical layer output channel bank in a specific application example of the present invention.
Fig. 5 is a schematic diagram of an input response Buffer and an input Buffer allocation scheme in an embodiment of the present invention.
FIG. 6 is a schematic diagram of a logic layer input channel module in a specific application example of the present invention.
FIG. 7 is a diagram illustrating the read/write control of the logical layer input channel bank in an embodiment of the present invention.
FIG. 8 is a block diagram of PCS layer modules in an example embodiment of the present invention.
Fig. 9 is a transmission mode allocation table in a specific application example of the present invention.
FIG. 10 is a cross-point control table in an example embodiment of the present invention.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
The dual-channel serial RapidIO interface supporting multiple transmission modes is a dual-channel transmission scheme based on a RapidIO2.0 protocol, can realize one-to-two interconnection of RapidIO equipment on the basis of having the characteristics of low delay, high bandwidth and high expansibility of standard serial RapidIO, and has higher transmission flexibility and bandwidth utilization rate.
As shown in fig. 1, the dual-channel serial RapidIO interface supporting multiple transmission modes of the present invention includes:
the controller is used for exchanging data with the inside of the system, generating a request packet and processing a response packet, and a path used for data transmission can be selected through a PortID field in a software programming register; according to the characteristics of dual-channel transmission, two responders are used for respectively responding to data transmission on two channels, so that the responses of the controller to the transmission on the two channels are not interfered with each other.
And the logic layer and transmission layer circuit is used for taking charge of packet format conversion, packet caching, reordering, packet sending, packet retransmitting and the like, simultaneously detecting, receiving and caching the received packets of each path and sending input requests to the controller. The logic layer cache plays a role in packet backup and relieving the difference between a physical link and the transmission rate inside the system, for double-channel transmission, two channels share the logic layer cache, 32 independent caches are used for realizing output cache and input cache, each 16 blocks of the output cache and the input cache are reserved, a private storage space is reserved for each channel, a storage space (8 priority levels in total and supporting CRF (random number) bits) is reserved for each priority level packet, the logic layer accesses a specific cache block through a write address identifier and a read address identifier, and the two channels access the cache blocks uniquely and differently at the same time; two paths belong to completely independent physical links, the operations of sending, reordering, retransmitting and the like of packets need to be carried out according to respective actual transmission conditions, and a high-priority packet on one path cannot block the transmission of a low-priority packet on the other path, so that two independent packet sending/reordering controllers are used for respectively controlling the packet transmission of the path 0 and the path 1; in the input channel logic, a path 0 and a path 1 respectively have an input packet head detector and a data detector; in the output channel logic, the channel 0 and the channel 1 respectively have an independent packet assembly controller, assemble and cut respective packet headers and data into 64-bit data streams, write the 64-bit data streams into respective interface FIFO, and wait for the physical layer to send the data streams; and the channel 0 and the channel 1 share an input/output packet head processing related module and a TID generator, and the circuit area consumption is reduced by multiplexing the modules between two channels.
And the physical protocol layer belongs to a part of the RapidIO physical layer and is used for being responsible for CRC check, idle sequence generation, transmission flow control and error management. Path 0 and path 1 have their own physical protocol layer logic; path 0 and path 1 are completely different physical links connected, and therefore require separate physical protocol layers to maintain the physical links.
And the PCS layer belongs to a part of a RapidIO physical layer. The PCS layer is used for synchronizing the received data on each LANE, decoding the received data by 8B/10B, and performing multichannel alignment and link width initialization according to the link transmission condition on each channel; and distributing the data to be transmitted of the physical layer to each channel according to the link initialization width, and transmitting the data after 8B/10B coding.
Referring to fig. 9, according to the transmission mode classification of the dual-channel RapidIO, the channel 0 needs to perform dual-channel and four-channel alignment and 1x/2x/4x initialization, and the channel 1 needs to perform dual-channel alignment and 1x/2x initialization. When RapidIO works in the single-path mode, the PCS layer is only controlled by a path 0; when RapidIO is operated in the two-channel mode, the RapidIO is controlled by the channel 0 and the channel 1 together. The two paths have respective lane alignment state machines and link initialization state machines.
And the SerDes unit is used for performing data conversion between the parallel code group of the PCS layer and the link serial code stream to complete the function defined by the PMA layer in the RapidIO protocol.
The cross switch is positioned between the PCS layer and the SerDes and used for interconnecting channels of the PCS layer and the SerDes according to a channel mode; namely, the 4LANE of the PCS layer and the 4LANE of the SerDes are arbitrarily interconnected. With reference to fig. 10, 14 transmission modes are implemented in total in a specific application: a single channel-1 x-LANE0, a single channel-1 x-LANE1, a single channel-1 x-LANE2, a single channel-1 x-LANE3, a single channel-2 x-LANE0-LANE1, a single channel-2 x-LANE2-LANE3, a single channel-4 x-LANE0-LANE1-LANE2-LANE3, a double channel-1 x-LANE0-LANE1, a double channel-1 x-LANE0-LANE2, a double channel-1 x-LANE2-LANE 2, a double channel-2 x-LANE2-LANE 2-LANE 2-LANE 2. The input/output crossbar interfaces the 4LANE of the PCS layer with the 4LANE of the SerDes according to fig. 10.
From the above, in the present invention, the physical protocol layer, PCS layer and SerDes belong to the same physical layer in RapidIO protocol. Lane0 and lane1 require respective response controllers, packet transmit/reorder controllers, incoming packet detection, physical protocol layer circuits. For the PCS layer, a channel 0 needs to be subjected to double-channel and four-channel alignment and 1x/2x/4x initialization, and a channel 1 needs to be subjected to double-channel alignment and 1x/2x initialization, so that double channels have respective channel alignment state machines and link initialization state machines. The double-channel serial RapidIO high-speed interface supporting multiple transmission modes can be realized through the technical scheme. The technical scheme can solve the problems of bandwidth waste and poor transmission flexibility of the traditional single-channel RapidIO.
As shown in fig. 2, which is a block diagram of a logic layer output channel module in a specific application example of the present invention, path 0 and path 1 are completely independent transmission links, so that the logics related to the physical layer interface are independent from each other; through optimization of the cache space, way 0 and way 1 may access the cache simultaneously. The output channel feeds back the occupation condition of the cache to the controller, and the controller distributes the available packet to the output channel for packet format conversion, packet head processing, TID distribution and cache writing; the packet sending/rearranging controller selects the packet with the highest priority to carry out packet assembly and cutting, and then sends the packet into the interface FIFO, and the request packet with response also needs to send the packet head into the input response Buffer for caching so as to ensure that the correct response can be received; when receiving the packet confirmation signal, releasing the buffer space occupied by the packet, and when receiving the packet non-reception signal or the packet retransmission signal, retransmitting the packet.
Fig. 3 is a schematic diagram illustrating a logic layer output channel buffer allocation scheme in an embodiment of the present invention. Divide 16 blocks of output buffer into 3 parts: private storage area, public storage area, and priority storage area. The number of the priority storage areas is 8, the number of the packets (CRF bits are valid) with 8 priorities are RapidIO, each packet with the priority has a priority storage area, and the packet with the higher priority can occupy the storage area with the lower priority; the public storage area and the priority storage area belong to a dual-path shared storage area. Each path is provided with a private storage area, each path can only occupy the private storage area belonging to the path, so that the output cache at least reserves a storage space for each path, when the physical link of one path is blocked to cause all output packets to be blocked in the cache, the other path is provided with at least one private space which can cache the packets and send the packets. For each channel to-be-sent packet, the sequence of occupied cache space is a current-level priority storage area, a public storage area, a low-priority storage area and a private storage area, and the packet with the priority of N can occupy at most N +8 storage spaces.
Fig. 4 is a diagram illustrating an organization of a logical layer output channel bank in an embodiment of the invention. The output cache is divided into a data cache and a packet header cache, the data cache comprises 16 blocks (each block comprises 256 bytes), the packet header cache comprises 16 registers, and the data cache and the packet header cache are in one-to-one correspondence. The output channel accesses a specific cache block through a write address identifier and a read address identifier (the address identifier is N which represents that the Nth block data cache and the Nth packet header cache are currently accessed and are provided by the cache pointer manager and the rearrangement controller). By allocating the cache space, it can be ensured that the read address identifier and the write address identifier of the way 0 and the way 1 are unique and different from each other at any time. Each channel reads data from a corresponding cache block according to the read address identification provided by its own reorder controller. Each cache block records a write address at the end of a packet when data is written, and when the read address is equal to the write address when data is read, the packet reading is considered to be ended. The bank organization of the input channels is the same as the output channels.
Fig. 5 is a schematic diagram illustrating an allocation scheme of input response buffers and input buffers in a specific application example of the present invention. The input response Buffer and the input Buffer are distributed in the same scheme. The 16 input response buffers are divided into two parts, a private storage area is reserved for each path, and the two paths share a public storage area. When a certain path needs to send a request packet with response, the public storage area is occupied first, and the private storage area is occupied after the public storage area is full; when both are full, packet transmission is suspended until there is an input response Buffer available. For the access 0, the condition that the input response Buffer is full is that the private storage area is full and the public storage area is full; for the access 1, the condition that the input response Buffer is full is that the private storage area is full and the full occupation quantity of the public storage area is 13; therefore, the method can ensure that a plurality of paths cannot occupy the only one cache resource at the same time. The input buffer is occupied in a similar way, and when the input buffer of a certain path is full, the packet is rejected and a packet retransmission control symbol is sent out.
Fig. 6 is a block diagram of a logic layer input channel module in a specific application example of the present invention. The two paths separate the packet header and the data from the received data stream, buffer the data, analyze and process the packet header and detect errors; if the false packet header is detected, releasing the cache space occupied by the packet and updating the value of the error management register; if a valid packet header is detected, serializing the packet header (considering that the packet header may be detected in the same clock cycle by the path 0 and the path 1, and the link transmission rate determines that the time interval of detecting two continuous packet headers in the same path in the dual-path mode is more than or equal to two clock cycles, and serializing the packet headers of the path 0 and the path 1 by using the interval of the two clock cycles); after the packet head passes through the processing module, writing the correct packet head into a packet head cache, and sending an input request and the address identifier of the packet to the controller by the ULI interface; and after receiving the response of the controller, reading the corresponding packet header and data from the packet header cache and the data cache according to the response pointer, and sending the packet header and the data to the controller to finish data transmission. In this process, the occupation condition of the input buffer is fed back to the buffer management module in the physical layer, so that the physical layer can select to receive the packet or retransmit the packet.
Fig. 7 is a schematic diagram illustrating read/write control of a logical layer input channel bank in an embodiment of the present invention. The input buffer has the same composition as the output buffer, and is divided into a packet header and a data buffer. The data cache is divided into 16 storage blocks, each cache block has an independent read-write control path, and each data cache corresponds to one packet header in the input packet header cache. The write path of the N-th block cache is selected from the write signals and write data of the two paths according to the PortID, the PortID is specified when the cache is allocated, and if the N-th block cache is allocated to the path 0, the PortID of the N-th block cache is 4' b 0001; if the nth block cache is allocated to way 1, the PortID of the nth block cache is 4' b 0010; default PortID 4' b 0000; and the read port judges whether data reading is needed or not according to the read address identifier, and when the read address identifier is equal to N, the read port indicates that the data is required to be read from the cache of the block and is sent to the controller.
FIG. 8 is a block diagram of PCS layer modules in a specific application example of the present invention. When RapidIO works in the single-path mode, the PCS layer is only controlled by a path 0; when RapidIO works in a dual-channel 2x mode, a channel 0 initializes and caches data of LANE0 and LANE1 according to received data of LANE0 and LANE1, output data is distributed to LANE0 and LANE1 to be sent, and correspondingly, a channel 1 performs the same operation according to the received data of LANE2 and LANE 3; when RapidIO works in a dual-channel 1x mode, due to the existence of the cross switch, the channel 0 only needs to initialize according to the received data of the LANE0, buffer the data of the LANE0, distribute the output data to the LANE0 and send the output data, and correspondingly, the channel 1 carries out the same operation according to the received data of the LANE 1.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (10)
1. A dual-channel serial RapidIO interface supporting multiple transmission modes is characterized by comprising:
the controller is used for exchanging data with the inside of the system, generating a request packet and processing a response packet, and a path used for data transmission can be selected through a PortID field in a software programming register;
the logic layer and transmission layer circuit is used for being responsible for packet format conversion, packet caching, reordering, packet sending, packet retransmitting, detecting, receiving and caching the received packet of each path at the same time, and sending an input request to the controller;
the physical protocol layer is used for being responsible for CRC check, idle sequence generation, transmission flow control and error management;
the PCS layer is used for synchronizing the received data on each LANE, decoding the received data by 8B/10B, and performing multichannel alignment and link width initialization according to the link transmission condition on each channel; distributing data to be sent of a physical layer to each channel according to the link initialization width, and sending the data after 8B/10B coding;
the SerDes unit is used for performing data conversion between the parallel code group of the PCS layer and the link serial code stream to complete the function defined by the PMA layer in the RapidIO protocol;
and the cross switch is positioned between the PCS layer and the SerDes and used for interconnecting the channels of the PCS layer and the SerDes according to the channel mode.
2. The dual-channel serial RapidIO interface supporting multiple transmission modes according to claim 1, wherein the logic layer plays a role in packet backup and relieving the difference between the transmission rates of the physical link and the system, for dual-channel transmission, two channels share the logic layer cache, 32 independent caches are used for realizing output cache and input cache, 16 blocks are respectively used for the output cache and the input cache, a private storage space is reserved for each channel, and a storage space is reserved for each priority packet.
3. The dual-channel serial RapidIO interface supporting multiple transmission modes according to claim 2, wherein the logic layer accesses a specific cache block by writing address identifier and reading address identifier, and at the same time, the two channels access the cache block uniquely and differently from each other; two paths belong to completely independent physical links, the operations of sending, reordering, retransmitting and the like of packets need to be carried out according to respective actual transmission conditions, a high-priority packet on one path cannot block the transmission of a low-priority packet on the other path, and two independent packet sending/reordering controllers are adopted to respectively control the packet transmission of the path 0 and the path 1.
4. The dual-channel serial RapidIO interface supporting multiple transmission modes according to claim 3, wherein according to the transmission mode classification of the dual-channel RapidIO, the channel 0 needs to perform dual-channel and four-channel alignment and 1x/2x/4x initialization, and the channel 1 needs to perform dual-channel alignment and 1x/2x initialization; when RapidIO works in the single-path mode, the PCS layer is only controlled by a path 0; when RapidIO works in a double-channel mode, the RapidIO is controlled by a channel 0 and a channel 1 together; the two paths have respective lane alignment state machines and link initialization state machines.
5. The dual-channel serial RapidIO interface supporting multiple transmission modes according to any one of claims 1-4, wherein two responders are used in the controller to respond to data transmission on two channels respectively, so that the responses of the controller to the transmission on the two channels do not interfere with each other.
6. The dual-path serial RapidIO interface supporting multiple transmission modes according to any of claims 1-4,
the crossbar is used to implement 14 transmission modes: a single channel-1 x-LANE0, a single channel-1 x-LANE1, a single channel-1 x-LANE2, a single channel-1 x-LANE3, a single channel-2 x-LANE0-LANE1, a single channel-2 x-LANE2-LANE3, a single channel-4 x-LANE0-LANE1-LANE2-LANE3, a double channel-1 x-LANE0-LANE1, a double channel-1 x-LANE0-LANE2, a double channel-1 x-LANE2-LANE 2, a double channel-2 x-LANE2-LANE 2-LANE 2-LANE 2.
7. The dual-channel serial RapidIO interface supporting multiple transmission modes according to any one of claims 1 to 4, wherein channel 0 and channel 1 in the output channel module of the logic layer are completely independent transmission links, and channel 0 and channel 1 can access the buffer simultaneously; the output channel feeds back the occupation condition of the cache to the controller, and the controller distributes the available packet to the output channel for packet format conversion, packet head processing, TID distribution and cache writing; the packet sending/rearranging controller selects the packet with the highest priority to carry out packet assembly and cutting, and then sends the packet into the interface FIFO, and the request packet with response also needs to send the packet head into the input response Buffer for caching; when receiving the packet confirmation signal, releasing the buffer space occupied by the packet, and when receiving the packet non-reception signal or the packet retransmission signal, retransmitting the packet.
8. The dual-channel serial RapidIO interface supporting multiple transmission modes according to any one of claims 1 to 4, wherein the input response buffers in the logic layer are completely the same as the input Buffer allocation scheme, the 16 input response buffers are divided into two parts, a private memory area is reserved for each channel, and the two channels share a public memory area; when a certain path needs to send a request packet with response, the public storage area is occupied first, and the private storage area is occupied after the public storage area is full; when both are full, packet transmission is suspended until there is an input response Buffer available.
9. The dual-channel serial RapidIO interface supporting multiple transmission modes according to any one of claims 1 to 4, wherein two channels in the input channel of the logic layer separate the packet header and data from the received data stream, buffer the data and analyze and process the packet header, detect errors; if the false packet header is detected, releasing the cache space occupied by the packet and updating the value of the error management register; if a valid packet header is detected, serializing the packet header; after the packet head passes through the processing module, writing the correct packet head into a packet head cache, and sending an input request and the address identifier of the packet to the controller by the ULI interface; and after receiving the response of the controller, reading the corresponding packet header and data from the packet header cache and the data cache according to the response pointer, and sending the packet header and the data to the controller to finish data transmission.
10. The dual-path serial RapidIO interface supporting multiple transmission modes according to any one of claims 1-4, characterized in that when RapidIO is operated in a single path mode, the PCS layer is controlled only by path 0; when RapidIO works in a dual-channel 2x mode, a channel 0 initializes and caches data of LANE0 and LANE1 according to received data of LANE0 and LANE1, output data is distributed to LANE0 and LANE1 to be sent, and correspondingly, a channel 1 performs the same operation according to the received data of LANE2 and LANE 3; when RapidIO works in a dual-channel 1x mode, due to the existence of the cross switch, the channel 0 only needs to initialize according to the received data of the LANE0, buffer the data of the LANE0, distribute the output data to the LANE0 and send the output data, and correspondingly, the channel 1 carries out the same operation according to the received data of the LANE 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911012232.8A CN110781112A (en) | 2019-10-23 | 2019-10-23 | Dual-channel serial RapidIO interface supporting multiple transmission modes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911012232.8A CN110781112A (en) | 2019-10-23 | 2019-10-23 | Dual-channel serial RapidIO interface supporting multiple transmission modes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110781112A true CN110781112A (en) | 2020-02-11 |
Family
ID=69386574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911012232.8A Pending CN110781112A (en) | 2019-10-23 | 2019-10-23 | Dual-channel serial RapidIO interface supporting multiple transmission modes |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110781112A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111258945A (en) * | 2020-02-20 | 2020-06-09 | 广州思林杰网络科技有限公司 | Embedded system communication interface and communication method |
| CN111600813A (en) * | 2020-05-13 | 2020-08-28 | 中国人民解放军国防科技大学 | Multi-mode interconnection interface controller for converged network |
| CN112148651A (en) * | 2020-10-10 | 2020-12-29 | 中国人民解放军国防科技大学 | Enhanced rapidio interconnection device and equipment |
| TWI735199B (en) * | 2020-04-08 | 2021-08-01 | 慧榮科技股份有限公司 | Apparatus and method for segmenting a data stream of a physical layer |
| CN113312304A (en) * | 2021-06-04 | 2021-08-27 | 海光信息技术股份有限公司 | Interconnection device, mainboard and server |
| TWI818274B (en) * | 2020-04-08 | 2023-10-11 | 慧榮科技股份有限公司 | Apparatus and method for segmenting a data stream of a physical layer |
| US11829759B2 (en) | 2020-04-08 | 2023-11-28 | Silicon Motion, Inc. | Apparatus and method for segmenting a data stream of a physical layer |
| CN118300908A (en) * | 2024-06-06 | 2024-07-05 | 芯云晟(杭州)电子科技有限公司 | Multi-channel connector of serial-parallel transceiver and multi-channel connecting chip of serial-parallel transceiver |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394678A (en) * | 2008-11-07 | 2009-03-25 | 烽火通信科技股份有限公司 | Serialization/de-serialization interface module generally used in GEPON/GPON |
| CN101604541A (en) * | 2009-06-24 | 2009-12-16 | 北京理工大学 | Two-channel digital radio-frequency memory board |
| CN106506104A (en) * | 2016-12-01 | 2017-03-15 | 中国电子科技集团公司第四十研究所 | A kind of portable wireless channel simulation device |
-
2019
- 2019-10-23 CN CN201911012232.8A patent/CN110781112A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394678A (en) * | 2008-11-07 | 2009-03-25 | 烽火通信科技股份有限公司 | Serialization/de-serialization interface module generally used in GEPON/GPON |
| CN101604541A (en) * | 2009-06-24 | 2009-12-16 | 北京理工大学 | Two-channel digital radio-frequency memory board |
| CN106506104A (en) * | 2016-12-01 | 2017-03-15 | 中国电子科技集团公司第四十研究所 | A kind of portable wireless channel simulation device |
Non-Patent Citations (2)
| Title |
|---|
| 舒志兴: "RapidIO高速接口物理编码子层的设计与验证", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 郭欣童 等: "支持多种传输模式的双通路串行RapidIO设计与实现", 《计算机工程与科学》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111258945A (en) * | 2020-02-20 | 2020-06-09 | 广州思林杰网络科技有限公司 | Embedded system communication interface and communication method |
| TWI735199B (en) * | 2020-04-08 | 2021-08-01 | 慧榮科技股份有限公司 | Apparatus and method for segmenting a data stream of a physical layer |
| TWI818274B (en) * | 2020-04-08 | 2023-10-11 | 慧榮科技股份有限公司 | Apparatus and method for segmenting a data stream of a physical layer |
| US11829759B2 (en) | 2020-04-08 | 2023-11-28 | Silicon Motion, Inc. | Apparatus and method for segmenting a data stream of a physical layer |
| CN111600813A (en) * | 2020-05-13 | 2020-08-28 | 中国人民解放军国防科技大学 | Multi-mode interconnection interface controller for converged network |
| CN111600813B (en) * | 2020-05-13 | 2021-10-29 | 中国人民解放军国防科技大学 | Multi-mode interconnection interface controller for converged network |
| CN112148651A (en) * | 2020-10-10 | 2020-12-29 | 中国人民解放军国防科技大学 | Enhanced rapidio interconnection device and equipment |
| CN112148651B (en) * | 2020-10-10 | 2022-05-03 | 中国人民解放军国防科技大学 | Enhanced rapidio interconnection device and equipment |
| CN113312304A (en) * | 2021-06-04 | 2021-08-27 | 海光信息技术股份有限公司 | Interconnection device, mainboard and server |
| CN118300908A (en) * | 2024-06-06 | 2024-07-05 | 芯云晟(杭州)电子科技有限公司 | Multi-channel connector of serial-parallel transceiver and multi-channel connecting chip of serial-parallel transceiver |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110781112A (en) | Dual-channel serial RapidIO interface supporting multiple transmission modes | |
| US6393021B1 (en) | Integrated multiport switch having shared data receive FIFO structure | |
| KR101271245B1 (en) | Interconnection System | |
| US7522468B2 (en) | Serial memory interface | |
| US7061929B1 (en) | Data network with independent transmission channels | |
| US20080232387A1 (en) | Electronic Device and Method of Communication Resource Allocation | |
| JP2001524727A (en) | Low latency shared memory switch structure | |
| JP2006502642A (en) | Integrated circuit and method for establishing a transaction | |
| JPH10340243A (en) | Input/output data transfer system | |
| EP0882343A1 (en) | Serial data interface method and apparatus | |
| US20070110052A1 (en) | System and method for the static routing of data packet streams in an interconnect network | |
| US10387355B2 (en) | NoC interconnect with linearly-tunable QoS guarantees for real-time isolation | |
| US6975626B1 (en) | Switched network for low latency communication | |
| EP3326347B1 (en) | Method and system for usb 2.0 bandwidth reservation | |
| US7065580B1 (en) | Method and apparatus for a pipelined network | |
| CN1221919A (en) | System for interchanging data between data processor units having processors interconnected by common bus | |
| US6904046B2 (en) | Self-route multi-memory packet switch adapted to have an expandable number of input/output ports | |
| US20210409510A1 (en) | Transmitter and Receiver, Serializer and Deserializer and Methods for Transmitting and Receiving, Serializing and Deserializing | |
| US6470021B1 (en) | Computer network switch with parallel access shared memory architecture | |
| US7218638B2 (en) | Switch operation scheduling mechanism with concurrent connection and queue scheduling | |
| WO2023202294A1 (en) | Data stream order-preserving method, data exchange device, and network | |
| CN103516627A (en) | Method and apparatus for transmitting and receiving data packets in multi-chip communication | |
| JP2002281063A (en) | Packet switch and packet memory access method to be used for the same | |
| US20040151175A1 (en) | Transparent data format within host device supporting differing transaction types | |
| US7130302B2 (en) | Self-route expandable multi-memory packet switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200211 |