TWI735199B - Apparatus and method for segmenting a data stream of a physical layer - Google Patents

Abstract

An apparatus for diving a data stream, installed in a physical layer, includes: a data register and a boundary detector. The boundary detector is capable of detecting a boundary-lock pattern and a special symbol. The boundary detector detects the content of the data buffer, and when detecting a boundary-lock pattern or a special symbol, outputs a starting address that the boundary-lock pattern or the special symbol stored in the data buffer to an offset register for updating a value of the offset register, thereby enabling a stream divider to perform data-segment divisions according to a new value stored in the offset register. By additionally tracking the special symbol, the physical layer reduces time for correcting data-segment errors resulting from a reduced quantity of boundary-lock patterns sent by a host.

Description

Physical layer data stream cutting device and method

The invention relates to a storage device, in particular to a physical layer data stream cutting device and method.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host can provide any address for accessing the NOR flash memory device on the address pin, and promptly retrieve it from the data pin of the NOR flash memory device Obtain the data stored at that address. On the contrary, NAND flash memory devices are not random access, but serial access. NAND flash memory devices cannot access any random address like NOR flash memory devices. Instead, the master device needs to write serial bytes (bytes) into the NAND flash memory device to define the request The type of command (for example, read, write, erase, etc.), and the address used for this command. The address can point to a page (the smallest data block for writing in a flash memory device) or a block (the smallest data block for erasing in a flash memory device).

To meet the requirements of high-speed communication, the physical layer of the flash memory device may include a serializer/deserializer (Serializer/Deserializer, SerDes for short). SerDes is a pair of functional circuits to make up for the deficiencies of limited input/output. It provides data transmission on a single wire or differential pair, so that the input and output pins and the wiring between them can be minimized. In detail, the transmitting end converts low-speed parallel signals into high-speed serial signals, and transmits them to the receiving end through a single wire or a differential pair. However, in the SerDes environment, due to frequency difference or environmental factors, the Phase-Locked Loop PLL is released (Lose Lock), resulting in the insertion of unnecessary bits in the original data, or the loss of the original data Part of the bits. Therefore, the present invention provides a data stream cutting device and method to solve the above-mentioned problems.

In view of this, how to reduce or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

This specification provides an embodiment of a data stream cutting device at the physical layer, which is installed in the physical layer and includes a data register and a boundary detector. The boundary detector has the ability to detect the boundary lock mode and special symbols. It is used to detect the contents of the data register. When the data register contains the boundary lock mode or special symbols, it outputs the detected boundary lock mode or the special symbol in the data register. The start address of the special symbol is given to the offset register to update the value stored in the offset register, so that the stream splitter cuts the data segment in the data register according to the new value stored in the offset register.

This specification provides an embodiment of a data stream cutting method, executed by the physical layer, including: comparing each combination of n consecutive bit data in the data register and the boundary lock mode; comparing the consecutive n bit data in the data register Each combination and special symbol; and when any combination of n consecutive bits of data in the data register matches the boundary lock mode or special symbol, it is changed to be based on the boundary lock mode or the start bit of the special symbol in the data register Address the content in the data register to generate one or more fragments.

This specification provides an embodiment of another data stream cutting method, executed by the physical layer, including: when the previously cut data is decoded successfully, comparing each combination of n consecutive bit data in the data register with the boundary lock mode; when When the previously cut data fails to decode, compare each combination of n consecutive bits of data in the data register with special symbols; and when any combination of n consecutive bits of data in the data register matches the boundary lock mode or special symbols , Change to cut the content in the data register according to the boundary lock mode or the starting address of the special symbol in the data register to generate one or more fragments.

One of the advantages of the above embodiment is that by tracking special symbols more in the physical layer, the time required to correct data cutting errors when the host side reduces the boundary lock mode is reduced.

Other advantages of the present invention will be explained in more detail with the following description and drawings.

The following descriptions are preferred implementations for completing the invention, and their purpose is to describe the basic spirit of the invention, but not to limit the invention. The actual content of the invention must refer to the scope of the claims that follow.

It must be understood that the words "including" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operations, elements, and/or components, but they do not exclude the possibility of adding More technical features, values, method steps, job processing, components, components, or any combination of the above.

Words such as "first", "second", and "third" in the claims are used to modify the elements in the claims, not to indicate that there is a priority, prerequisite relationship, or an element Prior to another element, or the chronological order of execution of method steps, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being “connected” or “coupled” to another element, it can be directly connected or coupled to other elements, and intervening elements may appear. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other terms used to describe the relationship between elements can also be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent" and so on.

Refer to Figure 1. The electronic device includes a host side 110, a controller 130, and a storage device 150, and the controller 130 and the storage device 150 can be collectively referred to as a device side. The electronic device can be a personal computer, a laptop computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, and other electronic products. The interface of the host side 110 (not shown in FIG. 1) and the host interface (Host Interface) 171 of the controller 130 can use Universal Flash Storage (UFS) and Universal Serial Bus (USB) , Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E) and other communication protocols communicate with each other. The storage interface (Storage Interface) 139 of the controller 130 and the flash memory interface of the storage device 150 can communicate with each other through the Double Data Rate (DDR) communication protocol, for example, Open NAND Flash Interface (ONFI), Double data rate switch (DDR Toggle) or other interface communication protocol. The controller 130 includes a processing unit 131 for receiving host commands from the host terminal 110 through a physical layer (PHY) 170 and a media access control layer (Media Access Control, MAC Layer) 133, such as reading, writing, Wipe orders, etc. The processing unit 131 can be implemented in a variety of ways, such as using general-purpose hardware (for example, a single processor, multi-processors with parallel processing capabilities, graphics processors, or other processors with computing capabilities), and is executing software and/or Provides the specified function when the firmware is instructed. The controller 130 further includes a static random access memory (SRAM) 135, which is used to configure the space as a data buffer to store user data that the host write command wants to write to the storage device 150, and the host read command instructs the slave The user data read by the storage device 150 and the data needed during execution, such as variables, data tables, host-to-flash comparison table (Host-to-Flash, H2F Table), flash-to-host comparison table (Flash-to -Host, F2H Table) etc. The controller 130 further includes a NAND Flash Controller (NFC) 138, which provides functions required in the process of accessing the storage device 150, such as a command sequencer (Command Sequencer), and a low density parity check (Low Density Parity Check, LDPC) and so on. The processing unit 131 instructs the storage device 150 to perform data reading, writing, and erasing operations through the NFC 138 and the storage interface 139 according to host commands.

The storage device 150 includes a storage unit 153, which provides a large amount of storage space, usually hundreds of gigabytes (GB) or even several terabytes (Terabytes, TB) for storing large amounts of User data, such as high-resolution images, videos, etc. The storage unit 153 includes a control circuit and a memory array. The memory cells in the memory array can include single level cells (SLCs), multiple level cells (MLCs), and triple level cells. Cells, TLCs), Quad-Level Cells (QLCs) or any combination of the above. The processing unit 131 writes user data to the designated address (destination address) in the storage device 150 (specifically, the storage unit 153) through the storage interface 139, and from the designated address (source address) in the storage device 150 ) Read user data. The storage interface 139 uses several electronic signals to coordinate data and command transmission between the controller 130 and the storage device 150, including a data line, a clock signal, and a control signal. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transfer Chip Enable (CE), Address Latch Enable (ALE), and command extraction to enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to FIG. 2, the flash memory interface 151 may include four I/O channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3, and each channel is connected to four NAND flash memory modules, for example, channel CH#0 is connected NAND flash memory modules 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory module can be packaged as an independent die. The NAND flash memory controller 138 can send one of the enabling signals CE#0 to CE#3 through the back-end interface 139 and the flash memory interface 151 to enable the NAND flash memory modules 153#0 to 153#3, 153#4 to 153# 7. 153#8 to 153#11, or 153#12 to 153#15, then read user data from the enabled NAND flash memory module in parallel, or write user data to the enabled NAND flash memory Module.

The physical layer 170 of the controller 130 can be set to an 8b/10b, 64b/66b or 128b/130b serializer/deserializer (Serializer/Deserializer, SerDes for short) environment. However, frequency difference or environmental factors will cause the Phase-Locked Loop PLL to lose lock, causing unnecessary bits to be inserted into the original data transmitted by the host 110, or the host 110 is lost. Some bits in the original data sent. When the controller 130 is mounted on a mobile phone, the interference of the environment is more serious. For example, the surge generated by the user operating the touch screen affects the analog circuit in the physical layer 170 (also known as the analog physical layer A- PHY), which makes the phase-locked loop unlocked happen more frequently. The analog physical layer contains a serializer, which is used to map each data segment into a code that uses more bits before serializing the data, such as mapping an 8, 64 or 128-bit segment to 10, 66, or 130. Bit code. For example, referring to FIG. 3A, the host side 110 transmits data 310 to the physical layer 170 in the controller 130 through the host interface 171, including the data stream "b01100001101010000011". However, due to the unlocking of the phase-locked loop, the physical layer 170 receives the error data 330 as shown in FIG. 3B or the error data 350 as shown in FIG. 3C. The data stream 330 in FIG. 3B includes the bit "b11" 330p that does not exist in the original data 310, and the original bit "b00" 350q in the original data 310 is missing in the data stream 350 in FIG. 3C. Since the original data stream is composed of a series of fragments of a fixed size (for example, 10, 66, 130 bits, or other numbers of bits), incorrectly inserted or missing bits will cause errors in subsequent data cutting. For example, the original data stream 310 shown in FIG. 3A should be cut into two 10-bit segments "b0110000110" and "b1010000011". However, the data stream 330 shown in FIG. 3B cuts out two incorrect 10-bit segments "b0110011001" and "b1010100000". The data stream 350 shown in FIG. 3C cuts out two incorrect 10-bit segments "b0110011010" and "b10000011xx".

In order to solve the cutting error caused by the unlocking of the phase-locked loop as described above, in some implementations of the 8b/10b SerDes environment, the host 110 may periodically transmit a boundary lock pattern (Boundary-lock Pattern), for example, the cluster of UFS Head of Burst HOB (also known as MK0 or K.28.5 symbol), etc., so that the physical layer 170 can re-determine the boundary of each segment (Boundary) by tracking the boundary lock mode of the information stream transmitted from the host interface 171 And cut accordingly. In some implementations of the 128b/130b SerDes environment, the host 110 may periodically transmit the boundary lock mode, such as the PCI-E Comma Character (also known as K28.5 symbol), etc., to allow the physical layer 170 determines and cuts the boundary of the segment. However, in order to obtain a better transmission rate, the host side 110 may reduce the number of transmissions in the boundary lock mode, which causes the physical layer 170 to take longer to correct data cutting errors.

In order to improve the shortcomings of the above-mentioned implementation, in an 8b/10b SerDes environment, an embodiment of the present invention proposes a physical layer circuit that not only tracks the boundary lock mode in the information stream from the host interface 171 during the effective packet transmission period, It also tracks the special symbols in the information stream from the host interface 171 during the idle period (Idle), such as the fill element of UFS (FILLER, also known as K.28.1 symbol). Referring to FIG. 4, take the host 110 writing user data as an example. Under normal circumstances, the host terminal 110 sends the SOB 410 and then sends the host write command CMD 420 to enable the controller 130 to cut the data stream correctly. Then, after receiving the Acknowledgement ACK 430 sent by the controller 130, the host terminal 110 starts to transmit the user data DAT 460. Before starting to send user data, the host 110 sends an SOB 410 to enable the controller 130 to cut the data stream correctly. The host write command CMD 420 and user data 460 can be referred to as a valid packet. Those skilled in the art understand that valid packets also include host management commands, other host input/output commands, parameters, and other information that can be used by the protocol layer (Protocol Layer). The period during which valid packets are transmitted and associated necessary control symbols (such as boundary lock mode, synchronization mode SYN, etc.) is called the effective packet transmission period. The period after the host write command CMD 420 is sent to the next SOB 410 is called the idle period t _IDLE . _{During the idle period t IDLE} waiting for the confirmation 430 from the device side, the host side 110 can continuously transmit the filling element FIL 450 to the device side. Please refer to Table 1 for details of UFS's burst head and filler element: Table 1 enter RD = -1 RD = +1 name symbol HGF EDCBA abcdei fghj abcdei fghj K.28.1 001 11100 001111 1001 110000 0110 FILLER K.28.5 101 11100 001111 1010 110000 0101 MARKER0

In the 128b/130b SerDes environment, the physical layer circuit not only tracks the boundary lock mode during data transmission, but also tracks a special symbol, such as the PCI-E Fast Training Sequence (Fast Training Sequence FTS, also known as K28.1 symbol). For details of PCI-E comma and fast training sequence, please refer to Table 2: Table 2 coding symbol name describe K28.1 FTS Fast training sequence Leave L0s to L0 in the ordered data set K28.5 COM comma Used for plane and link initialization and management Those skilled in the art understand that FTS is used to be inserted before valid data. By tracking more symbols, the physical layer 170 can also correct data cutting errors as soon as possible when the host side 110 lengthens the period of transmitting the synchronization mode.

Referring to FIG. 1, the physical layer 170 includes the host interface 171 described above for receiving host commands, parameters, and user data from the host terminal 110. Taking the 8b/10b SerDes environment as an example, the host commands, parameters, and user data sent by the host terminal 110 are encoded in units of 10 bits. The physical layer 170 further includes a data register 173, a boundary detector 174, a stream splitter 175, an offset register (Offset Register) 176, and a decoder 177. The data register 173 can store 20 bits of data received through the host interface 171. The offset register 176 records the boundary of the data segment (Boundary, which may also be referred to as the starting address of the cutting). The stream splitter 175 cuts the data bits in the data register 173 into one or more segments according to the value of the offset register 176 and outputs them to the decoder 177. 5A and 5B respectively show the data segment cutting situation when the offset register 173 records 0 and 2 according to an embodiment of the present invention. The data register 173 stores 20-bit data 510 at time t1, and then stores the next 20-bit data 530 at time t2.

Referring to FIG. 5A, for example, when the offset register 176 records 0, the stream splitter 175 can treat the 0th to 9th bits in the data 510 as the fragment Fn at the time point t1, and the first to the data 510 10 to 19 bits are regarded as the segment Fn+1, and the data of the two segments are output to the decoder 177. The stream splitter 175 can treat the 0th to 9th bits in the data 530 as the fragment Fn+2, and the 10th to 19th bits in the data 530 as the fragment Fn+3 at the time point t2, and output The information of the two segments is given to the decoder 177.

Referring to FIG. 5B, for example, when the offset register record is 2, the stream splitter 175 can treat the 2nd to 11th bits in the data 510 as a segment Fn at time t1, and output the data of this segment for decoding In addition, the 12th to 19th bits in the data 510 are reserved for later use. The stream splitter 175 can combine the retained data bits with the 0th to 1st bits in the data 530 as the fragment Fn+1 at the time point t2, and the 2nd to 11th bits in the data 530 as the fragment Fn+1. Fragment Fn+2, and output the data of the two fragments to the decoder 177. In addition, the 12th to 19th bits in the data 530 are reserved for later use.

According to different SerDes environment settings, the decoder 177 can be an 8b/10b converter (Converter), a 64b/66b converter or a 128b/130b converter. The decoder 177 includes a mapping table for converting the input data bits into codes represented by fewer bits, for example, mapping the input 10, 66 or 130-bit data into 8, 64 or 128-bit codes. When any input data bit cannot be converted according to the mapping table, the decoder 177 determines that the input data bit is wrong, and can output a decoding error signal to the boundary detector 174. Conversely, when the transcoding is successful, the decoder 177 outputs a decoding success signal to the boundary detector 174. For example, in an 8b/10b SerDes environment, 10 bits can represent 2 ¹⁰ =1024 states, and the mapping table only contains 2 ⁸ =256 mapping relationships. Therefore, when the decoder 177 cannot convert the input data bits into any code, it means that the original data has been changed during the transmission process.

Referring to FIG. 1, the boundary detector 174 has the boundary lock mode (such as the burst header of UFS or the comma symbol of PCI-E) in the detection data register 173 and the preset special symbols (such as the padding element of UFS or PCI -E FTS) capabilities. It should be noted that this default special symbol is not originally used in the specification to determine the boundary of each segment in the data stream, but has other uses. The boundary detector 174 continuously detects the content of the data register 173, and when the data register 173 contains the boundary lock mode or the preset special symbol, outputs the detected boundary lock mode or the preset special symbol in the data register 173 The start address is given to the offset register 176 for updating the value of the offset register 176 to the detected start address. After that, the stream splitter 175 cuts the data segment in the data register 173 according to the new value stored in the offset register 176.

Referring to FIG. 6, in some embodiments of the 8b/10b SerDes environment, for the UFS burst head (K.28.5), the boundary detector 174 includes 11 output circuits 630-0 to 630-10, coupled to offset registers 176, respectively output 0 to 10 to the offset register 176 when being driven. The boundary detector 174 includes 11 comparators 610-0 to 610-10 for detecting all possible combinations of continuous 10-bit data in the data register 173. For example, the comparator 610-0 detects the data D[9:0] from the 0th to 9th bits in the data register 173, and the comparator 610-1 detects the data D[9:0] from the 1st to 10th bits in the data register 173. :1], and so on. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit corresponds to the starting address of the continuous 10-bit data input by the comparator in the data register 173. For example, the comparator 610-0 is coupled to the output circuit 630-0 capable of outputting 0, the comparator 610-1 is coupled to the output circuit 630-1 capable of outputting 1, and so on. Each of the comparators 610-0 to 610-10 compares the input continuous 10-bit data and the UFS burst header. When the input 10-bit data matches the UFS burst header, the comparator output signal drives the coupled output circuit to output a specific value (that is, the start address of the UFS burst header in the data register 173) to Offset register 176. On the contrary, the comparator does not output a signal. In addition, for the UFS filling element (K.28.1), the boundary detector 174 further includes 11 comparators 620-0 to 620-10 for detecting all possible combinations of continuous 10-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit corresponds to the starting address of the continuous 10-bit data input by the comparator in the data register 173. For example, the comparator 620-0 is coupled to the output circuit 630-0 capable of outputting 0, the comparator 620-1 is coupled to the output circuit 630-1 capable of outputting 1, and so on. Each of the comparators 620-0 to 620-10 compares the input continuous 10-bit data and the UFS padding element. When the input 10-bit data matches the padding element of UFS, the comparator output signal drives the coupled output circuit to output a specific value (that is, the starting address of the padding element in the data register 173) to the offset register 176. On the contrary, the comparator does not output a signal.

Referring to FIG. 7, in some embodiments of the 128b/130b SerDes environment, the data register 173 stores 260 bits of data. For the PCI-E comma symbol (K28.5), the boundary detector 174 includes 131 output circuits 730-0 to 730-130, which are coupled to the offset register 176, and respectively output 0 to 130 to the offset when being driven Register 176. The boundary detector 174 includes 131 comparators 710-0 to 710-130 for detecting all possible combinations of continuous 130-bit data in the data register 173. For example, the comparator 710-0 detects the data D[129:0] of bits 0 to 129 in the data register 173, and the comparator 710-1 detects the data D[130] of bits 1 to 130 in the data register 173. :1], and so on. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit corresponds to the starting address of the continuous 130-bit data input by the comparator in the data register 173. For example, the comparator 710-0 is coupled to the output circuit 730-0 capable of outputting 0, the comparator 710-1 is coupled to the output circuit 730-1 capable of outputting 1, and so on. Each of the comparators 710-0 to 710-130 compares the input continuous 130-bit data and the PCI-E comma symbol. When the input 130-bit data matches the PCI-E comma symbol, the comparator output signal drives the coupled output circuit to output a specific value (that is, the PCI-E comma symbol is the start bit of the data register 173 Address) to the offset register 176. On the contrary, the comparator does not output a signal. In addition, for PCI-E FTS (K28.1), the boundary detector 174 includes 131 comparators 720-0 to 720-130 for detecting all possible combinations of continuous 130-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit corresponds to the starting address of the continuous 130-bit data input by the comparator in the data register 173. For example, the comparator 720-0 is coupled to the output circuit 740-0 capable of outputting 0, the comparator 720-1 is coupled to the output circuit 740-1 capable of outputting 1, and so on. Each of the comparators 720-0 to 720-130 compares the input continuous 130-bit data and PCI-E FTS. When the input 130-bit data matches the PCI-E FTS, the comparator output signal drives the coupled output circuit to output a specific value (that is, the starting address of the PCI-E FTS in the data register 173) to the offset Shift register 176. On the contrary, the comparator does not output a signal.

Referring to FIG. 8, in some embodiments of the 8b/10b SerDes environment, the boundary detector 174 includes a multiplexer (Multiplexer MUX) 850, the two input terminals of which are respectively inputted with the UFS burst header and the UFS filling element. The multiplexer 850 outputs the UFS burst header to all the comparators 810-0 to 810-10 according to the control signal Ct corresponding to the decoding success signal of the decoder 177, and according to the control signal Ct corresponding to the decoding failure signal of the decoder 177 'Output UFS padding element to all comparators 810-0 to 810-10. The boundary detector 174 includes 11 output circuits 830-0 to 830-10, the coupling relationship and functions of which are respectively similar to the output circuits 730-0 to 730-10 shown in FIG. 7. The boundary detector 174 includes 11 comparators 810-0 to 810-10 for detecting all possible combinations of continuous 10-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit corresponds to the starting address of the continuous 10-bit data input by the comparator in the data register 173. Each of the comparators 810-0 to 810-10 compares the continuous 10-bit data input from the data register 173 with the code input from the multiplexer 850. When the two match, the comparator output signal drives the coupled output circuit to output a specific value (that is, the start address of the UFS burst header or UFS filling element in the data register 173) to the offset register 176. On the contrary, the comparator does not output a signal. Compared to Figure 6, the circuit shown in Figure 8 reduces the number of comparators by half.

Referring to FIG. 9, in some embodiments of the 128b/130b SerDes environment, the boundary detector 174 includes a multiplexer 950 whose two input terminals respectively input the PCI-E comma symbol and the PCI-E FTS. The multiplexer 950 outputs the PCI-E comma symbol to all the comparators 910-0 to 910-10 according to the control signal Ct corresponding to the decoding success signal of the decoder 177, and is controlled according to the decoding failure signal corresponding to the decoder 177 The signal Ct' outputs PCI-E FTS to all the comparators 910-0 to 910-10. The boundary detector 174 includes 131 output circuits 930-0 to 930-130, the coupling relationship and functions of which are respectively similar to the output circuits 730-0 to 730-130 shown in FIG. The boundary detector 174 includes 131 comparators 910-0 to 910-130 for detecting all possible combinations of continuous 130-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit corresponds to the starting address of the continuous 130-bit data input by the comparator in the data register 173. Each of the comparators 910-0 to 910-130 compares the continuous 130-bit data input from the data register 173 with the code input from the multiplexer 950. When the two match, the comparator output signal drives the coupled output circuit to output a specific value (that is, the PCI-E comma symbol or the start address of the PCI-E FTS in the data register 173) to the offset Register 176. On the contrary, the comparator does not output a signal. Compared to Fig. 7, the circuit shown in Fig. 9 reduces the number of comparators by half.

In some embodiments, refer to the data stream cutting method performed by the physical layer 170 shown in FIG. 10.

Step S1010: This method continuously updates the content in the data register 173 to store the data transmitted from the host terminal 110.

Step S1030: After each content in the data register 173 is updated, compare each possible combination of n consecutive bit data in the data register 137 with the boundary lock mode.

Step S1050: After each content in the data register 173 is updated, each possible combination of n consecutive bits of data in the data register 137 is compared with the preset special symbol.

Step S1070: When any combination of n consecutive bits of data in the data register 137 matches the boundary lock mode or the preset special symbol, it is changed to start according to the boundary lock mode or the preset special symbol in the data register 137 The starting address cuts the content in the data register 137 and is used to generate one or more segments.

In other embodiments, refer to the data stream cutting method executed by the physical layer 170 shown in FIG. 11.

Step S1110: This method continuously updates the content in the data register 173 to store the data transmitted from the host terminal 110.

Step S1130: Each time the content in the data register 173 is updated and the previously cut data is successfully decoded, each possible combination of n consecutive bit data in the data register 137 is compared with the boundary lock mode.

Step S1150: Each time the content in the data register 173 is updated and the previously cut data fails to decode, each possible combination of n consecutive bits of data in the data register 137 is compared with the preset special symbol.

Step S1170: When any combination of n consecutive bits of data in the data register 137 matches the boundary lock mode or the preset special symbol, the start bit in the data register 137 is based on the boundary lock mode or the preset special symbol The content in the data register 137 is segmented to generate one or more segments.

In some use cases of the method shown in Figure 10 or Figure 11, n is 10, the physical layer 170 is set to 8b/10b SerDes environment, the boundary lock mode is K.28.5 symbol, and the special symbol is used by the host during the idle period. K.28.1 symbol transmitted by 110.

In some other use cases of the method shown in Figure 10 or Figure 11, n is 130, the physical layer 170 is set to 128b/130b SerDes environment, the boundary lock mode is K28.5 symbol, and the special symbol is transmitted by the host side 110 And insert the K28.1 symbol before the valid data.

Although the embodiments of the present invention describe 8b/10b and 128b/130b SerDes environments as examples, those skilled in the art can also apply appropriate modifications to the devices and methods proposed in the embodiments to other SerDes environments in data storage, such as 64b /66b SerDes environment, etc.

Although FIGS. 1 to 2 and 6 to 9 include the above-described elements, it is not excluded that, without violating the spirit of the invention, more other additional elements can be used to achieve better technical effects. In addition, although the flowcharts in Figures 10-11 are executed in the specified order, those skilled in the art can modify the order of these steps on the premise of achieving the same effect without violating the spirit of the invention. Therefore, this The invention is not limited to using only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of applied claims must be interpreted in the broadest way to include all obvious modifications and similar settings.

110: host side 130: Controller 131: Processing Unit 133: Media Access Control Layer 135: Static random access memory 138: NAND flash memory controller 139: Storage Interface 150: storage device 151: Flash memory interface 153#0~153#15: NAND flash memory module 170: physical layer 171: Host Interface 173: Data Register 174: Boundary Detector 175: Stream Splitter 176: offset register 177: Decoder 179: Parallel Interface 310,330,350,510,530: data 330p, 350q: data bits 410: UFS's bunch of hair 420: host command 430: confirmation message 450: Filling Yuan 460: User Data Fn-1, Fn, Fn+1, Fn+2, Fn+3: data fragments 610-0~610-10,620-0~620-10,710-0~710-130,720-0~720-130,810-0~810-10,910-0~910-130: Comparator 630-0~630-10,730-0~730-130,830-0~830-10,830-0~830-130: output circuit 850,950: Multiplexer S1010~S1070, S1110~S1170: method steps

FIG. 1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of the connection between the flash memory interface and the storage unit.

FIG. 3A is a schematic diagram of the original data stream.

Figures 3B and 3C are schematic diagrams of the interfered data stream.

Figure 4 is a timing diagram of the host side writing user data.

5A and 5B are schematic diagrams of data fragment cutting according to an embodiment of the present invention.

6 to 9 are block diagrams of a boundary detector according to an embodiment of the present invention.

10 to 11 are flowcharts of a data stream cutting method according to an embodiment of the present invention.

110: main device

130: Controller

131: Processing Unit

133: Media Access Control Layer

135: Static random access memory

138: NAND flash memory controller

139: Storage Interface

150: storage device

171: Host Interface

173: Data Register

174: Boundary Detector

175: Stream Splitter

176: offset register

177: Decoder

179: Parallel Interface

Claims (14)

A data stream cutting device, installed in a physical layer, includes: A host interface, coupled to a host end; A data register, coupled to the host interface, for storing data received from the host through the host interface; and A boundary detector, coupled to the data register, is used to detect the content of the data register, and when the data register contains a boundary lock mode or a special symbol, output the boundary detected in the data register The lock mode or a starting address of the special symbol is given to an offset register to update the value stored in the offset register, so that a stream splitter performs the data in the data register according to the new value stored in the offset register Fragment cutting. The data stream cutting device according to claim 1, wherein the physical layer is set to an 8b/10b serializer/deserializer environment, the boundary lock mode is a K.28.5 symbol, and the special symbol is during an idle period The K.28.1 symbol transmitted by the host. The data stream cutting device according to claim 2, wherein the boundary detector includes: A plurality of output circuits coupled to the offset register, wherein each of the output circuits is used to output a specific value to the offset register when being driven; A plurality of first comparators are used to detect all possible combinations of continuous 10-bit data in the data register, wherein each of the first comparators is coupled to a corresponding output circuit, and when the data is detected When the continuous 10-bit data input by the register matches the K.28.5 symbol, drive the coupled output circuit; and A plurality of second comparators are used to detect all possible combinations of continuous 10-bit data in the data register, wherein each of the second comparators is coupled to a corresponding output circuit, and when the data is detected When the continuous 10-bit data input by the register matches the K.28.1 symbol, the coupled output circuit is driven. The data stream cutting device according to claim 2, wherein the boundary detector includes: A plurality of output circuits coupled to the offset register, wherein each of the output circuits is used to output a specific value to the offset register when being driven; A multiplexer, coupled to a decoder, for outputting the K.28.5 symbol according to a control signal corresponding to a decoding success message of the decoder, and according to a control signal corresponding to a decoding failure message of the decoder The signal outputs the K.28.1 symbol; and Multiple comparators are used to detect all possible combinations of continuous 10-bit data in the data register. Each of the comparators is coupled to a corresponding output circuit and the multiplexer. When the continuous 10-bit data input by the data register matches the sign output by the multiplexer, the coupled output circuit is driven. The data stream cutting device according to claim 1, wherein the physical layer is set to a 128b/130b serializer/deserializer environment, the boundary lock mode is a K28.5 symbol, and the special symbol is used by the host The terminal sends and inserts the K28.1 symbol before the valid data. The data stream cutting device according to claim 5, wherein the boundary detector includes: A plurality of output circuits coupled to the offset register, wherein each of the output circuits is used to output a specific value to the offset register when being driven; A plurality of first comparators are used to detect all possible combinations of continuous 130-bit data in the data register. Each of the first comparators is coupled to a corresponding output circuit. When the data is detected When the continuous 130-bit data input by the register matches the K28.5 symbol, drive the coupled output circuit; and A plurality of second comparators are used to detect all possible combinations of continuous 130-bit data in the data register. Each of the second comparators is coupled to a corresponding output circuit. When the data is detected When the continuous 130-bit data input by the register matches the K.281 symbol, the coupled output circuit is driven. The data stream cutting device according to claim 5, wherein the boundary detector includes: A plurality of output circuits coupled to the offset register, wherein each of the output circuits is used to output a specific value to the offset register when being driven; A multiplexer, coupled to a decoder, for outputting the K28.5 symbol according to a control signal corresponding to a decoding success message of the decoder, and according to a control signal corresponding to a decoding failure message of the decoder The signal outputs the K28.1 symbol; and Multiple comparators are used to detect all possible combinations of continuous 130-bit data in the data register. Each of the comparators is coupled to a corresponding output circuit and the multiplexer. When the continuous 130-bit data input by the data register matches the sign output by the multiplexer, the coupled output circuit is driven. The data stream cutting device according to claim 1, wherein the physical layer is set as a serializer/deserializer environment. A data stream cutting method, executed by a physical layer, including: Compare each combination of n consecutive bits of data in a data register with a boundary lock mode; Compare each combination of n consecutive bits of data in the data register with a special symbol; and When any combination of n consecutive bits of data in the data register matches the boundary lock mode or the special symbol, it is changed to cut the data according to the boundary lock mode or the starting address of the special symbol in the data register The content in the data register is used to generate one or more fragments. The data stream cutting method according to claim 9, wherein n is 10, the physical layer is set to 8b/10b serializer/deserializer environment, the boundary lock mode is K.28.5 symbol, and the special symbol It is a K.28.1 symbol transmitted by a host during an idle period. The data stream cutting method according to claim 9, wherein n is 130, the physical layer is set to 128b/130b serializer/deserializer environment, the boundary lock mode is K28.5 symbol, and the special symbol It is the K28.1 symbol sent by a host and inserted before the valid data. A data stream cutting method, executed by a physical layer, including: When the previously cut data is successfully decoded, compare each combination of n consecutive bits of data in a data register with a boundary lock mode; When the previously cut data fails to decode, compare each combination of n consecutive bits of data in the data register with a special symbol; and When any combination of n consecutive bits of data in the data register matches the boundary lock mode or the special symbol, it is changed to cut the data according to the boundary lock mode or the starting address of the special symbol in the data register The content in the data register is used to generate one or more fragments. The data stream cutting method according to claim 12, wherein n is 10, the physical layer is set to 8b/10b serializer/deserializer environment, the boundary lock mode is K.28.5 symbol, and the special symbol It is a K.28.1 symbol transmitted by a host during an idle period. The data stream cutting method according to claim 12, wherein n is 130, the physical layer is set to 128b/130b serializer/deserializer environment, the boundary lock mode is K28.5 symbol, and the special symbol It is the K28.1 symbol sent by a host and inserted before the valid data.

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