TWI818274B - Apparatus and method for segmenting a data stream of a physical layer - Google Patents

Abstract

An apparatus for diving a data stream, installed in a physical layer, includes: a data register and a boundary detector. The boundary detector is capable of detecting a special symbol. The boundary detector detects the content of the data buffer, and when detecting a special symbol, outputs a starting address that the special symbol stored in the data buffer to an offset register for updating a value of the offset register, thereby enabling a stream divider to perform data-segment divisions according to a new value stored in the offset register. By additionally tracking the special symbol, the physical layer reduces time for correcting data-segment errors resulting from a reduced quantity of boundary-lock patterns sent by a host.

Description

Physical layer data stream cutting device and method

The present invention relates to a storage device, and in particular, to a physical layer data stream cutting device and method.

Flash memory devices are generally divided into NOR flash memory devices and NAND flash memory devices. The NOR flash memory device is a random access device. The host can provide any address for accessing the NOR flash memory device on the address pin and obtain the data pin of the NOR flash memory device in real time. Get the data stored at this address. In contrast, NAND flash memory devices do not have random access, but sequential access. NAND flash memory devices cannot access any random address like NOR flash memory devices. Instead, the master device needs to write a sequence of bytes values to the NAND flash memory device to define the request. The type of command (e.g., read, write, erase, etc.), and the address used for this command. The address can point to a page (the smallest block of data for a write operation in a flash memory device) or a block (the smallest block of data for an erase operation in a flash memory device).

In order to meet the requirements of high-speed communication, the physical layer of the flash memory device may include a serializer/deserializer (SerDes for short). SerDes is a pair of functional circuits used to make up for the shortcomings of limited input/output. It provides data transmission on a single wire or a differential pair, allowing the input and output pins and the wiring between them to be minimized. Specifically, the transmitting end converts low-speed parallel signals into high-speed serial signals and transmits them to the receiving end through a single wire or differential pair. However, in the SerDes environment, due to frequency difference or environmental factors, the Phase-Locked Loop PLL loses its lock (Lose Lock), causing unnecessary bits to be inserted into the original data, or the original data to be lost. part of the bits. because Therefore, the present invention proposes a data stream cutting device and method to solve the above problems.

In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is a problem that needs to be solved.

This specification provides an embodiment of a physical layer data stream cutting device, which is installed in the physical layer and includes: a data register and a boundary detector. The boundary detector has the ability to detect special symbols and is used to detect the contents of the data register. When the data register contains special symbols, it outputs the starting address of the special symbols detected in the data register to the offset register. The value stored in the offset register is updated, so that the stream splitter performs segmentation of the data fragments in the data register according to the new value stored in the offset register.

This specification provides an embodiment of a data stream cutting method, which is executed by the physical layer and includes: comparing each combination of n consecutive n-bit data in the data register with a special symbol; and when the n consecutive n-bit data in the data register is When any combination matches a special symbol, the content in the data register is cut according to the starting address of the special symbol in the data register to generate one or more fragments.

This specification provides another embodiment of a data stream cutting method, which is executed by the physical layer, including: when the previously cut data fails to be decoded, comparing each combination of consecutive n bit data in the data register with a special symbol; and when When any combination of n consecutive n-bit data in the data register matches a special symbol, the content in the data register is changed to be cut according to the boundary lock mode or the starting address of the special symbol in the data register to generate one or more fragments.

One of the advantages of the above embodiment is to reduce the time required to correct data cutting errors when the host side reduces the boundary lock mode by tracking special symbols in the physical layer.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

110: Host side

130:Controller

131: Processing unit

133:Media access control layer

135: Static random access memory

138:NAND flash controller

139:Storage interface

150:Storage device

151:Flash interface

153#0~153#15: NAND flash memory module

170:Entity layer

171:Host interface

173:Data register

174: Boundary Detector

175:Stream splitter

176:Offset register

177:Decoder

179: Parallel interface

310,330,350,510,530: Information

330p, 350q: data bits

410:UFS’s Congfatou

420: Host writes command

430: Confirmation message

450: Filling element

460:User information

Fn-1,Fn,Fn+1,Fn+2,Fn+3: data fragment

610-0~610-10,620-0~620-10,710-0~710-130,720-0~720-130,810-0~810-10,910-0~910-130: Comparator

630-0~630-10,730-0~730-130,830-0~830-10,930-0~930-130: Output circuit

850,950:Mux

S1010~S1070, S1110~S1170: Method steps

FIG. 1 is a schematic diagram of the system architecture of a flash memory according to an embodiment of the present invention.

Figure 2 is a schematic diagram of the connection between the flash memory interface and the storage unit.

Figure 3A is a schematic diagram of raw data streaming.

Figures 3B and 3C are schematic diagrams of disturbed data streams.

Figure 4 is a timing diagram for the host to write user data.

5A and 5B are schematic diagrams of data fragment cutting according to an embodiment of the present invention.

6 to 9 are block diagrams of boundary detectors according to embodiments of the present invention.

10 to 11 are flowcharts of a data stream cutting method according to an embodiment of the present invention.

The following description is a preferred implementation manner for completing the invention, and its purpose is to describe the basic spirit of the invention, but is not intended to limit the invention. For the actual invention, reference must be made to the following claims.

It must be understood that the words "including" and "include" used in this specification are used to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude the possibility of adding further technical features, values, method steps, processes, components, components, or any combination of the above.

The use of words such as "first", "second" and "third" in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority, precedence relationship between them, or that they are one element. Prior to another element, or the chronological order in which method steps are performed, it is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements could be interpreted in a similar fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," etc.

Refer to Figure 1. The electronic device includes a host side (Host Side) 110, a controller 130 and a storage device 150, and the controller 130 and the storage device 150 can be collectively referred to as a device side (Device). Side). The electronic device may be a personal computer, a laptop computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera and other electronic products. The interface of the host 110 (not shown in Figure 1) and the host interface (Host Interface) 171 of the controller 130 can use Universal Flash Storage (UFS) or Universal Serial Bus (USB) , Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E) and other communication protocols to communicate with each other. The storage interface (Storage Interface) 139 of the controller 130 and the flash memory interface of the storage device 150 can communicate with each other using a Double Data Rate (DDR) communication protocol, such as Open NAND Flash Interface (ONFI), Double data rate switch (DDR Toggle) or other interface protocols. The controller 130 includes a processing unit 131 for receiving host commands from the host 110 through a physical layer (Physical Layer, PHY) 170 and a media access control layer (Media Access Control, MAC Layer) 133, such as reading, writing, Erase command etc. The processing unit 131 may be implemented in a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and when executing software and/or Provides specified functions when executing firmware commands. The controller 130 also includes a Static Random Access Memory (SRAM) 135, which is used to configure space as a data buffer to store user data to be written to the storage device 150 by the host write command. The host read command indicates from The user data read by the storage device 150, as well as the data required during the execution process, such as variables, data tables, host-to-flash (H2F Table), flash-to-host comparison table (Flash-to -Host, F2H Table), etc. The controller 130 also includes a NAND Flash Controller (NFC) 138, which provides functions required in accessing the storage device 150, such as a command sequencer (Command Sequencer) and a low density parity check (Low Density Parity Check). LDPC) wait. The processing unit 131 instructs the storage device 150 to perform data reading, writing, erasing and other operations through the NFC 138 and the storage interface 139 according to the host command.

The storage device 150 includes a storage unit 153, which provides a large amount of storage space, usually hundreds of gigabytes (GB) or even several terabytes (TB), for storing a large amount of data. User data, such as high-resolution images, videos, etc. The storage unit 153 includes a control circuit and a memory array. The memory cells in the memory array may include single level cells (Single Level Cells, SLCs), multiple level cells (Multiple Level Cells, MLCs), or triple level cells. Cells (TLCs), Quad-Level Cells (QLCs), or any combination of the above. The processing unit 131 writes the user data to the specified address (destination address) in the storage device 150 (specifically, the storage unit 153) through the storage interface 139, and from the specified address (source address) in the storage device 150 ) reads user data. The storage interface 139 uses several electronic signals to coordinate the transfer of data and commands between the controller 130 and the storage device 150, including a data line (Data Line), a clock signal (Clock Signal), and a control signal (Control Signal). Data lines can be used to transmit commands, addresses, read and write data; control signal lines can be used to transmit chip enable (Chip Enable, CE), address extraction enable (Address Latch Enable, ALE), command extraction enable Control signals such as Command Latch Enable (CLE) and Write Enable (WE).

Referring to Figure 2, the flash memory interface 151 may include four input/output channels (I/O channels, hereinafter referred to as channels) CH#0 to CH#3. Each channel is connected to four NAND flash memory modules. For example, channel CH#0 is connected NAND flash memory modules 153#0, 153#4, 153#8 and 153#12. Each NAND flash memory module can be packaged as an independent chip (die). The NAND flash memory controller 138 can send one of the enable signals CE#0 to CE#3 through the storage interface 139 and the flash memory interface 151 to enable the NAND flash memory modules 153#0 to 153#3, 153#4 to 153#7. , 153#8 to 153#11, or 153#12 to 153#15, and then read user data from the enabled NAND flash module in parallel, or write user data to Enabled NAND flash memory modules.

The physical layer 170 of the controller 130 may be configured as an 8b/10b, 64b/66b or 128b/130b serializer/deserializer (SerDes) environment. However, frequency differences or environmental factors can cause the phase-locked loop (Phase-Locked Loop PLL) to lose lock, causing unnecessary bits to be inserted into the original data transmitted by the host 110, or the host 110 losing A portion of the bits in the original data being transmitted. When the controller 130 is mounted on a mobile phone, environmental interference is more serious. For example, the surge generated by the user's operation of the touch screen affects the analog circuit in the physical layer 170 (also called the analog physical layer Analog Physical Layer A- PHY), causing phase-locked loop de-locking to occur more frequently. The analog physical layer contains a serializer that maps each data segment into a code that uses more bits before serializing the data, such as mapping 8, 64, or 128-bit segments into 10, 66, or 130 bits. Bit code. For example, referring to FIG. 3A , the host 110 transmits data 310 to the physical layer 170 in the controller 130 through the host interface 171 , including the data stream “b01100001101010000011”. However, due to the unlocking of the phase-locked loop, the physical layer 170 receives the error data 330 as shown in FIG. 3B or the error data 350 as shown in FIG. 3C. The data stream 330 in Figure 3B includes the bit "b11" 330p that does not exist in the original data 310, while the data stream 350 in Figure 3C is missing the original bit "b00" 350q in the original data 310. Since the original data stream consists of a series of fragments of a fixed size (for example, 10, 66, 130 bits, or other numbers of bits), incorrectly inserted or missing bits can cause subsequent data segmentation errors. For example, the original data stream 310 shown in FIG. 3A should originally be cut into two 10-bit segments "b0110000110" and "b1010000011". However, the data stream 330 shown in FIG. 3B is cut into two incorrect 10-bit fragments "b0110011001" and "b1010100000". The data stream 350 shown in Figure 3C cuts out two incorrect 10-bit fragments "b0110011010" and "b10000011xx".

In order to solve the cutting error caused by the unlocking of the phase-locked loop as described above, in some implementations of the 8b/10bSerDes environment, the host 110 can periodically transmit the boundary lock Boundary-lock Pattern, such as the Head of Burst HOB (also known as MK0 or K.28.5 symbol) of UFS, etc., allows the physical layer 170 to track the boundaries of the data stream transmitted from the host interface 171 Lock mode to re-determine the Boundary of each segment and cut accordingly. In some implementations of the 128b/130b SerDes environment, the host 110 can periodically transmit a boundary lock mode, such as PCI-E Comma Character (also known as K28.5 symbol), etc., to allow the physical layer to 170 determines and cuts fragment boundaries. However, in order to obtain a better transmission rate, the host 110 may reduce the number of transmissions in the boundary lock mode, which further lengthens the time for the physical layer 170 to correct data cutting errors.

In order to improve the shortcomings of the above implementations, in the 8b/10b SerDes environment, the embodiment of the present invention proposes a physical layer circuit that not only tracks the boundary lock mode in the data stream transmitted from the host interface 171 during valid packet transmission, but also Special symbols in the information stream transmitted from the host interface 171 are also tracked during the idle period (Idle), such as UFS filler elements (FILLER, also known as K.28.1 symbols). Referring to Figure 4, taking the host 110 writing user data as an example. Under normal circumstances, the host 110 sends the HOB 410 and then the host write command CMD 420 to enable the controller 130 to correctly cut the data stream. Next, after receiving the acknowledgment message (Acknowledgement ACK) 430 sent by the controller 130, the host 110 starts to transmit the user data DAT 460. Before starting to transmit user data, the host 110 sends HOB 410 to allow the controller 130 to correctly cut the data stream. The host write command CMD 420 and user data 460 can be called valid packets. Those skilled in the art understand that valid packets also include host management commands, other host input and output commands, parameters, and other information that can be used by the protocol layer (Protocol Layer). The period during which valid packets and associated necessary control symbols (such as boundary lock mode, synchronization mode SYN, etc.) are transmitted is called the valid packet transmission period. The period from when the host write command CMD 420 is sent to the next HOB 410 is called the idle period t _IDLE . During the idle period t _IDLE waiting for the confirmation 430 from the device side, the host side 110 may continuously send fill elements FIL 450 to the device side. Please refer to Table 1 for details of UFS cluster heads and filling elements:

In the 128b/130b SerDes environment, the physical layer circuit not only tracks the boundary lock mode during data transmission, but also tracks a special symbol, such as PCI-E's Fast Training Sequence FTS (also known as K28.1 symbol). For details about PCI-E comma symbols and fast training sequences, please refer to Table 2:

Those skilled in the art understand that FTS is used to be inserted before valid data. By tracking more symbols, the physical layer 170 can also correct data cutting errors as early as possible when the host 110 extends the period of transmitting the synchronization pattern.

Referring to FIG. 1 , the physical layer 170 includes the host interface 171 as mentioned above, which is used for receiving host commands, parameters, user information, etc. from the host terminal 110 . Taking the 8b/10b SerDes environment as an example, the host commands, parameters and user data sent by the host 110 will be encoded in 10-bit units. The physical layer 170 further includes a data register 173, a boundary detector 174, a stream splitter 175, an offset register (Offset Register) 176 and a decoder 177. The data register 173 can store 20 bits of data received through the host interface 171 . The offset register 176 records the boundary (Boundary, also called the starting address of cutting) of the data segment. A stream splitter (Stream Splitter) 175 splits the data bits in the data register 173 into one or more segments according to the value of the offset register 176, and outputs the segments to the decoder 177. 5A and 5B respectively show the data segment cutting situation when the offset register 173 records 0 and 2 according to the embodiment of the present invention. The data register 173 stores at time point t1 20 bits of data 510 are stored, and then the next 20 bits of data 530 are stored at time point t2.

Referring to FIG. 5A, for example, when the offset register 176 records 0, the stream splitter 175 can regard the 0th to 9th bits in the data 510 as the fragment Fn at time point t1, and the 0th to 9th bits in the data 510 as the fragment Fn. 10 to 19 bits are regarded as segment Fn+1, and the data of the two segments are output to the decoder 177. The stream splitter 175 can treat the 0th to 9th bits in the data 530 as the segment Fn+2, the 10th to 19th bits in the data 530 as the segment Fn+3 at the time point t2, and output The two fragments of data are given to the decoder 177.

Referring to FIG. 5B, for example, when the offset register 176 records 2, the stream splitter 175 can regard the 2nd to 11th bits in the data 510 as a segment Fn at time point t1, and output the data of this segment to Decoder 177, in addition, bits 12 to 19 of the data 510 are reserved for later use. The stream splitter 175 may combine the retained data bits with the 0th to 1st bits in the data 530 as the fragment Fn+1 at the time point t2, and the 2nd to 11th bits in the data 530 as the fragment Fn+1. Fragment Fn+2, and output the data of the two fragments to the decoder 177. In addition, the 12th to 19th bits in the data 530 are reserved for later use.

According to different SerDes environment settings, the decoder 177 can be an 8b/10b converter (Converter), a 64b/66b converter or a 128b/130b converter. The decoder 177 includes a mapping table for converting input data bits into codes represented by fewer bits, for example, mapping input 10, 66 or 130-bit data into 8, 64 or 128-bit codes. When any input data bit cannot be converted into any code according to the mapping table, the decoder 177 determines that the input data bit is incorrect and may output a decoding error signal to the boundary detector 174 . On the contrary, when the transcoding is successful, the decoder 177 outputs a decoding success signal to the boundary detector 174 . For example, in an 8b/10b SerDes environment, 10 bits can represent 2 ¹⁰ =1024 states, and the mapping table only contains 2 ⁸ =256 mapping relationships. Therefore, when the decoder 177 cannot convert the input data bits into any code, it means that the original data has been changed during transmission.

Referring to FIG. 1 , the boundary detector 174 has the boundary locking mode (such as the burst header of UFS or the comma symbol of PCI-E) in the detection data register 173 and the preset special symbol (such as Such as UFS's fill element or PCI-E's FTS) capability. It should be noted that this default special symbol was not originally used in the specification to determine the boundaries of each segment in the data stream, but has other uses. The boundary detector 174 continuously detects the contents of the data register 173, and when the data register 173 contains a boundary lock pattern or a preset special symbol, outputs the boundary lock pattern or the preset special symbol detected in the data register 173. The starting address is given to the offset register 176 for updating the value of the offset register 176 to the detected starting address. Afterwards, the stream splitter 175 splits the data segments in the data register 173 according to the new value stored in the offset register 176 .

Referring to Figure 6, in some embodiments of the 8b/10b SerDes environment, for the UFS burst header (K.28.5), the boundary detector 174 includes 11 output circuits 630-0 to 630-10, coupled to the offset register 176, when driven, outputs 0 to 10 respectively to the offset register 176. The boundary detector 174 includes 11 comparators 610-0 to 610-10, which are used to detect all possible combinations of consecutive 10-bit data in the data register 173. For example, the comparator 610-0 detects the data D[9:0] of the 0th to 9th bits in the data register 173, and the comparator 610-1 detects the data D[10] of the 1st to 10th bits in the data register 173. :1], and so on. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit is consistent with the starting address of the continuous 10-bit data input by the comparator in the data register 173 . For example, the comparator 610-0 is coupled to the output circuit 630-0 capable of outputting 0, the comparator 610-1 is coupled to the output circuit 630-1 capable of outputting 1, and so on. Each of the comparators 610-0 to 610-10 compares the input continuous 10-bit data and the UFS cluster header. When the input 10-bit data matches the UFS cluster header, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting address of the UFS cluster header in the data register 173) to Offset register 176. Otherwise, the comparator does not output a signal. In addition, for UFS padding elements (K.28.1), the boundary detector 174 also includes 11 comparators 620-0 to 620-10 for detecting all possible combinations of consecutive 10-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit is consistent with the starting address of the continuous 10-bit data input by the comparator in the data register 173 . For example, The comparator 620-0 is coupled to the output circuit 630-0 capable of outputting 0, the comparator 620-1 is coupled to the output circuit 630-1 capable of outputting 1, and so on. Each of the comparators 620-0 to 620-10 compares the input continuous 10-bit data and the UFS padding element. When the input 10-bit data matches the filling element of UFS, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting address of the filling element in the data register 173) to the offset register 176. Otherwise, the comparator does not output a signal.

Referring to Figure 7, in some embodiments of a 128b/130b SerDes environment, data register 173 stores 260 bits of data. For PCI-E comma notation (K28.5), the boundary detector 174 includes 131 output circuits 730-0 to 730-130, coupled to the offset register 176, which when driven, output 0 to 130 to offset respectively. Register 176. The boundary detector 174 includes 131 comparators 710-0 to 710-130, which are used to detect all possible combinations of 130 consecutive bits of data in the data register 173. For example, the comparator 710-0 detects the data D[129:0] in the 0th to 129th bits in the data register 173, and the comparator 710-1 detects the data D[130] in the 1st to 130th bits in the data register 173. :1], and so on. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit is consistent with the starting address of the continuous 130-bit data input by the comparator in the data register 173 . For example, the comparator 710-0 is coupled to the output circuit 730-0 capable of outputting 0, the comparator 710-1 is coupled to the output circuit 730-1 capable of outputting 1, and so on. Each of the comparators 710-0 to 710-130 compares the input continuous 130-bit data and the PCI-E comma symbol. When the input 130-bit data matches the PCI-E comma symbol, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting bit of the PCI-E comma symbol in the data register 173 address) to offset register 176. Otherwise, the comparator does not output a signal. In addition, for PCI-E FTS (K28.1), the boundary detector 174 includes 131 comparators 720-0 to 720-130 to detect all possible combinations of continuous 130-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit is consistent with the starting address of the continuous 130-bit data input by the comparator in the data register 173 . For example, the comparator 720-0 is coupled to the output circuit 730-0 capable of outputting 0, and the comparator 720-1 is coupled to the output circuit 730-0 capable of outputting 0. output circuit 730-1 capable of outputting 1, and so on. Each of the comparators 720-0 to 720-130 compares the input continuous 130-bit data and the PCI-E FTS. When the input 130-bit data matches the PCI-E FTS, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting address of the PCI-E FTS in the data register 173) to the offset Shift register 176. Otherwise, the comparator does not output a signal.

Referring to Figure 8, in some embodiments of the 8b/10b SerDes environment, the boundary detector 174 includes a multiplexer (Multiplexer MUX) 850, the two input terminals of which input the UFS burst header and the UFS padding element respectively. The multiplexer 850 outputs the UFS burst header to all comparators 810-0 to 810-10 according to the control signal Ct corresponding to the decoding success signal of the decoder 177, and according to the control signal Ct corresponding to the decoding failure signal of the decoder 177 'Output UFS padding elements to all comparators 810-0 to 810-10. The boundary detector 174 includes 11 output circuits 830-0 to 830-10, whose coupling relationships and functions are respectively similar to the output circuits 630-0 to 630-10 shown in FIG. 6 . The boundary detector 174 includes 11 comparators 810-0 to 810-10, which are used to detect all possible combinations of consecutive 10-bit data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit is consistent with the starting address of the continuous 10-bit data input by the comparator in the data register 173 . Each of the comparators 810-0 to 810-10 compares the continuous 10-bit data input from the data register 173 with the code input from the multiplexer 850. When the two match, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the starting address of the UFS burst header or UFS fill element in the data register 173) to the offset register 176. Otherwise, the comparator does not output a signal. Compared with Figure 6, the circuit shown in Figure 8 has half the comparators.

Referring to Figure 9, in some embodiments of a 128b/130b SerDes environment, the boundary detector 174 includes a multiplexer 950, the two input terminals of which input PCI-E comma symbols and PCI-E FTS respectively. The multiplexer 950 outputs PCI-E comma symbols to all comparators 910-0 to 910-130 according to the control signal Ct corresponding to the decoding success signal of the decoder 177, and according to the control corresponding to the decoding failure signal of the decoder 177 Signal Ct' outputs PCI-E FTS to all comparators 910-0 to 910-130. Boundary detector 174 includes 131 output circuits 930-0 to 930-130, whose coupling relationship and function are respectively similar to the output circuits 730-0 to 730-130 shown in Figure 7. The boundary detector 174 includes 131 comparators 910-0 to 910-130, which are used to detect all possible combinations of 130 consecutive bits of data in the data register 173. Each comparator is coupled to a corresponding output circuit, and the output value of the output circuit is consistent with the starting address of the continuous 130-bit data input by the comparator in the data register 173 . Each of the comparators 910-0 to 910-130 compares the continuous 130-bit data input from the data register 173 with the code input from the multiplexer 950. When the two match, the comparator outputs a signal to drive the coupled output circuit to output a specific value (that is, the PCI-E comma symbol or the starting address of the PCI-E FTS in the data register 173) to the offset Register 176. Otherwise, the comparator does not output a signal. Compared with Figure 7, the circuit shown in Figure 9 has half the comparators.

In some embodiments, refer to the data stream cutting method performed by the physical layer 170 as shown in FIG. 10 .

Step S1010: This method continuously updates the content in the data register 173 to store data transmitted from the host 110.

Step S1030: Each time the content in the data register 173 is updated, compare each possible combination of n consecutive bit data in the data register 173 with the boundary lock mode.

Step S1050: Each time the content in the data register 173 is updated, compare each possible combination of n consecutive bit data in the data register 173 with the preset special symbols.

Step S1070: When any combination of n consecutive n-bit data in the data register 173 matches the boundary lock mode or the preset special symbol, change the starting point in the data register 173 according to the boundary lock mode or the preset special symbol. The content in the starting address cutting data register 173 is used to generate one or more segments.

In other embodiments, refer to the data stream cutting method performed by the physical layer 170 shown in FIG. 11 .

Step S1110: This method continuously updates the content in the data register 173 to store data transmitted from the host 110.

Step S1130: Each time the content in the data register 173 is updated and the previously cut data When the decoding is successful, each possible combination of n consecutive bit data in the data register 173 is compared with the boundary lock mode.

Step S1150: Each time the content in the data register 173 is updated and the previously cut data fails to be decoded, compare each possible combination of n consecutive n bit data in the data register 173 with a preset special symbol.

Step S1170: When any combination of n consecutive n-bit data in the data register 173 matches the boundary lock mode or the preset special symbol, the starting bit in the data register 173 is determined according to the boundary lock mode or the preset special symbol. The contents of the address segmentation data register 173 are used to generate one or more segments.

In some use cases of the method shown in Figure 10 or Figure 11, n is 10, the physical layer 170 is set to an 8b/10b SerDes environment, the boundary lock mode is K.28.5 symbols, and the special symbols are used by the host during idle periods 110 transmitted K.28.1 symbols.

In other use cases of the method shown in Figure 10 or Figure 11, n is 130, the physical layer 170 is set to a 128b/130b SerDes environment, the boundary lock mode is K28.5 symbols, and the special symbols are sent by the host 110 And insert the K28.1 symbol before the valid data.

Although the embodiments of the present invention describe 8b/10b and 128b/130b SerDes environments as examples, those skilled in the art can also make appropriate modifications to the devices and methods proposed in the embodiments and apply them to other SerDes environments in data storage, such as 64b /66b SerDes environment, etc.

Although Figures 1 to 2 and 6 to 9 contain the components described above, it does not rule out that more other additional components can be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flowcharts in Figures 10 to 11 are executed in a specified order, those skilled in the art can modify the order of these steps while achieving the same effect without violating the spirit of the invention. Therefore, this The invention is not limited to the use of only the sequence described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements which will be obvious to one skilled in the art. Therefore, the scope of the claims of the application must be interpreted in the broadest manner to include all obvious modifications and similar arrangements.

110: Host side

130:Controller

131: Processing unit

133:Media access control layer

135: Static random access memory

138:NAND flash controller

139:Storage interface

150:Storage device

171:Host interface

173:Data register

174: Boundary Detector

175:Stream splitter

176:Offset register

177:Decoder

179: Parallel interface

Claims (12)

A data stream cutting device is installed in a physical layer and includes: a host interface coupled to a host; a data register coupled to the host interface for storing data received from the host through the host interface data; and a boundary detector coupled to the data register for detecting the contents of the data register, and when the data register contains a special symbol, outputting the value of the special symbol detected in the data register A starting address is given to an offset register to update the value stored in the offset register, so that a stream splitter performs segmentation of data in the data register according to the new value stored in the offset register. The data stream cutting device of claim 1, wherein the physical layer is configured as an 8b/10b serializer/deserializer environment, and the special symbol is a K.28.1 symbol transmitted by the host during an idle period. The data stream cutting device of claim 2, wherein the boundary detector includes: a plurality of output circuits coupled to the offset register, wherein each of the output circuits is used to output a specific value when driven to the offset register; and a plurality of comparators for detecting all possible combinations of continuous 10-bit data in the data register, wherein each comparator is coupled to a corresponding output circuit. When detecting When the continuous 10-bit data input from the data register matches the K.28.1 symbol, the coupled output circuit is driven. The data stream cutting device as described in claim 1, wherein the physical layer is set to a 128b/130b serializer/deserializer environment, and the special symbol is K28. transmitted by the host and inserted before the valid data. 1 symbol. The data stream cutting device of claim 4, wherein the boundary detector includes: a plurality of output circuits coupled to the offset register, wherein each of the output circuits is used to output a specific value when driven to the offset register; and a plurality of comparators for detecting all possible combinations of continuous 130-bit data in the data register, wherein each comparator is coupled to a corresponding output circuit. When detecting When the continuous 130-bit data input from the data register matches the K28.1 symbol, the coupled output circuit is driven. The data stream cutting device as claimed in claim 1, wherein the physical layer is configured as a serializer/deserializer environment. A data stream cutting method, executed by a physical layer, includes: comparing each combination of n consecutive n bits of data in a data register with a special symbol, where n is a positive integer; and when n consecutive n bits in the data register When any combination of metadata matches the special symbol, the content in the data register is cut according to the starting address of the special symbol in the data register to generate one or more fragments. The data stream cutting method as described in claim 7, wherein n is 10, the physical layer is set to an 8b/10b serializer/deserializer environment, and the special symbol is transmitted by a host during an idle period K.28.1 symbol. The data stream cutting method as described in request item 7, wherein n is 130, the physical layer is set to a 128b/130b serializer/deserializer environment, and the special symbol is transmitted by a host and inserted into a valid K28.1 symbol before the data. A data stream cutting method, executed by a physical layer, includes: when decoding of previously cut data fails, comparing each combination of consecutive n bit data in the data register with a special symbol, where n is a positive integer; and When any combination of n consecutive bits of data in the data register matches the special symbol, the content in the data register is cut according to the starting address of the special symbol in the data register to generate a or multiple fragments. The data stream cutting method as described in claim 10, wherein n is 10, the physical layer is set to an 8b/10b serializer/deserializer environment, and the special symbol is transmitted by a host during an idle period K.28.1 symbol. The data stream cutting method as described in request 10, wherein n is 130, the physical layer is set to a 128b/130b serializer/deserializer environment, and the special symbol is transmitted by a host and inserted into a valid K28.1 symbol before the data.

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