CN111258945A - Embedded system communication interface and communication method - Google Patents
Embedded system communication interface and communication method Download PDFInfo
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- CN111258945A CN111258945A CN202010104591.2A CN202010104591A CN111258945A CN 111258945 A CN111258945 A CN 111258945A CN 202010104591 A CN202010104591 A CN 202010104591A CN 111258945 A CN111258945 A CN 111258945A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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Abstract
The invention discloses a communication interface and a communication method of an embedded system, wherein the communication interface comprises: the logic layer is used for defining all communication protocols and communication protocol packet formats; a transport layer including a data channel and an auxiliary channel for defining a single common transport layer and including a buffer for transmission between the logical layer and the physical layer; and the physical layer is used for defining interface information, and the interface information comprises a communication signal and an interface protocol corresponding to the communication signal. The invention adopts a layered design, makes each layer logic single, and defines all communication protocols and communication protocol packet formats in the logic layer, defines a single common transmission layer in the transmission layer and contains a buffer memory for transmission between the logic layer and the physical layer, and defines communication signals and interface protocols corresponding to the communication signals in the physical layer, thereby improving the transmission capability of the bus without increasing the width and frequency of the data bus. The invention can be widely applied to the technical field of data transmission.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to an embedded system communication interface and a communication method.
Background
The traditional bus adopts the working mode of a parallel bus, and the buses are generally divided into three groups: data lines, address lines, and control lines. The number of pins required to implement such a bus interconnect is large, for example, for a 64-bit data wide bus, there are typically 64 data lines, 32 to 40 address lines and 30 or so control lines, and due to the limitations of the semiconductor manufacturing process, there are a certain number of power and ground lines, resulting in about 200 or so leads, which causes problems for device packaging, testing and soldering. In order to improve the transmission capability of the bus, the conventional bus is usually implemented by increasing the width of the data bus or increasing the frequency of the bus. Increasing the bus frequency and data bandwidth, while somewhat satisfying the demand for high-speed data transfer, the wider bus also results in an increase in the device pin count, thereby increasing the package size and device production cost.
Disclosure of Invention
To solve one of the above technical problems, the present invention aims to: an embedded system communication interface and a communication method are provided, which can improve the transmission capability of a bus without increasing the width of the data bus and the bus frequency.
A first aspect of an embodiment of the present invention provides:
an embedded system communication interface, comprising:
the logic layer is used for defining all communication protocols and communication protocol packet formats;
a transport layer including a data channel and an auxiliary channel for defining a single common transport layer and including a buffer for transmission between the logical layer and the physical layer;
and the physical layer is used for defining interface information, and the interface information comprises a communication signal and an interface protocol corresponding to the communication signal.
Further, the transmission of the auxiliary channel of the transmission layer comprises a write operation cache and a read operation cache of the I2C; the data channel of the transmission layer comprises a message buffer and a data stream buffer.
Further, the cache mode adopts a FIFO mode.
Further, the logical layer includes integrated management of the secondary channel, messaging, flow control, and data flow of the data channel; wherein the content of the first and second substances,
the integrated management of the auxiliary channel is used for carrying out initialization and configuration management;
the message of the data channel is used for transmitting the message, so that the host computer and the slave computer can interact;
a flow control for controlling transmission of a data stream;
and the data stream is used for realizing the transmission logic of the data stream.
Further, the initializing and the configuration managing specifically include:
initialization and configuration management are performed through the read-write operation function of the I2C protocol.
Further, the communication signals include an I2C signal and an LVDS signal group, as well as a clock signal, a trigger signal and a synchronization signal; the I2C signal and the LVDS signal set both use a serial transmission protocol.
Further, the I2C signal and the LVDS signal set both use a serial transmission protocol, which specifically includes:
the serial transmission protocol of the I2C signal is an I2C protocol;
the serial transmission protocol of the LVDS signal group is Aurora8B/10B protocol.
Further, the clock signal, the trigger signal and the synchronous signal are all single-ended signals.
Further, the frequency of the clock signal is a fixed frequency, and the fixed frequency is 25 MHz.
A second aspect of an embodiment of the present invention provides:
an embedded system communication method, comprising the steps of:
acquiring slave terminal information of a preset interface through the preset interface;
initializing a preset interface according to slave terminal information;
acquiring host end information of the initialized preset interface;
controlling the communication between a slave end and a host end of a preset interface according to the host end information;
the preset interface is the embedded system communication interface, and the host information comprises a clock signal, a trigger signal and a synchronization signal.
The invention has the beneficial effects that: the invention adopts a layered design, makes the logic of each layer single, reduces the restriction on software, defines all communication protocols and communication protocol packet formats on a logic layer, defines a single common transmission layer on the transmission layer and contains a buffer memory for transmission between the logic layer and a physical layer, and defines a communication signal and an interface protocol corresponding to the communication signal on the physical layer, so that the transmission capability of the bus can be improved without increasing the width and the bus frequency of a data bus in the communication process.
Drawings
FIG. 1 is a schematic structural diagram of an embedded system communication interface according to an embodiment of the present invention;
fig. 2 is a schematic diagram of connection between a master and a slave according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
Before proceeding with a description of specific embodiments, the following terms are explained:
DashLink; the name of the interface in the embodiment of the present invention.
I2C bus: a simple, bi-directional two-wire synchronous serial bus developed by Philips corporation.
LVDS: the Low Voltage Differential Signaling is a Low-amplitude Differential Signaling technique.
Aurora 8B/10B: first, Aurora is a LogiCORE designed for easy implementation of Xilinx transceiversTMThe IP core provides a light-weight user interface, and a designer can construct a serial link on the basis. Aurora8B/10B is an extensible lightweight link layer protocol for high-speed serial communication.
FIFO mode: the computer is a traditional sequential execution method, In which an instruction entered First is completed and retired First, and then a second instruction is executed.
REF _ CLK, TRIGGER, and SYNC: respectively a reference clock, a trigger signal and a synchronization signal.
The embodiment of the invention provides an embedded system communication interface, which comprises:
the logic layer is used for defining all communication protocols and communication protocol packet formats; the communication protocol and the communication protocol packet format are necessary information for initializing the terminal and completing the transmission.
A transport layer including a data channel and an auxiliary channel for defining a single common transport layer and including a buffer for transmission between the logical layer and the physical layer; the buffers of the transmission layer all adopt FIFO mode, and the auxiliary channel transmission contains a write operation buffer and a read operation buffer of I2C; and the data channel comprises a message buffer and a data stream buffer. In particular, the transport layer is the necessary information for the passage of data packets from one terminal to another. The transmission layer is a single transmission layer, different logic layers and physical layers are compatible and converged by adopting a single common transmission layer specification, and the single logic layer entity enhances the adaptability of the DashLink.
And the physical layer is used for defining interface information, and the interface information comprises a communication signal and an interface protocol corresponding to the communication signal. The interface protocol is an interface protocol between devices such as packet transport, flow control, electrical characteristics, and low level error management.
Specifically, as shown in fig. 1, the DashLink interface is composed of a logic layer, a transport layer, and a physical layer, where:
the logic layer defines all protocols and packet formats, in particular necessary information for initializing the terminal and completing the transmission; specifically, the logic layer mainly includes four logic entities, namely, a message entity, a flow control entity and a data flow entity, of the integrated management and data channel of the auxiliary channel, which are specifically defined as:
integrated management of auxiliary channels: information such as initialization and configuration management of the slave is completed through read-write operation of the I2C protocol.
Message of data channel: the information transmission is completed by walking the data channel, and the information interaction of the master end and the slave end can be completed quickly.
Flow control: controlling the transmission of the data stream.
Data flow: and realizing the transmission of the data stream.
The transport layer is the necessary information for the passage of data packets from one terminal to another; specifically, the transport layer includes a buffer for transmission between the data in the logical layer and the data in the physical layer, and ensures efficiency and stability of transmission between the two layers. In the embodiment, a single common transport layer specification is adopted to accommodate and converge different logical layers and physical layers, and a single logical layer entity enhances the adaptability of the DashLink.
The physical layer describes interface protocols between devices such as packet transport, flow control, electrical characteristics, and low-level error management. Specifically, the physical layer is composed of three parts, namely an I2C signal group, an LVDS signal group and a REF _ CLK/TRIGGER/SYNC. Wherein the I2C signal uses a standard I2C protocol. The LVDS signal set defines a full-duplex serial differential link, an LVDS differential signal interface is adopted, and a serial transmission protocol adopts an Aurora8B/10B protocol of Xilinx, wherein the Aurora8B/10B protocol is a tailorable lightweight link layer protocol developed by Xilinx company for high-speed transmission. In this embodiment, data transmission between two devices is realized through one or more serial links, two data transmission modes of stream and frame and data communication modes such as full duplex and simplex can be supported, four channel number selections of 1x/2x/4x/8x are supported in TX/RX directions, channel number asymmetric selection is supported, a single channel has a highest transmission bandwidth of 1.25Gbps, and a single link can provide a highest bandwidth of 10 Gbps. The three signals of the clock signal, the trigger signal and the synchronous signal adopt single-ended signals. REF _ CLK is a reference clock signal fixed at 25MHz, and is provided by the host side for serial transmission of the transmitted and received reference clocks from the slave side during use. The TRIGGER signal is a TRIGGER signal, and is used for the slave to quickly inform the independent signal of the host from the slave to the host in the using process. The SYNC signal is a synchronous signal, and is used for accurate synchronization among a plurality of DashLink interfaces from the host end to the slave end in the using process. Therefore, the auxiliary channel of the physical layer of this embodiment uses the I2C bus to complete integrated management, the other data channel uses serial mode for transmission, the transmission level uses LVDS mode, 80-100cm of connection line can be allowed between the two connectors, and the single link transmission bandwidth can reach 10 Gbps.
Compared with the existing communication bus, the interface of the embodiment has the following advantages:
the first point is as follows: because the embodiment supports the asymmetry of the number of full-duplex data channels, in the actual process, if the bandwidth of unidirectional 10Gbps needs to be met, only 23 pins are needed, and if the bandwidth is not needed to be high, the number of pins can be further reduced by selecting the proper number of channels according to the requirement;
and a second point: the transmission protocol of the embodiment belongs to lightweight, has distinct layers, and has a single logic entity unit in each layer, so that a clear structure is obtained, the restriction of software is reduced, the efficiency is improved, and the system cost is reduced;
and a third point: the interface of the embodiment can complete the interconnection inside the case, between the back panel chip and the chip, and between the panels, thereby satisfying a large number of embedded scene application functions.
As a preferred embodiment, the buffer mode adopts a FIFO mode. The embodiment performs buffering by adopting the FIFO mode, so that the embodiment can be used for data transmission between different time domains during use.
As a preferred embodiment, the logical layer includes integrated management of the secondary channel, messaging, flow control and data flow of the data channel; wherein the content of the first and second substances,
the integrated management of the auxiliary channel is used for carrying out initialization and configuration management; in particular, the read-write operation function is provided according to the standard I2C protocol implementation.
The message of the data channel is used for transmitting the message, so that the host computer and the slave computer can interact; specifically, the message is taken as an object to realize the functions of sending and receiving the message.
A flow control for controlling transmission of a data stream; in particular, the flow control frame is taken as an object to realize the function of providing data flow blocking.
And the data stream is used for realizing the transmission logic of the data stream, namely the starting and ending positions of the data stream and the data length control function.
In the embodiment, different logic modules are defined for the logic layer, so that the execution of different functional modules is not interfered with each other.
In a preferred embodiment, the clock signal, the trigger signal and the synchronization signal are single-ended signals.
Specifically, the three signals of REF _ CLK, TRIGGER and SYNC of this implementation all adopt single-ended signals, where REF _ CLK is a reference clock signal, and the frequency is fixed to 25MHz, and in the embodiment, the REF _ CLK is provided by the host end and is used for the reference clock of serial transmission and reception at the host end; the TRIGGER signal is a TRIGGER signal, and in the embodiment, the TRIGGER signal is an independent signal used for the slave to quickly inform the host from the slave to the host; the SYNC signal is a synchronization signal, and in an embodiment, is used for precise synchronization between multiple DashLink interfaces from a master end to a slave end.
In addition, the embodiment of the invention also provides an embedded system communication method, which comprises the following steps:
acquiring slave terminal information of a preset interface through the preset interface; the slave side information includes information for controlling the slave side and information for configuring the slave side.
Initializing a preset interface according to slave terminal information;
acquiring host end information of the initialized preset interface; the host side information comprises LVDS signals, REF _ CLK signals, SYNC signals and TRIGGER signals, and REF _ CLK is a reference clock signal. The LVDS signal group comprises links in the TX direction and the RX direction, a serial transmission protocol adopts the Xilinx Aurora8B/10B protocol, four channel number selections of 1x/2x/4x/8x are supported in the two directions, and asymmetric channel number selection is supported; the REF _ CLK is a reference clock signal, the frequency of the REF _ CLK is fixed to 25MHz, and the REF _ CLK is used for a reference clock for serial transmission and receiving at a slave end; the TRIGGER signal is a TRIGGER signal and is used for the slave to quickly inform the host of an independent signal; the SYNC signal is a synchronous signal and is used for accurate synchronization among a plurality of DashLink interfaces.
Controlling the communication between a slave end and a host end of a preset interface according to the host end information;
the preset interface adopts the embedded system communication interface.
In some specific embodiments, the DashLink interface definition is as shown in table 1:
TABLE 1
By the definition of the above table 1, as shown in fig. 2, the application process is as follows: on an I2C bus, a host side can acquire information of a DashLink Slave side through an I2 CMmaster interface and an I2C Slave interface of a Slave side, and can complete control and configuration functions of the DashLink Slave side, so that initialization and control of the DashLink side are realized; the REF _ CLK/SYNC/TRIGGER adopts an independent single-ended signal, the REF _ CLK is a reference clock signal, the frequency is fixed to 25MHz, the REF _ CLK is provided by a host end and used for a reference clock transmitted and received by serial transmission at the slave end, the TRIGGER signal is a TRIGGER signal, the TRIGGER signal is from the slave end to the host end and used for the slave to quickly inform an independent signal of the host, and the SYNC signal is a synchronous signal and used for accurate synchronization among a plurality of DashLink interfaces from the host end to the slave end; the LVDS signal group comprises links in two directions of TX and RX, a serial transmission protocol adopts an Aurora8B/10B protocol of Xilinx, four channel number selections of 1x/2x/4x/8x are supported in the two directions, and asymmetric channel number selection is supported.
In summary, the embodiments of the present invention have the following advantages:
the first point is as follows: because the embodiment supports the asymmetry of the number of full-duplex data channels, in the actual process, if the bandwidth of unidirectional 10Gbps needs to be met, only 23 pins are needed, and if the bandwidth is not needed to be high, the number of pins can be further reduced by selecting the proper number of channels according to the requirement;
and a second point: the transmission protocol of the embodiment belongs to lightweight, has distinct layers, and has a single logic entity unit in each layer, so that a clear structure is obtained, the restriction of software is reduced, the efficiency is improved, and the system cost is reduced;
and a third point: the interface of the embodiment can complete the interconnection inside the case, between the back panel chip and the chip, and between the panels, thereby satisfying a large number of embedded scene application functions.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An embedded system communication interface, comprising: the method comprises the following steps:
the logic layer is used for defining all communication protocols and communication protocol packet formats;
a transport layer including a data channel and an auxiliary channel for defining a single common transport layer and including a buffer for transmission between the logical layer and the physical layer;
and the physical layer is used for defining interface information, and the interface information comprises a communication signal and an interface protocol corresponding to the communication signal.
2. The embedded system communication interface of claim 1, wherein: the transmission of the auxiliary channel of the transmission layer comprises a write operation cache and a read operation cache of I2C; the data channel of the transmission layer comprises a message buffer and a data stream buffer.
3. An embedded system communication interface according to claim 2, wherein: the cache mode adopts a FIFO mode.
4. An embedded system communication interface according to claim 2, wherein: the logic layer comprises integrated management of the auxiliary channel, messages, flow control and data flow of the data channel; wherein the content of the first and second substances,
the integrated management of the auxiliary channel is used for carrying out initialization and configuration management;
the message of the data channel is used for transmitting the message, so that the host computer and the slave computer can interact;
a flow control for controlling transmission of a data stream;
and the data stream is used for realizing the transmission logic of the data stream.
5. The embedded system communication interface of claim 4, wherein: the initialization and configuration management specifically includes:
initialization and configuration management are performed through the read-write operation function of the I2C protocol.
6. The embedded system communication interface of claim 1, wherein: the communication signals comprise an I2C signal, an LVDS signal group, a clock signal, a trigger signal and a synchronous signal; the I2C signal and the LVDS signal set both use a serial transmission protocol.
7. The embedded system communication interface of claim 6, wherein: the I2C signal and the LVDS signal set both adopt a serial transmission protocol, which specifically includes:
the serial transmission protocol of the I2C signal is an I2C protocol;
the serial transmission protocol of the LVDS signal group is Aurora8B/10B protocol.
8. The embedded system communication interface of claim 6, wherein: the clock signal, the trigger signal and the synchronous signal are all single-ended signals.
9. The embedded system communication interface of claim 6, wherein: the frequency of the clock signal is a fixed frequency, and the fixed frequency is 25 MHz.
10. A communication method of an embedded system is characterized in that: the method comprises the following steps:
acquiring slave terminal information of a preset interface through the preset interface;
initializing a preset interface according to slave terminal information;
acquiring host end information of the initialized preset interface;
controlling the communication between a slave end and a host end of a preset interface according to the host end information;
the preset interface is an embedded system communication interface as claimed in any one of claims 1 to 9, and the host side information includes a clock signal, a trigger signal and a synchronization signal.
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