CN206594657U - The serial transceiver controllers of multichannel UART based on bus communication - Google Patents
The serial transceiver controllers of multichannel UART based on bus communication Download PDFInfo
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- CN206594657U CN206594657U CN201720288082.3U CN201720288082U CN206594657U CN 206594657 U CN206594657 U CN 206594657U CN 201720288082 U CN201720288082 U CN 201720288082U CN 206594657 U CN206594657 U CN 206594657U
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Abstract
The utility model discloses a kind of serial transceiver controllers of multichannel UART based on bus communication, including processor CPU, FPGA internal logic unit, the processor CPU carries out bus communication with FPGA internal logic units and is connected, data for handling FPGA internal logic units, the FPGA internal logic units carry out serial communication with outside multichannel UART transceivers again and are connected, the data of the multichannel UART transceivers for reading and handling outside.The utility model is by extending a fpga chip and changing its internal logic structure, so that the UART connections of a control chip and multichannel carry out serial communication, the technical scheme being connected instead of original multiple 16C554 chips with multichannel UART serial ports, save production cost, follow-up HardwareUpgring is facilitated, solves and is taken using the bus produced by multi-chip and collision problem.
Description
Technical field
The utility model is related to electric and electronic technical field, and in particular to a kind of multichannel UART strings based on bus communication
Row transceiver controller.
Background technology
The metering and billing terminal of electricity consumption side is mainly included：The equipment such as concentrator, electric energy meter, collector, plant stand terminal.These
The data reading system of equipment room and communication, are all by RS-485 interfaces.The equipment of terminal room interconnection is more, while again to communication
Speed there are certain requirements, and this quantity to RS-485 passages proposes requirement.Such as：Plant stand terminal, its RS-485 paths are up to
20 passages.For the equipment based on ARM platform developments, the UART serial communication interfaces typically 5-7 that processor is carried
Individual passage, the requirement of 20 road serial communication interfaces is not reached much.Equipment vendors generally use extended mode in hardware design,
To reach the purpose of multichannel UART serial transceivers.Common extended mode is many using UART Universal Asynchronous Receiver Transmitter 16C554 progress
Passage extends.
Multichannel UART transceivers are extended by the way of 16C554, when requiring to reach more than 16 transceiver channels, plate
Need to place more than 4 chips (monolithic only possesses 4 passage UART).Design complexity is so considerably increased, PCB cloth is added
Line difficulty.Because multiple chips of extension need to increase the components such as the power supply of matching, peripheral circuit, the reliable of product is reduced
Property, maintainability.Simultaneously because the chip needed to use is more, the cost of product is added, is unfavorable for product competitiveness in the market.
Utility model content
In view of this, in order to solve above mentioned problem of the prior art, bus communication is based on the utility model proposes one kind
The serial transceiver controllers of multichannel UART.
The utility model is solved the above problems by following technological means：
A kind of serial transceiver controllers of multichannel UART based on bus communication, including processor CPU, FPGA internal logic
Unit；
The processor CPU carries out bus communication with FPGA internal logic units and is connected, for handling FPGA internal logics
The data of unit；
The FPGA internal logic units carry out serial communication with outside multichannel UART transceivers again and are connected, for reading
And handle the data of the multichannel UART transceivers of outside.
Further, the FPGA internal logic units include bus data read-write cell, channel selection unit, logic control
Unit processed, data buffer storage unit, file distributing unit, at least one simulation 16C554 asynchronous serial port unit；
The processor CPU carries out bus communication with FPGA internal logic units and is connected, for handling FPGA internal logics
The data of unit；
The bus data read-write cell respectively with processor CPU, channel selecting and logic control element, data buffer storage and
File distributing unit carries out bus communication connection, the read-write sequence for meeting processor CPU；
The channel selecting and logic control element carry out communication link with each simulation 16C554 asynchronous serial ports unit respectively
Connect, for selecting the passage in each simulation 16C554 asynchronous serial port units, for controlling each simulation 16C554 different
The data flow of serial port unit is walked, makes data flow in multichannel while carrying out avoiding dislocation during data transmit-receive；
The data buffer storage and file distributing unit carry out communication link with each simulation 16C554 asynchronous serial ports unit respectively
Connect, for bus data read-write cell received data, simulation 16C554 asynchronous serial port units received data to be carried out
Caching, extremely simulates the data distribution of data buffer area for the control flow according to channel selecting and logic control element
The corresponding functional block of 16C554 asynchronous serial port units；
The simulation 16C554 asynchronous serial ports unit is used for the function of the 16C554 chips of mock standard.
Further, each simulation 16C554 asynchronous serial ports unit includes receiving module, sending module, baud rate hair
Raw device, status control module and configuration register, interrupt logic control module, data/address bus buffer module；
The processor CPU is communicatively coupled with interrupt logic control module, data/address bus buffer module respectively；
The Baud rate generator carries out bus communication with receiving module, sending module, data/address bus buffer module respectively
Connection, the accuracy of data is received for improving, and reduces the bit error rate；
The data/address bus buffer module carries out bus communication with receiving module, sending module, Baud rate generator respectively
Connection, the data to be sent for distributing each UART passage receive each UART passage reception data to be uploaded, and distribution is each
The divide ratio of individual UART passages and Baud rate generator；
The interrupt logic control module is communicatively coupled with receiving module, sending module, Baud rate generator respectively,
For judging to receive or sending whether data activation threshold value or are overflowed so as to performing corresponding interrupt mode, for judging to send and
Whether normal work is so as to performing corresponding interrupt mode for the state controller of receiving module and sending module when receiving data；
The status control module and configuration register are carried out with receiving module, sending module, Baud rate generator respectively
Communication connection, the register control table for defining correlation, makes processor CPU configure FPGA internal logic lists by external bus
The function of member obtains status information；
Further, the receiving module includes FIFO receivers, receives buffer register, receive shift register, connect
Receive state controller；
The FIFO receivers are communicatively coupled with receiving buffer register, receiving shift register respectively, for setting
Put the data depth that triggering is interrupted；
The UART passages that shift register is received respectively with outside UART transceivers, reception state controller are carried out
Communication connection, for inputting RX data from the UART passages of outside UART transceivers.
It is described reception buffer register respectively with data/address bus buffer module, FIFO receivers, FIFO transmitters, baud rate
Generator carry out bus communication connection, for make the reception pattern receptions Data Matching bus transmission rate after output,
And produce the Read-write Catrol flag signal of the data/address bus buffer module；
The reception state controller is communicatively coupled with Baud rate generator, reception shift register respectively, is used for
Control receives the state of shift register, matches the DRP data reception process under different baud rates, and the RX signals received are originated
Position, data bit, parity check bit, stop position are detected；
The status control module and configuration register are shifted with FIFO receivers, reception buffer register, reception respectively
Register, reception state controller are communicatively coupled；
The interrupt logic control module respectively with FIFO receivers, receive buffer register, receive shift register, connect
State controller is received to be communicatively coupled；
Further, the sending module includes FIFO transmitters, sends holding register, sends shift register, hair
Send state controller；
It is described transmission holding register respectively with FIFO transmitters, send shift register be communicatively coupled, for from
FIFO transmitters take out 1Byte data, keep sending data, and are output to the transmission shift register, prevent the number sent
Misplaced according to order；
The FIFO transmitters are carried out with data/address bus buffer module, Baud rate generator, reception buffer register respectively
Bus communication is connected, for storing the depth data that the triggering configured by sending shift register is interrupted；
The transmission state controller is communicatively coupled with Baud rate generator, transmission shift register respectively, is used for
Control sends the state of shift register, matches the data transmission procedure under different baud rates, produces and sends TX data-signals
Start bit, parity check bit, stop position；
The UART passages that shift register is sent respectively with transmission state controller, outside UART transceivers are carried out
Communication connection, for directly exporting TX data to UART passages；
The status control module and configuration register are shifted with FIFO transmitters, transmission holding register, transmission respectively
Register, transmission state controller are communicatively coupled；
The interrupt logic control module respectively with FIFO transmitters, send holding register, send shift register, hair
State controller is sent to be communicatively coupled.
Compared with prior art, multichannel UART serial transceiver controller of the utility model based on bus communication, passes through
One fpga chip of extension simultaneously changes its internal logic structure, so that the UART connections of a control chip and multichannel are gone here and there
Port communications, the technical scheme being connected instead of original multiple 16C554 chips with multichannel UART serial ports, save production cost, side
Follow-up HardwareUpgring, solve and taken using the bus produced by multi-chip and collision problem.
Brief description of the drawings
, below will be to needed for embodiment description in order to illustrate more clearly of the technical scheme in the utility model embodiment
The accompanying drawing to be used is briefly described, it should be apparent that, drawings in the following description are only some realities of the present utility model
Example is applied, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is the structural representation of multichannel UART serial transceiver controller of the utility model based on bus communication；
Fig. 2 is the structural representation of simulation 16C554 asynchronous serial port units of the present utility model.
Embodiment
To enable above-mentioned purpose of the present utility model, feature and advantage more obvious understandable, below in conjunction with accompanying drawing and
The technical solution of the utility model is described in detail specific embodiment.It is pointed out that described embodiment is only
Only it is a part of embodiment of the utility model, rather than whole embodiments, based on the embodiment in the utility model, this area
The every other embodiment that those of ordinary skill is obtained under the premise of creative work is not made, belongs to the utility model
The scope of protection.
Embodiment
As shown in figure 1, a kind of serial transceiver controllers of multichannel UART based on bus communication, including processor CPU,
FPGA internal logic units；
The processor CPU carries out bus communication with FPGA internal logic units and is connected, for handling FPGA internal logics
The data of unit；
The FPGA internal logic units carry out serial communication with outside multichannel UART transceivers again and are connected, for reading
And handle the data of the multichannel UART transceivers of outside；
The FPGA internal logic units include bus data read-write cell, channel selection unit, logic control element, number
According to buffer unit, file distributing unit, at least one simulation 16C554 asynchronous serial port unit；
The processor CPU carries out bus communication with FPGA internal logic units and is connected, for handling FPGA internal logics
The data of unit；
The bus data read-write cell respectively with processor CPU, channel selecting and logic control element, data buffer storage and
File distributing unit carries out bus communication connection, the read-write sequence for meeting processor CPU；
The channel selecting and logic control element carry out communication link with each simulation 16C554 asynchronous serial ports unit respectively
Connect, for selecting the passage in each simulation 16C554 asynchronous serial port units, for controlling each simulation 16C554 different
The data flow of serial port unit is walked, makes data flow in multichannel while carrying out avoiding dislocation during data transmit-receive；
The data buffer storage and file distributing unit carry out communication link with each simulation 16C554 asynchronous serial ports unit respectively
Connect, for bus data read-write cell received data, simulation 16C554 asynchronous serial port units received data to be carried out
Caching, extremely simulates the data distribution of data buffer area for the control flow according to channel selecting and logic control element
The corresponding functional block of 16C554 asynchronous serial port units；
The simulation 16C554 asynchronous serial ports unit is used for the function of the 16C554 chips of mock standard.
As shown in Fig. 2 each simulation 16C554 asynchronous serial ports unit includes receiving module, sending module, baud rate
Generator, status control module and configuration register, interrupt logic control module, data/address bus buffer module；
The processor CPU is communicatively coupled with interrupt logic control module, data/address bus buffer module respectively；
The Baud rate generator carries out bus communication with receiving module, sending module, data/address bus buffer module respectively
Connection, the accuracy of data is received for improving, and reduces the bit error rate, the reception clock of Baud rate generator is the 16 of standard clk
Times, using the sampled data of intermediate time；
The data/address bus buffer module carries out bus communication with receiving module, sending module, Baud rate generator respectively
Connection, the data to be sent for distributing each UART passage receive each UART passage reception data to be uploaded, and distribution is each
The divide ratio of individual UART passages and Baud rate generator；
The interrupt logic control module is communicatively coupled with receiving module, sending module, Baud rate generator respectively,
For judging to receive or sending whether data activation threshold value or are overflowed so as to performing corresponding interrupt mode, for judging to send and
Whether normal work is so as to performing corresponding interrupt mode for the state controller of receiving module and sending module when receiving data；
Reach that the data depth of setting then triggers reception data outage pattern when receiving data FIFO, as transmission data FIFO
Reach that the data depth of setting then triggers transmission data outage pattern, then trigger data overflows interruption mould when receiving data and overflowing
Formula, when the state controller cycle count of receiving module and sending module is overflowed, then trigger data overflows interrupt mode；
The status control module and configuration register are carried out with receiving module, sending module, Baud rate generator respectively
Communication connection, the register control table for defining correlation, makes processor CPU configure FPGA internal logic lists by external bus
The function of member obtains status information；
The status information is such as：Baud rate control, interruption enable control, receive data-triggered depth, data parity check
Position configuration, the configuration of data frame stop position, data overflow verification；
The receiving module includes FIFO receivers, receives buffer register, receives shift register, reception state control
Device；
The FIFO receivers are communicatively coupled with receiving buffer register, receiving shift register respectively, for setting
Put the data depth that triggering is interrupted；
After the data stack of FIFO receivers is less than the data depth set, triggering is received into interrupt signal, it is described
The maximum storage depth of FIFO receivers is 16Byte；
The UART passages that shift register is received respectively with outside UART transceivers, reception state controller are carried out
Communication connection, for inputting RX data from the UART passages of outside UART transceivers.
It is described reception buffer register respectively with data/address bus buffer module, FIFO receivers, FIFO transmitters, baud rate
Generator carry out bus communication connection, for make the reception pattern receptions Data Matching bus transmission rate after output,
And produce the Read-write Catrol flag signal of the data/address bus buffer module；
The reception state controller is communicatively coupled with Baud rate generator, reception shift register respectively, is used for
Control receives the state of shift register, matches the DRP data reception process under different baud rates, and the RX signals received are originated
Position, data bit, parity check bit, stop position are detected；
The status control module and configuration register are shifted with FIFO receivers, reception buffer register, reception respectively
Register, reception state controller are communicatively coupled；
The interrupt logic control module respectively with FIFO receivers, receive buffer register, receive shift register, connect
State controller is received to be communicatively coupled；
The sending module includes FIFO transmitters, sends holding register, send shift register, send state control
Device；
It is described transmission holding register respectively with FIFO transmitters, send shift register be communicatively coupled, for from
FIFO transmitters take out 1Byte data, keep sending data, and are output to the transmission shift register, prevent the number sent
Misplaced according to order；
The FIFO transmitters are carried out with data/address bus buffer module, Baud rate generator, reception buffer register respectively
Bus communication is connected, for storing the depth data that the triggering configured by sending shift register is interrupted；
The depth data of the FIFO transmitters is 16Byte；
The transmission state controller is communicatively coupled with Baud rate generator, transmission shift register respectively, is used for
Control sends the state of shift register, matches the data transmission procedure under different baud rates, produces and sends TX data-signals
Start bit, parity check bit, stop position；
The UART passages that shift register is sent respectively with transmission state controller, outside UART transceivers are carried out
Communication connection, for directly exporting TX data to UART passages；
The status control module and configuration register are shifted with FIFO transmitters, transmission holding register, transmission respectively
Register, transmission state controller are communicatively coupled；
The interrupt logic control module respectively with FIFO transmitters, send holding register, send shift register, hair
State controller is sent to be communicatively coupled.
Compared with prior art, multichannel UART serial transceiver controller of the utility model based on bus communication, passes through
One fpga chip of extension simultaneously changes its internal logic structure, so that the UART connections of a control chip and multichannel are gone here and there
Port communications, the technical scheme being connected instead of original multiple 16C554 chips with multichannel UART serial ports, save production cost, side
Follow-up HardwareUpgring, solve and taken using the bus produced by multi-chip and collision problem.
Embodiment described above only expresses several embodiments of the present utility model, and it describes more specific and detailed,
But therefore it can not be interpreted as the limitation to the utility model the scope of the claims.It should be pointed out that for the common of this area
For technical staff, without departing from the concept of the premise utility, various modifications and improvements can be made, these all belong to
In protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.
Claims (5)
1. a kind of serial transceiver controllers of multichannel UART based on bus communication, it is characterised in that including processor CPU,
FPGA internal logic units；
The processor CPU carries out bus communication with FPGA internal logic units and is connected；
The FPGA internal logic units carry out serial communication with outside multichannel UART transceivers again and are connected.
2. the multichannel UART serial transceiver controllers according to claim 1 based on bus communication, it is characterised in that institute
Stating FPGA internal logic units includes bus data read-write cell, channel selection unit, logic control element, data buffer storage list
Member, file distributing unit, at least one simulation 16C554 asynchronous serial port unit；
The processor CPU carries out bus communication with FPGA internal logic units and is connected, for handling FPGA internal logic units
Data；
The bus data read-write cell respectively with processor CPU, channel selecting and logic control element, data buffer storage and data
Dispatching Unit carries out bus communication connection；
The channel selection unit is electrically connected with each simulation 16C554 asynchronous serial port units respectively；
The channel selecting and logic control element are communicatively coupled with each simulation 16C554 asynchronous serial port units respectively；
The data buffer storage and file distributing unit are communicatively coupled with each simulation 16C554 asynchronous serial port units respectively.
3. the multichannel UART serial transceiver controllers according to claim 2 based on bus communication, it is characterised in that institute
State each simulation 16C554 asynchronous serial ports unit including receiving module, sending module, Baud rate generator, status control module and
Configuration register, interrupt logic control module, data/address bus buffer module；
The processor CPU is communicatively coupled with interrupt logic control module, data/address bus buffer module respectively；
The Baud rate generator carries out bus communication with receiving module, sending module, data/address bus buffer module respectively and is connected；
The data/address bus buffer module carries out bus communication with receiving module, sending module, Baud rate generator respectively and is connected；
The interrupt logic control module is communicatively coupled with receiving module, sending module, Baud rate generator respectively；
The status control module and configuration register are communicated with receiving module, sending module, Baud rate generator respectively
Connection.
4. the multichannel UART serial transceiver controllers according to claim 3 based on bus communication, it is characterised in that institute
Stating receiving module includes FIFO receivers, reception buffer register, reception shift register, reception state controller；
The FIFO receivers are communicatively coupled with receiving buffer register, receiving shift register respectively；
UART passages, the reception state controller that shift register is received respectively with outside UART transceivers is communicated
Connection；
The reception buffer register occurs with data/address bus buffer module, FIFO receivers, FIFO transmitters, baud rate respectively
Device carries out bus communication connection；
The reception state controller is communicatively coupled with Baud rate generator, reception shift register respectively；
The status control module and configuration register respectively with FIFO receivers, receive buffer register, receive shift LD
Device, reception state controller are communicatively coupled；
The interrupt logic control module respectively with FIFO receivers, receive buffer register, receive shift register, receive shape
State controller is communicatively coupled.
5. the multichannel UART serial transceiver controllers according to claim 3 based on bus communication, it is characterised in that institute
Stating sending module includes FIFO transmitters, transmission holding register, transmission shift register, transmission state controller；
The transmission holding register is communicatively coupled with FIFO transmitters, transmission shift register respectively；
The FIFO transmitters enter row bus with data/address bus buffer module, Baud rate generator, reception buffer register respectively
Communication connection；
The transmission state controller is communicatively coupled with Baud rate generator, transmission shift register respectively；
The UART passages that shift register is sent respectively with transmission state controller, outside UART transceivers are communicated
Connection；
The status control module and configuration register respectively with FIFO transmitters, send holding register, send shift LD
Device, transmission state controller are communicatively coupled；
The interrupt logic control module respectively with FIFO transmitters, send holding register, send shift register, send shape
State controller is communicatively coupled.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991947A (en) * | 2017-12-29 | 2018-05-04 | 上海应用技术大学 | A kind of solenoid-driven and its control method based on FPGA |
| CN109634901A (en) * | 2018-12-13 | 2019-04-16 | 上海芷锐电子科技有限公司 | A kind of data transmission system and its control method based on UART |
| CN111830874A (en) * | 2020-07-23 | 2020-10-27 | 湖南中车时代通信信号有限公司 | Multi-channel serial digital signal transmission control device and method for train control system |
| CN112039745A (en) * | 2020-09-17 | 2020-12-04 | 广东高云半导体科技股份有限公司 | CAN bus communication control system and communication system |
| CN112395230A (en) * | 2020-12-21 | 2021-02-23 | 太原智林信息技术股份有限公司 | UART interface extension circuit based on programmable logic device |
| CN113406913A (en) * | 2021-07-12 | 2021-09-17 | 上海汇珏网络通信设备股份有限公司 | Cache circuit and method of electric power composite bus |
| CN113609067A (en) * | 2021-06-25 | 2021-11-05 | 天津津航计算技术研究所 | Implementation system of 32-channel RS485 interface card |
| CN114490474A (en) * | 2021-12-28 | 2022-05-13 | 武汉微创光电股份有限公司 | System for realizing extension of multi-path UART (universal asynchronous receiver/transmitter) interface through CPLD (complex programmable logic device) |
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2017
- 2017-03-22 CN CN201720288082.3U patent/CN206594657U/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991947A (en) * | 2017-12-29 | 2018-05-04 | 上海应用技术大学 | A kind of solenoid-driven and its control method based on FPGA |
| CN109634901A (en) * | 2018-12-13 | 2019-04-16 | 上海芷锐电子科技有限公司 | A kind of data transmission system and its control method based on UART |
| CN111830874A (en) * | 2020-07-23 | 2020-10-27 | 湖南中车时代通信信号有限公司 | Multi-channel serial digital signal transmission control device and method for train control system |
| CN112039745A (en) * | 2020-09-17 | 2020-12-04 | 广东高云半导体科技股份有限公司 | CAN bus communication control system and communication system |
| CN112039745B (en) * | 2020-09-17 | 2021-06-22 | 广东高云半导体科技股份有限公司 | CAN bus communication control system and communication system |
| CN112395230A (en) * | 2020-12-21 | 2021-02-23 | 太原智林信息技术股份有限公司 | UART interface extension circuit based on programmable logic device |
| CN113609067A (en) * | 2021-06-25 | 2021-11-05 | 天津津航计算技术研究所 | Implementation system of 32-channel RS485 interface card |
| CN113609067B (en) * | 2021-06-25 | 2024-03-19 | 天津津航计算技术研究所 | System for realizing 32-channel RS485 interface card |
| CN113406913A (en) * | 2021-07-12 | 2021-09-17 | 上海汇珏网络通信设备股份有限公司 | Cache circuit and method of electric power composite bus |
| CN114490474A (en) * | 2021-12-28 | 2022-05-13 | 武汉微创光电股份有限公司 | System for realizing extension of multi-path UART (universal asynchronous receiver/transmitter) interface through CPLD (complex programmable logic device) |
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Address after: 510000 Nancun Town, Panyu District, Guangzhou City, Guangdong Province, 6 1705 office buildings 383 North Panyu Avenue Patentee after: Guangzhou shining Electric Technology Co., Ltd. Address before: 511430 Dashi Stage 715, 105 National Road, Panyu District, Guangzhou, Guangdong 511 Patentee before: Guangzhou shining Electric Technology Co., Ltd. |