CN102354171B - Remote matrix switch control module having RS422 interface - Google Patents
Remote matrix switch control module having RS422 interface Download PDFInfo
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Abstract
The invention relates to a remote matrix switch control module having an RS422 interface. The module comprises two hardware submodules, which are an RS422 submodule and a matrix switch control submodule. Cores of the invention are as follows: a remote control based on an RS422 bus and flexible switching of large-scale matrix switches. The RS422 submodule comprises an RS422 isolation communication unit, an FPGA protocol coding unit and a buffer driving unit. And the matrix switch control submodule is composed of a CPLD protocol decoding unit, a column signal driving unit, a row signal driving unit and a relay array unit. According to the module provided in the invention, performances are stable; reliability is high; besides, the module has an RS422 bus interface and a communication rate can reach 2MB/s; therefore, the module is suitable for general signal switch and route selection and external device control and the like. Moreover, a switching demand on a switching value by traditional testing equipment can be met; meanwhile, the module can be widely applied to remote testing platforms including a temperature cabinet, a vibration table, and a rotary table and the like; and thus, deficiency based on PCI, CPCI and PXI bus interface equipment can be made up.
Description
Technical field
The present invention relates to a kind of long-range matrix switch control module of the RS422 of having interface.This module adopts the RS422 bus to carry out Long-distance Control, by matrix switch, measured signal is switched.The RS422 bus has also overcome the dependence to conventional P CI, PXI, CPCI interfacing equipment for Long-distance Control at a high speed provides reliable solution.Utilize the matrix switch control module, any one input can be connected in mode single or combination with output, thereby expand greatly the dirigibility of testing.The invention belongs to computer-aided test and field of automatic testing.
Background technology
Matrix switch as its name suggests, refer to that structure is the switch product of row (Row) row (Column) cross arrangement, its characteristics are that each node (CrossPoint) connects row/row, each node can operate separately, can realize the route of signal by the various combination that node is set.The use of matrix switch is very flexible, is the maximum product of kind in present programmed switch product, is widely used in fields such as automotive electronics, semiconductor test, Aero-Space.
The concept of matrix is quoted the concept of the linear algebra in high number, refer generally in the situation that the multichannel input has the output of multichannel to select, form matrix structure, be the output of each road all can from different input signals " short circuit ", the output of every road can only be connected the input of a certain road, but the input of a certain road all can (simultaneously) be connected different output.The function of matrix switch is in the situation that the multiple signals input can select multichannel (comprising 1 tunnel) signal to export, the selection of settling signal independently as required.
Be exactly to select on switching principle, the mode of selection has a variety of, the most exactly signal wire directly is connected together.The second way is to utilize relay to complete selection, utilizes the break-make of level pilot relay, can complete between output line and input signal disconnection with connect, but the also selection of settling signal.The third mode is according to circuit theory, utilizes the conducting of chip internal circuit and closes and connect and turn-off, and can control by level the selection of settling signal.
Relay mode and chip form respectively have relative merits.
relay mode: if do not consider the circuit part that Input matching and output drive, it is consistent with connection mode, to carry out connecting and disconnecting by physical contact, on this angle, (contact resistance and reaction time are arranged at most) that there is no what index concept, therefore technical indicator is good and cheap, its shortcoming is less stable, by physical contact after all, relay has certain life-span, in principle, the sound when being arranged, is arranged in 80,000 average failure-free operation and operation, due to wiring board cabling reason, that can not do is larger, seem high-grade not.
Chip form: owing to connecting by circuit and turn-offing, there is technical indicator (in the situation that Input matching drives the same with output) in chip itself, therefore want the safeguards technique index, will select special-purpose switching chip, therefore price is higher, but good stability, the matrix size that can form is larger.
RS422 standard full name is " electrical specification of balanced voltage digital interface circuit ", and it has defined the characteristic of interface circuit.Because receiver adopts high input impedance and sends the driver driving force stronger than RS232, therefore allow to connect a plurality of receiving nodes on same transmission line, can connect at most 10 nodes.An i.e. main equipment (Master), all the other are from equipment (Salve), from not communicating by letter between equipment, so RS422 supports point-to-points two-way communication.Receiver input impedance is 4K, therefore the maximum load capability of making a start is 10 * 4K+100 Ω (terminating resistance).The RS422 four-wire interface is owing to adopting independent sending and receiving passage, therefore needn't control data direction, between each device, any necessary signal exchange all can realize by software mode (XON/XOFF shakes hands) or hardware mode (a pair of independent twisted-pair feeder).The maximum transmission distance of RS422 is 4000 feet (approximately 1219 meters), and peak transfer rate is 10Mb/s.
The RS422 bus is owing to having the various features such as transmission range is long, baud rate is adjustable, speed is fast, antijamming capability is strong, so have a wide range of applications in test and control field.
FPGA (Field Programmable Gate Array) field programmable gate array, it is the product that further develops on the basis of the programming devices such as PAL, GAL, EPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome again the limited shortcoming of original programming device gate circuit number.
CPLD (Complex Programmable Logic Device) CPLD is the device that develops out from PAL and GAL device, and scale is large comparatively speaking, and complex structure belongs to the large scale integrated circuit scope.It is a kind of user according to needs separately and the digital integrated circuit of constitutive logic function voluntarily.It has flexible in programming, integrated level is high, the cycle of designing and developing is short, the scope of application is wide, developing instrument is advanced, design and manufacture cost is low, require low, standardized product to need not the characteristics such as test, strong security, price be popular to deviser's hardware experience, can realize fairly large circuit design, therefore be widely used among the prototype and production (generally below 10000) of product.
In Test Application, the most complicated switch problem is usually directed to " simply " on-the-spot parts, voltage, and electric current, short circuit or open circuit, and by a large amount of input data, the equipment of testing is controlled these aspects.Test itself is also uncomplicated, but the quantity of test and access point causes complicated test problem.Along with access point in test macro becomes increasingly complex, utilize matrix switch to carry out suitable arrangement to reduce the switch cost in test macro to test point, just can reach best cost benefit.
Existing matrix switch control module on market be the control for local side mostly, and scale is less, can't satisfy the demand based on remote measurements such as incubator, turntables; Simultaneously, most products is based on the interface module of PXI, VIX, and very high to equipment requirement itself, general applicability is not strong.Therefore, develop a large-scale, based on the matrix switch control module of Long-distance Control, have very high use value.Adopt the RS422 bus can grow the communication of distance, for Long-distance Control (20 meters to 50 meters) provides solution effectively, and the speed of 2MB/s has well satisfied the real-time of process control; The versatility of RS422 bus is very strong, only needs equipment to have the RS422 interface and can use the present invention; Matrix switch control module of the present invention (all can control separately by 8*16 matrix, each contact, can expand more extensive matrix) be greatly improved than traditional scale and dirigibility, simultaneously, adopt FPGA and CPLD to carry out logic control, both simplified the complexity of design, the dirigibility that has improved again product.
Summary of the invention
The object of the present invention is to provide a kind of long-range matrix switch control module of the RS422 of having interface, be used for simplifying the switching system of testing apparatus, reduce the switch cost of test macro, based on the RS422 bus, for Long-distance Control provides solution effectively.It can with the access point of to-be-measured cell (DUT) be connected resource and connect, and to testing equipment, thus the effectiveness of this part function in verifying apparatus.
A kind of long-range matrix switch control module with RS422 interface of the present invention comprises two submodules:
1) RS422 submodule: this module specifically comprises three signal processing units
A) RS422 isolated communication unit;
B) FPGA protocol code unit;
C) buffering driver element
2) matrix switch is controlled submodule: this module specifically comprises four signal processing units
A) CPLD protocol-decoding unit
B) column signal driver element
C) go signal driving unit
D) relay array unit
RS422 isolated communication unit is made of RS422 transceiver and RS422 protocol chip.The RS422 transceiver is converted to the differential signal (being the RS422 steering order) of RS422 the single-ended Transistor-Transistor Logic level signal that is complementary with the RS422 protocol chip, realizes simultaneously the electrical isolation of difference and single-ended signal.The RS422 protocol chip receives the serial data from the RS422 transceiver, is converted into parallel data and is stored in chip internal reception FIFO and produces interruption.
FPGA protocol code unit coordinates its peripheral circuit to consist of take FPGA as core, uses Verilog HDL Programming with Pascal Language to realize.FPGA receives the interrupt instruction from the RS422 protocol chip, reads the data (RS422 steering order) in its reception FIFO, and data conversion storage is entered in the RAM of FPGA inside; FPGA processes the data in RAM, according to communication protocol, produces the matrix switch steering order that matrix switch is controlled submodule.
The buffering driver element drives chip by buffering and consists of.The signal (matrix switch steering order) of FPGA output is the LVTTL level signal, after buffering drives chip, is converted to the Transistor-Transistor Logic level signal that is complementary with far-end CPLD.
CPLD protocol-decoding unit coordinates its peripheral circuit to consist of take CPLD as core, receives the matrix switch steering order that issues from the RS422 submodule, and carries out protocol-decoding, and then produce the column/row control signal of relay array.
The relay array unit is made of the relay array of 8*16, often classifies 8 as, 16 of every behaviors, and each relay all is positioned at the place, point of crossing of row/row, and the positive and negative two ends of relay coil are controlled by corresponding column signal and row signal respectively.During and if only if relay coil forward conduction, relay contact closure.The normally opened contact of relay connects the test lead of measurand.The stationary contact that is positioned at the relay of odd-numbered line (1,3,5,7 row) in array connects an end of testing tool, and the stationary contact that is positioned at the relay of even number line (0,2,4,6 row) connects the other end (carrying out electrical interconnection by binding post and testing tool) of testing tool.Long-range RS422 instruction pilot relay array, corresponding two relays of gating, (two relays of gating lay respectively at odd-numbered line and even number line can to realize testing tool and measurand interconnected, i.e. two two ends that stationary contact is received testing tool, two normally opened contacts are received the two ends of measurand).
The column signal driver element is take 16 P-channel field-effect transistor (PEFT) pipes as core, and 16 road row control signals that CPLD is exported drive.Every road signal controlling one row (8) relay.The grid of each field effect transistor connects the output terminal of corresponding CPLD, and drain electrode connects the anode of the relay coil of respective column, and source electrode connects the 5V power supply.
The row signal driving unit is take 8 NPN type Darlington transistors as core, and 8 road row control signals that CPLD is exported drive.Every road signal controlling delegation (16) relay.The base stage of each Darlington transistor connects the output terminal of corresponding CPLD, and collector connects the negative terminal of corresponding row relay coil, grounded emitter.
Wherein, the RS422 submodule has the signal gang socket of DB15, and the RS422 steering order that issues for receiving remote equipment provides communication interface.
The FPGA of RS422 submodule controls submodule CPLD with matrix switch and is connected by the gang socket of DB25 signal, communicates with 8 bit parallel buses.
For 8*16 relay array unit (totally 128 relays), be divided into 16 groups (every group of 8 relays) by row, it is divided into 4 groups (every group of 2 relays lay respectively at odd-numbered line and even number line) by being about to again, forms 64 relay groups.Two normally opened contacts of every group relay are connected, and namely form altogether 64 test points, and each test point connects an end of measurand, draw by the signal gang socket of DB78, are used for carrying out electrical interconnection with measurand.
Wherein, all corresponding 2 relays of each test point, and lay respectively at odd-numbered line and even number line, namely stationary contact is received respectively the two ends of testing tool.By relay gate, the test point of measurand can be received any end of testing tool.
Wherein, data in described FPGA internal RAM are the RS422 steering order, totally 5 bytes, first byte is the address that matrix switch is controlled submodule, second and third byte is the ranks steering order that first group of matrix switch controlled submodule, and fourth, fifth byte is the ranks steering order that second group of matrix switch controlled submodule.
Wherein, described FPGA externally exports as frame data take 8 bit parallel data (1 byte), communicates with CPLD.
Wherein, the frame head of the described FPGA data stream of communicating by letter with CPLD is the reset instruction that matrix switch is controlled submodule.This instruction has two frame data: the first frame is that 11010101, the second frames are 10101010.
Wherein, the form of the Frame that described FPGA communicates by letter with CPLD (1 byte) is: low three (bit0-bit2) is for exercising the energy signal, middle four (bit3-bit6) are the row enable signal, and most significant digit (bit7) is the read signal, that is reads enable signal.
Wherein, the time interval of described FPGA every frame data of communicating by letter with CPLD is 2.5us (100 FPGA clock).
Wherein, described relay is the midget relay AGN2004H that PANASONIC is produced.
Wherein, in described row signal driving unit, the output terminal of Darlington transistor all has the pull-up resistor of 75 Ω.
A kind of long-range matrix switch control module with RS422 interface of the present invention, its advantage and effect are: utilize the RS422 bus to provide reliable solution for Long-distance Control at a high speed, the traffic rate of 2MB/s has well guaranteed the real-time of test macro.It is many that the present invention has a number of channels, and low on-resistance, switch bear the characteristics such as power is large, matrix structure flexible form, are suitable for the control of general signaling switch, Route Selection, external devices and the aspects such as control of mid power signal.Utilize matrix switch to carry out suitable arrangement to test point, significantly reduced the complexity of switching system in the test macro, also reduced cost when improving maintainability.Simultaneously, adopt FPGA and CPLD programmable logic device (PLD) to carry out logic control, improved the dirigibility of product, reduced debugging difficulty.The present invention is simple in structure, very easy to use.
Description of drawings
Figure 1 shows that hardware global design block diagram of the present invention.
Figure 2 shows that the RS422 isolated communication Unit Design figure in Fig. 1.
Figure 3 shows that the FPGA protocol code Unit Design process flow diagram in Fig. 1.
Fig. 4 a, 4b are depicted as the auxiliary circuit design in Fig. 2.
Fig. 5 a, 5b are depicted as FPGA configuration module port definition in Fig. 4 a, 4b.
Figure 6 shows that the data layout in the CPLD protocol-decoding unit in Fig. 1.
Figure 7 shows that the fundamental diagram of the CPLD protocol-decoding unit finite state machine in Fig. 1.
Figure 8 shows that the concrete control chart of the relay array unit in Fig. 1.
Figure 9 shows that the concrete wiring diagram of the relay array unit in Fig. 1.
Figure 10 shows that the concrete structure figure of Darlington transistor in the relay array unit in Fig. 1.
In figure, concrete label is as follows:
101 102 FPGA protocol code unit, RS422 isolated communication unit
103 buffering driver element 104 CPLD protocol-decoding unit
105 column signal driver element 106 row signal driving unit
107 relay array unit 201 level switch modules
202 DC-DC insulating power supply module 203 RS422 transceivers
204 RS422 protocol chip 205 FPGA modules
301 RS422 protocol chip initialization module 302 RS422 protocol chip receive interruption modules
303 data conversion storage module 304 communication protocol coding modules
401 reset circuit module 402 FPGA configuration modules
501 fpga chip JTAG configured port definition 502 fpga chip AS configured port definition
801 column signal control module field effect transistor 802 row signaling control unit Darlington transistors
803 relay subelement 804 backward diodeds
The normally opened contact of stationary contact 902 relays of 901 relays
903 relay group 1,001 75 Ω pull-up resistors
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described further.
The present invention in conjunction with peripheral logical device, provides a kind of long-range matrix switch control module of the RS422 of having interface take FPGA and CPLD as core.
Please refer to accompanying drawing 1, a kind of long-range matrix switch control module with RS422 interface of the present invention comprises two hardware submodules: RS422 submodule and matrix switch are controlled submodule.The RS422 submodule comprises RS422 isolated communication unit 101, FPGA protocol code unit 102 and buffering driver element 103; Matrix switch is controlled submodule and is comprised CPLD protocol-decoding unit 104, column signal driver element 105, row signal driving unit 106 and relay array unit 107.
Described RS422 submodule and matrix switch are controlled submodule and are communicated by eight bit parallel buses.Issue the RS422 steering order by remote equipment, carry out electrical isolation through RS422 isolated communication 101 pairs of unit signal, serial RS422 data are converted to parallel data; Carry out data conversion storage by FPGA protocol code unit 102, and produce the matrix switch steering order according to the communication protocol coding; The matrix switch steering order of 103 pairs of FPGA outputs of buffering driver element cushions and drives and level conversion; By eight bit parallel buses, instruction arrives the far-end matrix switch and controls submodule; Carry out protocol analysis by 104 pairs of the unit instruction of CPLD protocol-decoding, obtain being listed as capable steering order; Carry out controlled quentity controlled variable output by column signal driver element 105, row signal driving unit 106, final operational relay array element 107, pilot relay contact break-make.
Please refer to accompanying drawing 2; for guaranteeing the electrical isolation isolation of product and testing apparatus; chosen the RS422 transceiver 203 with isolation features; the High-Speed RS 422 transceiver ADM2490E that AnalogDevices company produces; communication speed can reach 16Mbps; provide ± the 8kV esd protection, be applicable to high speed, the full-duplex communication of multicast communication circuit.The RS422 transceiver is converted to single-ended Transistor-Transistor Logic level signal with the differential signal of RS422 and inputs to FPGA, realizes simultaneously the electrical isolation of difference and single-ended signal.
Described RS422 protocol chip 204 has been chosen the SC28L202 that Philip company produces.This chip is independently protocol chip of binary channels, each passage is data bus and address bus and control signal wire separately and the FPGA sequential fit module by sharing all, carry out the sending and receiving of data, and complete the tasks such as control of traffic rate, communication data form.
Described RS422 protocol chip uses the external clock mode of operation, the 32M crystal oscillator that clock has selected KOAN company to produce, and highest communication speed can reach 2MB/s.
Described DC-DC insulating power supply module 202 has been selected the IF0505S-1W insulating power supply module of MORNSUN.
Described level switch module 201 is used for outside 5V voltage is converted into 3.3V voltage and 1.5V voltage.3.3V voltage is used for to most components and parts power supplies, 1.5V is used for the fpga chip kernel is powered.Select the AS2830 level transferring chip.Level transferring chip 3.3V and 1.5V input and output pin all are designed with decoupling capacitor, respectively comprise 1 10uF low frequency filtering electric capacity and 1 0.1uF high-frequency filter capacitor.
Described FPGA module 205 has been selected the FPGA:EP1C12F324C6N of the Cyclone series of altera corp's production.Clock is chosen for the 40M crystal oscillator that KOAN company produces.
Shown in Fig. 4 a, this reset circuit module 401 is controlled by 1 reset button, and pressing is that pin sets low, and produces reset signal.
Shown in Fig. 4 b, described FPGA configuration module 402 is used for realizing that the program to FPGA module 205 loads and on-line debugging.The FPGA configuration module is divided into JTAG and two kinds of patterns of AS.JTAG is the on-line debugging pattern, power on namely available, but power down information all loses JTAG download port pinout mistake! Do not find Reference source.Shown in 5a; AS is the program Solidification pattern, uses the EEPROM save routine, and the FPGA power down is not lost, and the rear FPGA that powers on can read configurator from EEPROM, and EEPROM selects the EPCS4 chip, AS download port pinout such as mistake! Do not find Reference source.Shown in 5b.
Please refer to accompanying drawing 3, FPGA protocol code Unit Design process flow diagram.The FPGA hardware program uses Verilog HDL programming development, adopts modularization programming, has strengthened readability, maintainability and the transplantability of program.Program mainly is divided into four modules: 1) RS422 protocol chip initialization module 301; 2) RS422 protocol chip receive interruption module 302; 3) the data conversion storage module 303; 4) the communication protocol coding module 304.
After powering on, reset circuit module 401 can produce a low level pulse, and all logic chips are resetted.Then, the component register of 301 pairs of RS422 protocol chips of RS422 protocol chip initialization module carries out initial configuration, makes its normal operation.
Wherein, the initial configuration of RS422 protocol chip is: baud rate 2MB/s, 8 data bit, 1 position of rest, 1 parity check bit; Receiving the FIFO interruption is 5 (bytes).
During described program normal operation, in IDLE state (idle condition) circulation, RS422 protocol chip receive interruption module 302 is received data and is produced and interrupts; FPGA responds interruption, and data conversion storage module 303 coordinates the required sequential of RS422 protocol chip, data is deposited in the RAM of FPGA inside from the FIFO transfer of RS422 protocol chip; 304 couples of RAM of communication protocol coding module interrupt data to be processed, and judgement RS422 steering order according to communication protocol, produces the matrix switch steering order that matrix switch is controlled submodule.
Please refer to accompanying drawing 6, the external output matrix switching control instruction of FPGA, CPLD decodes to this instruction, data layout is 8 bit parallel data-signals, low three (bit0-bit2) is for exercising the energy signal, middle four (bit3-bit6) are the row enable signal, and most significant digit (bit7) is the read signal, that is reads enable signal.
In buffering driver element 103, buffering drives chip and has chosen the 74ABT244 that FAIRCHILD company produces, FPGA output signal---the matrix switch steering order is the LVTTL level signal, after buffering drives chip, be converted to the Transistor-Transistor Logic level signal that is complementary with far-end CPLD.
Please refer to accompanying drawing 7, be the fundamental diagram of CPLD protocol-decoding unit finite state machine.
Reset is global reset signal, and is effectively low.
When reset is high:
Wait: original state when low, jumps to Start as read; Be input as 11010101 if detect, jump to Clearstep1; Otherwise, circulation.
Start: reading, and output; If read becomes height, jump to Wait; Otherwise, circulation.
Clearstep1: if read is low, jump to Start; Be input as 10101010 if detect, jump to Clearstep2; Otherwise, circulation.
Clearstep2: zero clearing, and return to Wait.
Reset instruction: be 1010101 when the 6-0 position being detected, then again 0101010, represent all relay units reset (contact disconnection).
Described CPLD protocol-decoding unit 104 receives the matrix switch steering order that issues from the RS422 submodule.CPLD carries out protocol-decoding, produces the column/row control signal, thereby column signal driver element and row signal driving unit are controlled.CPLD has chosen the EPM7064SLC84-10N of the Max series of altera corp's production.The 5V Power supply, the IO pin can provide the 5V power supply, and crystal oscillator has been chosen the 10M crystal oscillator that KOAN company produces.
Please refer to accompanying drawing 8, the row control signal of relay array is provided by column signal control module field effect transistor 801.The present invention has adopted field effect transistor IRFU9220, and this chip is P channel power field effect transistor, R
DS (ON)Be 1.5 Ω.The capable control signal of relay array is provided by row signaling control unit Darlington transistor 802.The ULN2803A Darlington transistor array that the present invention adopts TI company to produce, collector current can reach 500mA.
Wherein, described relay array is the large scale array of 8*16, the midget relay AGN2004H that relay subelement 803 has adopted PANASONIC to produce.Each relay coil two ends backward dioded 804 that plays overcurrent protection in parallel, model is 1N4007.The positive and negative two ends of the coil of relay are controlled by row signal and column signal respectively, the input end of the contact termination measurand of relay.Control by long-range RS422 instruction, switch flexibly each contact, realize the route of signal.
Please refer to accompanying drawing 9, the relay array unit is made of the relay array of 8*16, and each relay all is positioned at the place, point of crossing of row/row, and the positive and negative two ends of relay coil are controlled by corresponding column signal and row signal respectively.During and if only if relay coil forward conduction, relay contact closure.The normally opened contact 902 of relay connects the test lead of measurand.The stationary contact 901 that is positioned at the relay of odd-numbered line (1,3,5,7 row) in array connects an end of testing tool, and the stationary contact that is positioned at the relay of even number line (0,2,4,6 row) connects the other end (carrying out electrical interconnection by binding post and testing tool) of testing tool.Long-range RS422 instruction pilot relay array, corresponding two relays of gating, (two relays of gating lay respectively at odd-numbered line and even number line can to realize testing tool and measurand interconnected, i.e. two two ends that stationary contact is received testing tool, two normally opened contacts are received the two ends of measurand).
For 8*16 relay array unit (totally 128 relays), be divided into 16 groups (every group of eight relays) by row, it is divided into 4 groups (every group of 2 relays lay respectively at odd-numbered line and even number line) by being about to again, forms 64 relay groups 903.Two normally opened contacts of every group relay are connected, and namely form altogether 64 test points, and each test point connects an end of measurand, draw by the signal gang socket of DB78, are used for carrying out electrical interconnection with measurand.
Wherein, each test point is corresponding relay group 903 all, and relay lays respectively at odd-numbered line and even number line, and namely stationary contact is received respectively the two ends of testing tool.By relay gate, the test point of measurand can be received any end of testing tool.
Please refer to accompanying drawing 10, Darlington transistor is open collector output, for guaranteeing accurately for coil provides forward voltage, has increased by 75 Ω pull-up resistors 1001 at output terminal.
Claims (11)
1. long-range matrix switch control module with RS422 interface, it is characterized in that: its composition is divided into two parts---and RS422 submodule and matrix switch are controlled submodule;
Wherein the RS422 submodule comprises:
One RS422 isolated communication unit, this unit is made of RS422 transceiver and RS422 protocol chip, the RS422 transceiver is with the differential signal of RS422---and the RS422 steering order is converted to the single-ended Transistor-Transistor Logic level signal that is complementary with the RS422 protocol chip, realizes simultaneously the electrical isolation of difference and single-ended signal; The RS422 protocol chip receives the serial data from the RS422 transceiver, is converted into parallel data and is stored in chip internal reception FIFO and produces interruption;
One FPGA protocol code unit, this unit coordinate its peripheral circuit to consist of take FPGA as core; FPGA receives the interrupt instruction from the RS422 protocol chip, reads data---the RS422 steering order in its reception FIFO, and data conversion storage is entered in the RAM of FPGA inside; FPGA processes the data in RAM, according to communication protocol, produces the matrix switch steering order that matrix switch is controlled submodule;
One buffering driver element, this unit drive chip by buffering and consist of, FPGA output signal---the matrix switch steering order is the LVTTL level signal, after buffering drives chip, be converted to the Transistor-Transistor Logic level signal that is complementary with far-end CPLD;
Matrix switch is controlled submodule and is comprised:
One CPLD protocol-decoding unit, this unit coordinate its peripheral circuit to consist of take CPLD as core, receive the matrix switch steering order that issues from the RS422 submodule, and carry out protocol-decoding, and then produce the column/row control signal of relay array;
One relay array unit, this unit is made of the relay array of 8*16, often classifies 8 as, 16 of every behaviors, each relay all is positioned at the place, point of crossing of column/row, and the positive and negative two ends of relay coil are controlled by corresponding column signal and row signal respectively; During and if only if relay coil forward conduction, relay contact closure; The normally opened contact of relay connects the test lead of measurand; The stationary contact that is positioned at the relay of odd-numbered line in array connects an end of testing tool, and the stationary contact that is positioned at the relay of even number line connects the other end of testing tool; Long-range RS422 instruction pilot relay array, corresponding two relays of gating are namely realized the interconnected of testing tool and measurand;
One column signal driver element, this unit are take 16 P-channel field-effect transistor (PEFT) pipes as core, and 16 road row control signals that CPLD is exported drive; Signal controlling one row in every road i.e. 8 relays; The grid of each field effect transistor connects the output terminal of corresponding CPLD, and drain electrode connects the anode of the relay coil of respective column, and source electrode connects the 5V power supply;
Delegation's signal driving unit, this unit is take 8 NPN type Darlington transistors as core, 8 road row control signals to CPLD output drive, every road signal controlling delegation i.e. 16 relays, the base stage of each Darlington transistor connects the output terminal of corresponding CPLD, collector connects the negative terminal of corresponding row relay coil, grounded emitter.
2. a kind of long-range matrix switch control module with RS422 interface according to claim 1, it is characterized in that: described RS422 submodule has the signal gang socket of DB15, and the RS422 steering order that issues for receiving remote equipment provides communication interface.
3. a kind of long-range matrix switch control module with RS422 interface according to claim 1, it is characterized in that: the FPGA of described RS422 submodule is connected by the gang socket of DB25 signal with the CPLD that matrix switch is controlled submodule, communicates with 8 bit parallel buses.
4. a kind of long-range matrix switch control module with RS422 interface according to claim 1, it is characterized in that: described relay array unit---8*16, totally 128 relays, be divided into 16 groups by row, every group of 8 relays, then it is divided into 4 groups by being about to, every group of 2 relays, lay respectively at odd-numbered line and even number line, form 64 relay groups; Two normally opened contacts of every group relay are connected, and namely form altogether 64 test points, and each test point connects an end of measurand, draw by the signal gang socket of DB78, are used for carrying out electrical interconnection with measurand.
5. a kind of long-range matrix switch control module with RS422 interface according to claim 4, it is characterized in that: all corresponding 2 relays of described each test point, and lay respectively at odd-numbered line and even number line, namely stationary contact is received respectively the two ends of testing tool; By relay gate, the test point of measurand is received any end of testing tool.
6. a kind of long-range matrix switch control module with RS422 interface according to claim 3, it is characterized in that: described FPGA externally exports as frame data take 8 bit parallel data, communicates with CPLD.
7. a kind of long-range matrix switch control module with RS422 interface according to claim 3, it is characterized in that: the frame head of the data stream that FPGA communicates by letter with CPLD is the reset instruction that matrix switch is controlled submodule, this instruction has two frame data: the first frame is that 11010101, the second frames are 10101010.
8. a kind of long-range matrix switch control module with RS422 interface according to claim 3, it is characterized in that: the form of the Frame that FPGA communicates by letter with CPLD is: low three is that bit0-bit2 exercises the energy signal, middle four is that bit3-bit6 is the row enable signal, most significant digit is that bit7 is the read signal, that is reads enable signal.
9. a kind of long-range matrix switch control module with RS422 interface according to claim 3, it is characterized in that: the time interval of every frame data that FPGA communicates by letter with CPLD is 2.5us, i.e. 100 FPGA clocks.
10. a kind of long-range matrix switch control module with RS422 interface according to claim 1 is characterized in that: described relay is the midget relay AGN2004H that PANASONIC is produced.
11. a kind of long-range matrix switch control module with RS422 interface according to claim 1, it is characterized in that: in described row signal driving unit, the output terminal of Darlington transistor all has the pull-up resistor of 75 Ω.
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| CN104483876B (en) * | 2014-11-30 | 2017-02-22 | 中国计量学院 | Array control device applicable to scanning switch internal relay |
| CN104635052B (en) * | 2015-02-11 | 2017-08-25 | 合肥工业大学 | Apply the on-off circuit in electromagnetic relay contact resistance test equipment |
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| CN106652427A (en) * | 2016-12-14 | 2017-05-10 | 南京长峰航天电子科技有限公司 | Serial control system of electronic array |
| CN107505486A (en) * | 2017-09-07 | 2017-12-22 | 国营芜湖机械厂 | A kind of high pressure program controlled matrix switch |
| CN107888585A (en) * | 2017-11-09 | 2018-04-06 | 山东船舶技术研究院 | Multiplexing isolation full-duplex communication module |
| CN110119118B (en) * | 2018-02-05 | 2024-03-01 | 中国科学院沈阳自动化研究所 | Low-cost energy-saving wireless remote automatic on-off device and method applied to AGV |
| CN112565640B (en) * | 2020-10-30 | 2022-09-27 | 北京时代民芯科技有限公司 | Method and system for eliminating column noise of CMOS image sensor in nuclear environment |
| CN112363542B (en) * | 2020-11-23 | 2022-09-27 | 上海航天测控通信研究所 | Ground equipment for rocket-borne phased array antenna initial phase balancing |
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