CN111830874A - Multi-channel serial digital signal transmission control device and method for train control system - Google Patents
Multi-channel serial digital signal transmission control device and method for train control system Download PDFInfo
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Abstract
The invention provides a multi-channel serial digital signal transmission control device and method for a train control system, wherein the device comprises: a programmable logic device and a processor. The programmable logic device is configured to collect n paths of externally input serial input data and carry out serial-to-parallel conversion on the n paths of serial input data to obtain converted parallel input data; the programmable logic device is also configured to perform parallel-to-serial conversion on the parallel output data and send the converted m paths of serial output data to the outside. The processor is communicatively coupled to the programmable logic device, the processor configured to receive and process the parallel input data, the processor further configured to send the parallel output data to the programmable logic device, control the conversion of the parallel output data into the m-way serial output data.
Description
Technical Field
The invention relates to digital signal transmission control, in particular to a device for controlling multi-channel serial digital signal transmission.
Background
Most of the existing train control vehicle-mounted systems adopt a single acquisition or output processing mode for serial digital signals, and even if the serial digital signals are subjected to input and output control, the signals are not further processed, and the real-time and resource optimization processing is not performed.
The problems and drawbacks of the prior art solutions are as follows:
a) the processing mode of the serial digital signals is single, the serial digital signals are in an acquisition mode or an output mode, and the serial digital signals of continuous code sequences cannot be received and sent;
b) serial digital signals are not further processed, so that the serial digital signals cannot be efficiently transmitted and received, and the real-time performance is poor;
c) the optimal configuration mode of the hardware resources is not considered, and the hardware resources are wasted.
Disclosure of Invention
The invention mainly adopts a mode of a processor + programmable logic device architecture to control the input and output of a plurality of paths of serial digital signals, the programmable logic device collects the serial digital signals input from the outside, sends the serial digital signals required by the outside, and performs logic conversion on the collection and sending through the programmable logic device, and the processor processes the received converted parallel digital signals and controls the parallel digital signals required to be sent.
Specifically, the present invention provides a multi-channel serial digital signal transmission control apparatus for a train control system, the apparatus including:
the programmable logic device is configured to collect n paths of externally input serial input data and carry out serial-to-parallel conversion on the n paths of serial input data to obtain converted parallel input data; the programmable logic device is also configured to perform parallel-to-serial conversion on the parallel output data and send the converted m paths of serial output data to the outside; and
a processor communicably coupled to the programmable logic device, the processor configured to receive and process the parallel input data, the processor further configured to send the parallel output data to the programmable logic device, controlling the conversion of the parallel output data into the m-way serial output data.
In one embodiment, the programmable logic device and the processor receive and transmit the parallel input data and the parallel output data to each other through a data bus; and the processor accesses the parallel input data which is stored in the programmable logic device and is subjected to serial-parallel conversion through an address bus and sends a control signal to the programmable logic device through a control bus.
In one embodiment, the programmable logic device comprises: the device comprises a decoder, a data selector, a serial-parallel conversion module and a parallel-serial conversion module;
when the n paths of serial input data are input into the programmable logic device, each path of serial input data is subjected to serial-parallel conversion through the serial-parallel conversion module, and the converted parallel input data are stored in the data selector; the processor sends address data to the decoder through an address bus, the address data represents an address of the parallel input data to be read, and the decoder decodes according to the address data and outputs a corresponding selection signal to the data selector; the data selector selects corresponding parallel input data according to the selection signal and outputs the parallel input data to the processor through a data bus;
when m paths of serial output data need to be output by the programmable logic device, the parallel output data needing to be output are written into the parallel-serial conversion module of the programmable logic device by the processor through the data bus, and the parallel-serial conversion module is controlled by an output control signal of the decoder to output the m paths of serial output data.
In one embodiment, the programmable logic device further comprises:
an input output buffer module coupled to the data selector and the parallel-to-serial conversion module and configured to buffer the parallel output data from the processor or buffer the parallel input data input to the processor from the data selector, wherein input and output directions of the input output buffer module are controlled by the decoder.
In one embodiment, the programmable logic device is further configured to generate a periodic pulse signal, the periodic pulse signal controls the working timing of the serial-to-parallel conversion module and the parallel-to-serial conversion module, the programmable logic device further sends the periodic pulse signal to the processor, and the processor controls the timing of reading and writing the programmable logic device according to the periodic pulse signal.
In one embodiment, the periodic pulse signal is generated by frequency division of a clock signal of the programmable logic device.
In one embodiment, the programmable logic device is an FPGA and the processor is a CPU.
In one embodiment, the decoder receives the address data, the read/write signal, and the chip select signal from the processor, and outputs the select signal, the output control signal, and the input-output buffer module control signal.
In one embodiment, the data bus is an 8-bit tri-state bidirectional data bus, the n is 16, and the m is 2.
The invention also provides a multi-channel serial digital signal transmission control method for the train control system, which comprises the following steps:
providing a processor and a programmable logic device that are in communication with each other;
the programmable logic device collects n paths of externally input serial input data, carries out serial-parallel conversion on the n paths of serial input data, and sends the converted parallel input data to the processor;
the processor processing the parallel input data;
the processor sends parallel output data needing to be sent to the outside to the programmable logic device;
the programmable logic device performs parallel-to-serial conversion on the parallel output data under the control of the processor and sends the converted m paths of serial output data to the outside;
the working time sequence of the serial-parallel conversion and the parallel-serial conversion is controlled by a periodic pulse signal of the programmable logic device, the reading and writing time sequence of the processor to the programmable logic device is related to the periodic pulse signal of the programmable logic device, and the periodic pulse signal is generated by frequency division of a clock signal of the programmable logic device.
In one embodiment, the programmable logic device is an FPGA and the processor is a CPU.
The invention is mainly applied to the safe digital input and output of the train control vehicle-mounted system. A large number of serial signals are transmitted in a train control vehicle-mounted system, and under the condition that a code sequence is long or a plurality of '0' or '1' are repeated, codes are easy to leak or make mistakes when data are acquired by a traditional AD acquisition device. The invention adopts the processor to combine the framework of the programmable logic device to control the input and the output of the multi-channel serial digital signals, can receive and transmit the serial digital signals of the continuous code sequence, can further process the received serial digital signals to realize high-efficiency transmission and reception, and has strong real-time performance; in addition, the invention fully considers the optimized configuration of hardware resources and saves the hardware resources.
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The foregoing summary, as well as the following detailed description of the invention, will be better understood when read in conjunction with the appended drawings. It is to be noted that the appended drawings are intended as examples of the claimed invention. In the drawings, like reference characters designate the same or similar elements.
Fig. 1 shows a multi-channel serial digital signal transmission control apparatus according to an embodiment of the present invention;
FIG. 2 illustrates a functional logic diagram of a programmable logic device according to an embodiment of the present invention; and
fig. 3 shows a flow chart of control of transmission of a multi-channel serial digital signal according to an embodiment of the present invention.
Detailed Description
The detailed features and advantages of the present invention are described in detail in the detailed description which follows, and will be sufficient for anyone skilled in the art to understand the technical content of the present invention and to implement the present invention, and the related objects and advantages of the present invention will be easily understood by those skilled in the art from the description, claims and drawings disclosed in the present specification.
The invention is mainly applied to the safe digital input and output of the train control vehicle-mounted system. A large number of serial signals are transmitted in a train control vehicle-mounted system, and under the condition that a code sequence is long or a plurality of '0' or '1' are repeated, codes are easy to leak or make mistakes when data are acquired by a traditional AD acquisition device. The invention adopts a processor combined with the architecture of a programmable logic device to control the input and output of multiple paths of serial digital signals, collects the serial digital signals input from the outside, sends serial number signals required by the outside, and performs logic conversion on the collection and the sending through the programmable logic device, and the processor processes the received converted parallel digital signals and controls the parallel digital signals required to be sent.
Specifically, when a signal is input, the programmable logic device acquires serial data, converts the serial data into parallel data, stores the parallel data at a fixed address, and reads the parallel data through a data bus by the processor; when the signal is required to be output, the processor writes parallel data into the programmable logic device through the data bus, and the programmable logic device converts the parallel data into serial data to be output.
The processor of the present invention may comprise a CPU or DSP or other processor with signal processing capabilities.
The programmable logic device of the present invention may comprise an FPGA or a CPLD. When the real-time requirement of the processed signal is high, an FPGA can be adopted. When the real-time requirement of the processed signal is not high, a CPLD can be adopted.
Fig. 1 shows a multi-channel serial digital signal transmission control apparatus according to an embodiment of the present invention. The apparatus includes a CPU 101 and an FPGA 102. It should be noted that although the processor is shown in fig. 1 in the form of a CPU and the programmable logic device is shown in the form of an FPGA, as previously described, the present invention is not limited to this particular embodiment.
As shown IN fig. 1, the FPGA inputs serial input signals IN1, IN 2, …, INn. The FPGA outputs serial output signals OUT1, OUT2, …, OUT m. Wherein n is an integer of 1 or more, and m is an integer of 1 or more. The FPGA and the CPU can be connected in a communication mode. Parallel data are mutually received and sent between the FPGA and the CPU through a data bus. The CPU accesses the data stored in the FPGA through an address bus and sends control signals to the FPGA through a control bus, wherein the control signals comprise read-write signals RW and chip selection signals CS.
In addition, precise timing requirements are essential to enable efficient, real-time, and accurate processing of multi-channel digital signals. In the invention, the FPGA needs two paths of clock signals, one path is used for synchronizing a sequential logic circuit in the FPGA, and the other path is used for frequency division to generate a periodic pulse signal. The periodic pulse signal is used for controlling the time sequence of processing a code sequence, namely controlling the working time sequence of serial-to-parallel conversion of input data or serial-to-parallel conversion of output data. In one embodiment, the periodic pulse signal is generated by frequency division from the FPGA clock signal. In one embodiment, the period of the periodic pulse signal is 5 ms.
IN one embodiment, the address bus is a 16-bit (ADDR [15:0]), the DATA bus is an 8-bit tri-state bidirectional DATA bus (DATA [7:0]), the control bus is a read-write signal (RW) and a chip select signal (CS), the serial input DATA IN 1-IN n is 16-way input DATA (i.e., n is 16), the serial output DATA OUT 1-OUT m is 2-way serial output DATA (i.e., m is 2), and the synchronous logic clock signal and the periodic pulse signal are both set to 5 ms.
Fig. 2 shows a functional logic diagram of a programmable logic device according to an embodiment of the invention. The programmable logic device comprises a decoder 201, a data selector 202, a serial-parallel conversion module 203, a parallel-serial conversion module 204 and an input-output buffer module IOBUF 205.
When external serial input data is input, the programmable logic device collects the serial input data, for example, 16-way input serial signals IN1 to IN 16. After each path of serial input data is subjected to serial-parallel conversion through the serial-parallel conversion module 203, the serial input data is sent to the data selector 202; the address data ADDR [15:0] of the processor is sent to a decoder 201 of the programmable logic device through an address bus, the address data represents the address of the data to be read, and the corresponding selection signals SELECT _ IN [3:0] are decoded by the decoder and output to a data selector 202, and the parallel output data to be output are selected; the DATA selector 202 reads the selected parallel output DATA according to SELECT _ IN [3:0] and outputs the parallel output DATA DATA [7:0] to the processor via the DATA bus.
When the serial output DATA needs to be output, the processor writes the parallel output DATA DATA [7:0] into the parallel-to-serial conversion block 204 of the programmable logic device through the DATA bus, and the output control signals SELECT _ OUT1 and SELECT _ OUT2 of the decoder 201 control the parallel-to-serial conversion block 204 to output the serial output DATA OUT1, OUT 2.
The input/output buffer module control signal SELECT _ IO of the decoder 201 controls the input/output buffer module, and the input/output buffer module controls the transmission direction of the 8-bit tri-state bidirectional data bus according to the SELECT _ IO, and waits for the processor to read and write data.
The periodic pulse signal controls the operation timing of the serial-to-parallel conversion module 203 and the parallel-to-serial conversion module 204, for example, the timing of parallel-to-serial or serial-to-parallel conversion. Meanwhile, the programmable logic device also sends a periodic pulse signal to the processor, and the periodic pulse signal is associated with the time sequence of reading and writing the programmable logic device by the processor. In one embodiment, when the input signal is input, the programmable logic device converts 8-bit serial data into parallel data within 5ms, and the processor accesses the programmable logic device through the address bus in the next 5 ms.
In the invention, the width of the data bus, the total path number of the serial input data and the total path number of the serial output data are independent. In addition, the total number of lanes of serial input data is not limited to 16 lanes, the total number of lanes of serial output data is not limited to 2 lanes, and the width of the data bus is not limited to 8 bits. In practical applications, the data bus width or the number of input/output signal paths can be increased or decreased according to practical requirements.
Fig. 3 illustrates a multi-channel serial digital signal transmission control method according to an embodiment of the present invention. The method comprises the following steps:
step 301: providing a processor and a programmable logic device that are in communication with each other;
step 302: the programmable logic device collects n paths of externally input serial input data, carries out serial-parallel conversion on the n paths of serial input data, and sends the converted parallel input data to the processor;
step 303: the processor processing the parallel input data;
step 304: the processor sends parallel output data needing to be sent to the outside to the programmable logic device;
step 305: the programmable logic device performs parallel-to-serial conversion on the parallel output data under the control of the processor and sends the converted m paths of serial output data to the outside;
the working time sequence of the serial-parallel conversion and the parallel-serial conversion is controlled by a periodic pulse signal of the programmable logic device, the reading and writing of the programmable logic device by the processor are related to the periodic pulse signal of the programmable logic device, and the periodic pulse signal is generated by frequency division of a clock signal of the programmable logic device.
The invention adopts the processor to combine the framework of the programmable logic device to control the input and the output of the multi-channel serial digital signals, can receive and transmit the serial digital signals of the continuous code sequence, can further process the received serial digital signals to realize high-efficiency transmission and reception, and has strong real-time performance; in addition, the invention fully considers the optimized configuration of hardware resources and saves the hardware resources.
The terms and expressions which have been employed herein are used as terms of description and not of limitation. The use of such terms and expressions is not intended to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications may be made within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.
Also, it should be noted that although the present invention has been described with reference to the current specific embodiments, it should be understood by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes or substitutions may be made without departing from the spirit of the present invention, and therefore, it is intended that all changes and modifications to the above embodiments be included within the scope of the claims of the present application.
Claims (9)
1. A multi-channel serial digital signal transmission control apparatus for a train control system, the apparatus comprising:
the programmable logic device is configured to collect n paths of externally input serial input data and carry out serial-to-parallel conversion on the n paths of serial input data to obtain converted parallel input data; the programmable logic device is also configured to perform parallel-to-serial conversion on the parallel output data and send the converted m paths of serial output data to the outside; and
a processor communicably coupled to the programmable logic device, the processor configured to receive and process the parallel input data, the processor further configured to send the parallel output data to the programmable logic device, control conversion of the parallel output data into the m-way serial output data;
the working time sequence of the serial-parallel conversion and the parallel-serial conversion is controlled by a periodic pulse signal of the programmable logic device, the reading and writing time sequence of the processor to the programmable logic device is related to the periodic pulse signal of the programmable logic device, and the periodic pulse signal is generated by frequency division of a clock signal of the programmable logic device.
2. The multi-channel serial digital signal transmission control apparatus for a train control system according to claim 1, wherein said programmable logic device and said processor mutually receive and transmit said parallel input data and said parallel output data through a data bus; and the processor accesses the parallel input data which is stored in the programmable logic device and is subjected to serial-parallel conversion through an address bus and sends a control signal to the programmable logic device through a control bus.
3. The multi-channel serial digital signal transmission control apparatus for a train control system according to claim 1, wherein said programmable logic device comprises: the device comprises a decoder, a data selector, a serial-parallel conversion module and a parallel-serial conversion module;
when the n paths of serial input data are input into the programmable logic device, each path of serial input data is subjected to serial-parallel conversion through the serial-parallel conversion module, and the converted parallel input data are stored in the data selector; the processor sends address data to the decoder through an address bus, the address data represents an address of the parallel input data to be read, and the decoder decodes according to the address data and outputs a corresponding selection signal to the data selector; the data selector selects corresponding parallel input data according to the selection signal and outputs the parallel input data to the processor through a data bus;
when m paths of serial output data need to be output by the programmable logic device, the parallel output data needing to be output are written into the parallel-serial conversion module of the programmable logic device by the processor through the data bus, and the parallel-serial conversion module is controlled by an output control signal of the decoder to output the m paths of serial output data.
4. The multi-channel serial digital signal transmission control apparatus for a train control system according to claim 3, wherein said programmable logic device further comprises:
an input output buffer module coupled to the data selector and the parallel-to-serial conversion module and configured to buffer the parallel output data from the processor or buffer the parallel input data input to the processor from the data selector, wherein input and output directions of the input output buffer module are controlled by the decoder.
5. The multi-channel serial digital signal transmission control device for a train control system according to claim 1, wherein the programmable logic device is an FPGA, and the processor is a CPU.
6. The apparatus of claim 3, wherein the decoder receives the address data, the read/write signal, and the chip select signal from the processor, and outputs the select signal, the output control signal, and the input-output buffer module control signal.
7. The multi-channel serial digital signal transmission control device for a train control system as claimed in claim 2, wherein said data bus is an 8-bit tri-state bidirectional data bus, said n is 16, and said m is 2.
8. A multi-channel serial digital signal transmission control method for a train control system is characterized by comprising the following steps:
providing a processor and a programmable logic device that are in communication with each other;
the programmable logic device collects n paths of externally input serial input data, carries out serial-parallel conversion on the n paths of serial input data, and sends the converted parallel input data to the processor;
the processor processing the parallel input data;
the processor sends parallel output data needing to be sent to the outside to the programmable logic device;
the programmable logic device performs parallel-to-serial conversion on the parallel output data under the control of the processor and sends the converted m paths of serial output data to the outside;
the working time sequence of the serial-parallel conversion and the parallel-serial conversion is controlled by a periodic pulse signal of the programmable logic device, the reading and writing time sequence of the processor to the programmable logic device is related to the periodic pulse signal of the programmable logic device, and the periodic pulse signal is generated by frequency division of a clock signal of the programmable logic device.
9. The multi-channel serial digital signal transmission control method for a train control system according to claim 1, wherein the programmable logic device is an FPGA, and the processor is a CPU.
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Application publication date: 20201027 |