CN110362347B - Real-time priority multichannel processor and control method - Google Patents
Real-time priority multichannel processor and control method Download PDFInfo
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- CN110362347B CN110362347B CN201910648888.2A CN201910648888A CN110362347B CN 110362347 B CN110362347 B CN 110362347B CN 201910648888 A CN201910648888 A CN 201910648888A CN 110362347 B CN110362347 B CN 110362347B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
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Abstract
The invention relates to a real-time priority multichannel processor and a control method, which adopt a brand-new multichannel design architecture, realize the unified scheduling of a plurality of input streams to a plurality of output streams through fewer hardware logic circuits, allocate control time slots according to priority for each data channel, prevent the deadlock of a data scheduling state, have no internal storage unit, do not need to buffer intermediate data, have stable and reliable performance, can effectively improve the working efficiency of data scheduling among multiple channels, thoroughly solve the data interaction problem between all external data and an internal register and between an internal memory and an application system, and have priority data arbitration control, and the whole design is simple, easy, stable and reliable in practical application.
Description
Technical Field
The invention relates to a real-time priority multichannel processor and a control method, belonging to the technical field of data communication application.
Background
The multichannel data scheduling control method is widely applied to data communication control application, and aims at interconnection of various external devices and unified data scheduling.
Disclosure of Invention
The invention aims to solve the technical problem of providing a real-time priority multichannel processor, which adopts a brand-new multichannel design architecture and can effectively improve the working efficiency of data scheduling among multiple channels.
The invention adopts the following technical scheme for solving the technical problems: the invention designs a real-time priority multichannel processor which is used for realizing priority scheduling between multi-input data signals and multi-input control instructions; the system comprises a read-write control module, a data uplink control module, a data downlink control module, an emergency interruption control module and a centralized control module;
the output end of the data uplink control module and the input end of the data downlink control module are respectively connected with the read-write control module; the read-write control module is used for receiving asynchronous data input signals formed by one or two of multi-input data signals and multi-input control instructions, sampling the asynchronous data input signals and acquiring corresponding one or two of multi-target data signals and multi-target control instructions;
the input end of the data uplink control module and the output end of the data downlink control module are respectively connected with the centralized control module, the data uplink control module is used for realizing the establishment and connection of uplink channels, and the data downlink control module is used for realizing the establishment and connection of downlink channels;
the emergency interruption control module is connected with the read-write control module in a bidirectional data communication manner, meanwhile, the emergency interruption control module is communicated with the centralized control module in a unidirectional manner, the communication direction is pointed to the emergency interruption control module by the centralized control module, and the emergency interruption control module is used for realizing establishment and connection of an emergency interruption channel;
the centralized control module carries out priority scheduling on an uplink channel, a downlink channel and an emergency interrupt channel according to the preset priority level sequence, realizes priority scheduling on multi-target data signals and multi-target control instructions, and further realizes priority scheduling between multi-input data signals and multi-input control instructions.
As a preferred technical scheme of the invention: completing data access to an external memory based on priority scheduling between the multi-input data signals and the multi-input control instructions; the real-time priority multichannel processor also comprises an input/output control module, the centralized control module is in bidirectional data communication connection with the input/output control module, the input/output control module is connected with an external memory, and the input/output control module identifies a target data signal or a target control instruction from the centralized control module and completes data access to the external memory according to an identification result.
As a preferred technical scheme of the invention: the read-write control module realizes the receiving of asynchronous data input signals composed of one or two of multi-input data signals and multi-input control instructions through the communication with an external application system and an external control device respectively.
In view of the above, the technical problem to be solved by the present invention is to provide a control method based on a real-time priority multi-channel processor, which can effectively improve the working efficiency of data scheduling among multiple channels and realize stable data scheduling by applying a multi-channel architecture.
In order to solve the technical problems, the invention adopts the following technical scheme: the invention designs a control method based on a real-time priority multichannel processor, which comprises the following steps:
the method comprises the following steps that A, the read-write control module receives asynchronous data input signals composed of one or two of multi-input data signals and multi-input control instructions, samples the asynchronous data input signals, and obtains one or two of corresponding multi-target data signals and multi-target control instructions;
b, the read-write control module carries out latch processing on one or two types of the obtained multi-target data signals and the multi-target control instructions;
c, the read-write control module is respectively communicated with the data uplink control module, the data downlink control module and the emergency interruption control module to realize the establishment and connection of an uplink channel, a downlink channel and an emergency interruption channel;
and D, the centralized control module carries out priority scheduling on the uplink channel, the downlink channel and the emergency interrupt channel according to the preset priority sequence, namely the centralized control module realizes the priority scheduling acquisition of the multi-target data signals or the multi-target control instructions, namely the priority scheduling between the multi-input data signals and the multi-input control instructions.
As a preferred technical scheme of the invention: step E, after step D is executed, step E is executed;
and E, the input and output control module identifies the target data signal or the target control instruction from the centralized control module and completes data access to the external memory according to the identification result.
As a preferred technical scheme of the invention: the preset priority is an emergency interrupt channel, a downlink channel and an uplink channel in sequence from high to low.
Compared with the prior art, the real-time priority multichannel processor and the control method have the following technical effects by adopting the technical scheme:
the invention designs a real-time priority multichannel processor and a control method, adopts a brand-new multichannel design architecture, realizes the unified scheduling of a plurality of input streams to a plurality of output streams through fewer hardware logic circuits, allocates control time slots according to the priority for each data channel, prevents the deadlock of a data scheduling state, has no internal storage unit, does not need to buffer intermediate data, has stable and reliable performance, can effectively improve the working efficiency of data scheduling among multiple channels, thoroughly solves the problem of data interaction between all external data and an internal register as well as between an internal memory and an application system, and has priority data arbitration control, and the whole design is simple, feasible, stable and reliable in practical application.
Drawings
FIG. 1 is a block diagram of a real-time priority multi-channel processor designed in accordance with the present invention.
Detailed Description
The following description will explain embodiments of the present invention in further detail with reference to the accompanying drawings.
The invention designs a real-time priority multichannel processor which is used for realizing priority scheduling between multi-input data signals and multi-input control instructions; in practical application, as shown in fig. 1, the system includes a read-write control module, a data uplink control module, a data downlink control module, an emergency interrupt control module, and a centralized control module.
The output end of the data uplink control module and the input end of the data downlink control module are respectively connected with the read-write control module; the read-write control module realizes the receiving of asynchronous data input signals composed of one or two of multi-input data signals and multi-input control instructions through the communication with an external application system and an external control device respectively, and samples the asynchronous data input signals to obtain one or two of corresponding multi-target data signals and multi-target control instructions.
The input end of the data uplink control module and the output end of the data downlink control module are respectively connected with the centralized control module, the data uplink control module is used for realizing the establishment and connection of uplink channels, and the data downlink control module is used for realizing the establishment and connection of downlink channels.
The emergency interruption control module is connected with the read-write control module in a bidirectional data communication mode, meanwhile, the emergency interruption control module is communicated with the centralized control module in a unidirectional mode, the communication direction is directed to the emergency interruption control module by the centralized control module, and the emergency interruption control module is used for achieving establishment and connection of an emergency interruption channel.
The centralized control module carries out priority scheduling on an uplink channel, a downlink channel and an emergency interrupt channel according to the preset priority level sequence, realizes priority scheduling on multi-target data signals and multi-target control instructions, and further realizes priority scheduling between multi-input data signals and multi-input control instructions.
When the designed real-time priority multichannel processor is used in specific application, the data access to an external memory is further completed based on the priority scheduling between the multi-input data signals and the multi-input control instructions; the real-time priority multichannel processor also comprises an input/output control module, the centralized control module is in bidirectional data communication connection with the input/output control module, the input/output control module is connected with an external memory, and the input/output control module identifies a target data signal or a target control instruction from the centralized control module and completes data access to the external memory according to an identification result.
Aiming at the design of the real-time priority multi-channel processor for performing data access operation on the external memory in practical application, the invention is specifically designed and implemented by the following steps.
And step A, the read-write control module receives asynchronous data input signals consisting of one or two of multi-input data signals and multi-input control instructions, samples the asynchronous data input signals and obtains one or two of corresponding multi-target data signals and multi-target control instructions.
And B, the read-write control module carries out latch processing on one or two types of the obtained multi-target data signals and the multi-target control instructions.
And step C, the read-write control module is respectively communicated with the data uplink control module, the data downlink control module and the emergency interruption control module, so that the establishment and connection of an uplink channel, a downlink channel and an emergency interruption channel are realized.
And D, the centralized control module carries out priority scheduling on the uplink channel, the downlink channel and the emergency interrupt channel according to the preset priority sequence, namely the centralized control module realizes the priority scheduling acquisition of the multi-target data signals or the multi-target control instructions, namely the priority scheduling between the multi-input data signals and the multi-input control instructions, and then the step E is carried out.
In practical application, the preset priority is an emergency interrupt channel, a downlink channel and an uplink channel in sequence from high to low.
And E, the input and output control module identifies the target data signal or the target control instruction from the centralized control module and completes data access to the external memory according to the identification result.
In the above design control method, for the release operation of the data link of the uplink channel, the downlink channel, and the emergency interrupt channel, the release of the data link must be completed by transmitting the data release signal to the first stage of the reverse direction after the data has been processed.
The real-time priority multichannel processor and the control method designed by the technical scheme adopt a brand-new multichannel design architecture, realize the unified scheduling of a plurality of input streams to a plurality of output streams through fewer hardware logic circuits, allocate control time slots according to the priority for each data channel, prevent the deadlock of a data scheduling state, have no internal storage unit, do not need to buffer intermediate data, have stable and reliable performance, can effectively improve the working efficiency of data scheduling among multiple channels, thoroughly solve the problems of data interaction between all external data and internal registers and between an internal memory and an application system, and have priority data arbitration control, and the whole design is simple, feasible, stable and reliable in practical application.
In addition, the design scheme of the patent can instantiate a plurality of real-time priority multichannel processing, process more channels, greatly improve the processing efficiency of data with higher relative priority ratio, can be applied to data interaction processing under the condition of interconnection of a large number of external devices, and greatly improves the data processing capacity of the whole system.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (6)
1. A real-time priority multichannel processor is used for realizing priority scheduling between multi-input data signals and multi-input control instructions; the method is characterized in that: the system comprises a read-write control module, a data uplink control module, a data downlink control module, an emergency interruption control module and a centralized control module;
the output end of the data uplink control module and the input end of the data downlink control module are respectively connected with the read-write control module; the read-write control module is used for receiving asynchronous data input signals consisting of one or two of multi-input data signals and multi-input control instructions, sampling the asynchronous data input signals and acquiring corresponding one or two of multi-target data signals and multi-target control instructions;
the input end of the data uplink control module and the output end of the data downlink control module are respectively connected with the centralized control module, the data uplink control module is used for realizing the establishment and connection of uplink channels, and the data downlink control module is used for realizing the establishment and connection of downlink channels;
the emergency interruption control module is connected with the read-write control module in a bidirectional data communication manner, meanwhile, the emergency interruption control module is communicated with the centralized control module in a unidirectional manner, the communication direction points to the emergency interruption control module from the centralized control module, and the emergency interruption control module is used for realizing the establishment and connection of an emergency interruption channel;
the centralized control module carries out priority scheduling on an uplink channel, a downlink channel and an emergency interrupt channel according to the preset priority level sequence, realizes priority scheduling on multi-target data signals and multi-target control instructions, and further realizes priority scheduling between multi-input data signals and multi-input control instructions.
2. The real-time priority multi-channel processor of claim 1, wherein: completing data access to an external memory based on priority scheduling between the multi-input data signals and the multi-input control instructions; the real-time priority multichannel processor also comprises an input/output control module, the centralized control module is in bidirectional data communication connection with the input/output control module, the input/output control module is connected with an external memory, and the input/output control module identifies a target data signal or a target control instruction from the centralized control module and completes data access to the external memory according to an identification result.
3. A real-time priority multi-channel processor according to claim 1 or 2, characterized in that: the read-write control module realizes the receiving of asynchronous data input signals composed of one or two of multi-input data signals and multi-input control instructions through the communication with an external application system and an external control device respectively.
4. A control method for a real-time priority multi-channel processor according to claim 2, comprising the steps of:
the method comprises the following steps that A, the read-write control module receives asynchronous data input signals formed by one or two of multi-input data signals and multi-input control instructions, samples the asynchronous data input signals and obtains corresponding one or two of multi-target data signals and multi-target control instructions;
b, the read-write control module carries out latch processing on one or two types of the obtained multi-target data signals and the multi-target control instructions;
c, the read-write control module is respectively communicated with the data uplink control module, the data downlink control module and the emergency interruption control module to realize the establishment and connection of an uplink channel, a downlink channel and an emergency interruption channel;
and D, the centralized control module carries out priority scheduling on the uplink channel, the downlink channel and the emergency interrupt channel according to the preset priority sequence, namely the centralized control module realizes the priority scheduling acquisition of the multi-target data signals or the multi-target control instructions, namely the priority scheduling between the multi-input data signals and the multi-input control instructions.
5. The control method based on the real-time priority multi-channel processor as claimed in claim 4, wherein: step E, after step D is executed, step E is executed;
and E, the input and output control module identifies the target data signal or the target control instruction from the centralized control module and completes data access to the external memory according to the identification result.
6. A control method based on a real-time priority multi-channel processor according to claim 4 or 5, characterized in that: the preset priority is an emergency interrupt channel, a downlink channel and an uplink channel in sequence from high to low.
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