CN108279927A - The multichannel command control method and system, controller of adjustable instruction priority - Google Patents
The multichannel command control method and system, controller of adjustable instruction priority Download PDFInfo
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- CN108279927A CN108279927A CN201711433361.5A CN201711433361A CN108279927A CN 108279927 A CN108279927 A CN 108279927A CN 201711433361 A CN201711433361 A CN 201711433361A CN 108279927 A CN108279927 A CN 108279927A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/327—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for interrupts
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
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Abstract
The present invention provides a kind of the multichannel command control method and system, controller of adjustable instruction priority, including is that per thread configures one group of state controller；Moderator is asked to arbitrate different data read requests by fetching；By director data by instructing memory arbitration device to store memory space corresponding on piece memory；By instructing Read Controller according to the instruction in polling sequence reading on piece memory；The director data of the outfit instruction of equipment and device flag are sent to commander sender by command decoder；Director data is sent to corresponding equipment by commander sender；By the feedback signal of signal controller receiving device, and multiple and different threads is switched over, sequence is executed with control device.The multichannel command control method and system, controller of the adjustable instruction priority of the present invention solve the problems, such as the problem of priority is seized, instruction efficiency of transmission, multithreading operation stationary problem.
Description
Technical field
The present invention relates to the technical fields of instruction control, refer to more particularly to a kind of multichannel of adjustable instruction priority
Enable control method and system, controller.
Background technology
With flourishing for Internet of Things and artificial intelligence technology, the demand to the chip of high-performance low-power-consumption is increasingly
Greatly.In the prior art, the technology of Multi-core parallel processing is widely used in each processor.In multithreading scene, core
Inside piece instruction read module and each processing unit between synchronous operation, have become chip performance bottleneck it
One.
Currently, which can be roughly divided into two types for the common mode of reading instruction：
(1) instruction is directly read by CPU and configures internal register
This mode advantage is to realize simply.The chip of current many Embedded Applications uses the side of bus direct addressin
Formula reads instruction.Since AMBA (Advanced Microcontroller Bus Architecture) bus is embedding in low-power consumption
Enter the extensive application of formula chip, the direct addressin of AMBA buses is the addressing system being commonly used in chip.Such mode is profit
With AMBA buses by CPU and command memory, and the equipment connection of instruction is received, to improve the rate of the transmission of single instruction
And efficiency.But since the information exchange between equipment and command memory must could carry out transfer by CPU, to drop
The low working efficiency of CPU, when reading a large amount of instruction, the working performance of CPU is decreased obviously.This is towards CPU
The major defect of dual-bus structure.Management instruction for convenience simultaneously, the space that will be divided exclusively for instruction, in order to
Software is operated, and the pattern of this pre- occupancy increases the expense of memory.If the space size established is bigger than normal or less than normal,
All easily cause the problem on memory.Typically, bus direct addressin is used completely, transmits all instructions in chip,
In the case that instruction number is more, it will instruction is caused to read the performance bottleneck for becoming entire chip.Therefore, for extensive
The instruction of quantity is read and write, it is clear that with direct addressin is less suitable.
(2) indirect configuration method
Currently, many high-performance system on chip (System on Chip, SoC) chips have made dedicated instruction fetch module.
The technology of generally use level-one chained list, CPU configure instruction read module, the address of instruction and quantity are sent to and taken
Instruction module, instruction fetch module retransmit request to Memory Controller Hub, and Memory Controller Hub is when bus free, directly from interior
Access data are simultaneously transferred to instruction fetch module, and information is fed back to CPU again, thus largely subtracted by Data Transfer Done
Light cpu resource occupation rate, can greatly save system resource.But in place of this way Shortcomings：If primary complete
Operation need multistage to instruct, and instruction is dispersed in different positions, and CPU needs to carry out repeatedly the operation of similar direct addressin,
To reduce the working efficiency of CPU.
In addition to the problem in performance, the problem of traditional single port mode is seized there is also priority.Since bus transmits
It, must be into the arbitration of row bus when having multiple main equipments while applying for the use of bus with timesharing.When low priority
When equipment is read out instruction earlier than the equipment of high priority, bus will be occupied by the equipment of low priority, and high priority must
The equipment that must wait until low priority, which has read instruction, could obtain bus resource.This hardware device without resources regulation mechanism
It is be easy to cause the delay of information, the forming properties bottleneck at the strong application of instantaneity demand.For artificial intelligence chip, inside
There are many neural network unit and graphics processors.If using traditional realization method, to multiple hardware processing modules
Instruction is sent, when one of processing module blocks, remaining processing module can not receive new instruction.It is a kind of common
Solution be introduce interrupt module, the interruption with high Preemptive priority can be in low Preemptive priority
Responded in disconnected processing procedure, i.e. interrupt nesting, the interruption of high Preemptive priority in other words can nested low preemptive type it is preferential
The interruption of grade.But if doing so, each hardware processing module can arrange in pairs or groups one and instruct read module, can occupy many connect
Mouth resource, the area of occupancy can be bigger, and the synchronous communication between each hardware processing module can become more complicated, difficult
With control.Frequently the expense that can also increase CPU is interrupted in processing, causes cpu load excessive.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of adjustable instruction priority
Multichannel command control method and system, controller, improve the working performance of whole chip, and solve that priority seizes asks
Topic, control is simple, saves a large amount of interface resource and chip area.
In order to achieve the above objects and other related objects, the present invention provide it is a kind of it is adjustable instruction priority multichannel refer to
Control method is enabled, is included the following steps：Status register, fetching request moderator, instruction memory arbitration device, instruction reading are set
Controller, command decoder, signal controller and commander sender；One group of state controller, the shape are configured for per thread
The number of state the controller initial address of the memory headroom where the address of block, end address and instruction block for storing instruction
Amount, and configure reading instruction enabling signal；Descriptor pointer read requests are sent to bus, root according to the information of status register
The initial address of the instruction segment returned according to bus and end address send control command read requests and are asked to bus, and by fetching
Moderator is asked to arbitrate different data read requests；According to current instruction label, the director data of bus transfer is passed through into finger
Memory arbitration device is enabled to store memory space corresponding on piece memory；By instructing Read Controller to be arbitrated not using polling mode
With the command reading request of thread, the instruction on piece memory is read according to polling sequence, and will instruct by decoding selector
It is transferred to corresponding command decoder；The director data of the outfit instruction of equipment and device flag are sent out by command decoder again
Send to commander sender, instruct corresponding marker to be sent to signal controller the synchronous communication of equipment room, and will in
Severed finger enables corresponding interrupt signal be sent to system；Director data is sent to corresponding equipment by commander sender；Pass through
Signal controller receiving device is for the feedback signal of the director data received；According to the feedback signal of reception and synchronous communication
Instruction, switches over multiple and different threads by signal controller and executes sequence with control device.
In one embodiment of the invention, the arbitration principle of the fetching request moderator is：
Address requests are prior to request of data in single thread, and high priority is prior to low priority；
Request of data between different threads realizes that the thread of pause will be skipped directly using polling mode.
In one embodiment of the invention, controlled in the corresponding FIFO in channel that synchronization is chosen by instruction memory arbitration device
Device is to instructing corresponding memory space to be written and read operation.
Accordingly, the present invention provides a kind of multichannel command control system of adjustable instruction priority, including setting mould
Block, configuration module, arbitration modules, command process module, receiving module and handover module；
The setup module is for being arranged status register, fetching request moderator, instruction memory arbitration device, instruction reading
Controller, command decoder, signal controller and commander sender；
The configuration module is used to configure one group of state controller for per thread, and the state controller refers to for storing
The quantity of the initial address of the memory headroom where the address of block, end address and instruction block is enabled, and configures reading instruction and opens
Dynamic signal；
The arbitration modules are used to send descriptor pointer read requests to bus according to the information of status register, according to
The initial address for the instruction segment that bus returns and end address send control command read requests and are asked to bus, and by fetching
Moderator arbitrates different data read requests；
Command process module is used for according to current instruction label, by the director data of bus transfer by instructing storage secondary
It cuts out device and stores memory space corresponding on piece memory；By instructing Read Controller to arbitrate different threads using polling mode
Command reading request reads the instruction on piece memory according to polling sequence, and is transmitted instructions to pair by decoding selector
The command decoder answered；The director data of the outfit instruction of equipment and device flag are sent to by instruction by command decoder again
The synchronous communication of equipment room is instructed corresponding marker to be sent to signal controller by transmitter, and by interrupt instruction pair
The interrupt signal answered is sent to system；Director data is sent to corresponding equipment by commander sender；
The receiving module is used for through signal controller receiving device for the feedback signal of the director data received；
The handover module is used to be instructed according to the feedback signal of reception and synchronous communication, by signal controller to multiple
Different threads are switched over executes sequence with control device.
In one embodiment of the invention, the arbitration principle of the fetching request moderator is：
Address requests are prior to request of data in single thread, and high priority is prior to low priority；
Request of data between different threads realizes that the thread of pause will be skipped directly using polling mode.
In one embodiment of the invention, controlled in the corresponding FIFO in channel that synchronization is chosen by instruction memory arbitration device
Device is to instructing corresponding memory space to be written and read operation.
The present invention provides a kind of multichannel instruction control unit of adjustable instruction priority, including processor and memory；
The memory is for storing computer program；
The processor is used to execute the computer program of the memory storage, so that the adjustable instruction priority
Multichannel instruction control unit execute the multichannel command control method of above-mentioned adjustable instruction priority.
Finally, the present invention provides a kind of multichannel command control system of adjustable instruction priority, including it is above-mentioned can
The multichannel instruction control unit of adjust instruction priority, fetching request moderator, instruction memory arbitration device, refers to status register
Enable Read Controller, command decoder, signal controller and commander sender；
The status register for storing instruction the initial address of the memory headroom where the address of block, end address with
And the quantity of instruction block, and configure reading instruction enabling signal；
The fetching request moderator is for arbitrating different data read requests；
Described instruction memory arbitration device is used for the instruction data storage of bus transfer is empty to the corresponding storage of on piece memory
Between；
Described instruction Read Controller is used for the command reading request using polling mode arbitration different threads, according to poll
Sequence reads the instruction on piece memory；
Described instruction decoder is used to the director data of the outfit instruction of equipment and device flag being sent to instruction and send
The synchronous communication of equipment room is instructed corresponding marker to be sent to signal controller by device, and interrupt instruction is corresponding
Interrupt signal is sent to system；
The signal controller for receiving device for the feedback signal of the director data received, and to it is multiple not
It is switched over thread and sequence is executed with control device；
Described instruction transmitter is used to the director data of equipment being sent to corresponding equipment.
As described above, the multichannel command control method and system, controller of the adjustable instruction priority of the present invention, tool
There is following advantageous effect：
(1) working performance of whole chip is improved, and solves the problems, such as that priority is seized, utilizes the side of single interface
Formula realizes the synchronization between multiple pattern process modules, and control is simple, saves a large amount of interface resource and chip face
Product；
(2) instruction in other threads can be read when a thread pauses in fine granularity multithreading, from
And it can hide because of loss of throughput caused by long and short pause；
(3) in fine granularity situation, the intertexture of thread can eliminate full empty slot；
(4) since each clock cycle can change transmitting thread, therefore the operation of long delay can be hidden, greatly carried
The high performance of chip；
(5) two-stage chained list indirect addressing is supported, it is only necessary to which one piece of minimum fixed space stores a small amount of chained list of the first order
Address, and the address of storage is instructed then without any restrictions, to overcome memory headroom division and managerial problem, save
Hardware resource, also allows for peopleware and develops, and flexibility is high.
Description of the drawings
Fig. 1 is shown as stream of the multichannel command control method of the adjustable instruction priority of the present invention in an embodiment
Cheng Tu；
The multichannel command control method of adjustable instruction priority that Fig. 2 is shown as the present invention is in an embodiment
System Organization Chart；
Fig. 3 is shown as schematic diagram of the instruction two level chained list of the present invention in an embodiment；
The fine granularity multithreading that Fig. 4 is shown as the present invention asks the schematic diagram in an embodiment；
Fig. 5 is shown as schematic diagram of the instruction Read-write Catrol framework of the present invention in an embodiment；
Fig. 6 is shown as knot of the multichannel command control system of the adjustable instruction priority of the present invention in an embodiment
Structure schematic diagram；
Fig. 7 is shown as structure of the multichannel instruction control unit of the adjustable instruction priority of the present invention in an embodiment
Schematic diagram.
Component label instructions
61 setup modules
62 configuration modules
63 arbitration modules
64 command process modules
65 receiving modules
66 handover modules
71 processors
72 memories
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It should be noted that the diagram provided in following embodiment only illustrates the basic structure of the present invention in a schematic way
Think, component count, shape and size when only display is with related component in the present invention rather than according to actual implementation in schema then
Draw, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its assembly layout kenel
It is likely more complexity.
The multichannel command control method and system, controller of the adjustable instruction priority of the present invention improve integral core
The working performance of piece solves the problems, such as that priority is seized, and control is simple, saves a large amount of interface resource and chip face
Product.
As shown in Figure 1, in an embodiment, the multichannel command control method packet of adjustable instruction priority of the invention
Include following steps：
Step S1, status register is set, fetching request moderator, instruction memory arbitration device, instruction Read Controller, refer to
Enable decoder, signal controller and commander sender.
As shown in Fig. 2, creating a kind of hardware structure of the multichannel instruction control unit of adjustable instruction priority.Specifically
Ground, the framework of instruction is read in setting in SOC overall frameworks, including status register, fetching ask moderator, instruction storage secondary
Cut out device, instruction Read Controller, command decoder, signal controller and commander sender.
Step S2, it is that per thread configures one group of state controller, the ground of state controller block for storing instruction
The quantity of the initial address of memory headroom where location, end address and instruction block, and configure reading instruction enabling signal.
Specifically, per thread is all controlled by one group of status register.Status register is configured by cpu bus, is matched
The quantity of the initial address of the memory headroom where the address of store instruction block, end address and instruction block is set, and configures reading
Instruction fetch enabling signal.As shown in figure 3, marking off one piece of memory space in Installed System Memory, the data stored are each fingers
The actual address for enabling block obtains the actual address of instruction by accessing this memory space.The full dummy status of this memory space by
Read pointer and write pointer determine.After CPU has configured status register, instruction control unit can work independently, and not need CPU again
Configuration is participated in, to alleviate the live load of CPU.
Step S3, descriptor pointer read requests are sent to bus according to the information of status register, is returned according to bus
Instruction segment initial address and end address send control command read requests to bus, and by fetching ask moderator it is secondary
Cut out different data read requests.
Specifically, according to the information of status register, descriptor pointer read requests is sent and refer to bus, bus transfer is returned
Descriptor pointer data be instruction segment initial address and end address.According to the initial address of instruction segment and terminate ground
Location sends control command read requests bus.Wherein, two different data read requests are carried out by fetching request moderator
Request arbitration.As shown in figure 4, single thread includes the request of data of two kinds of different levels of high priority and low priority, write from memory
The sequence of low priority can be seized by recognizing high priority.For fetching asks moderator, Address requests are excellent in single thread
Prior to request of data, high priority is prior to low priority.Request of data between different threads is using polling mode realization, i.e.,
1~N number of thread intermediate rotation request, the thread of pause will be skipped directly.Fetching request moderator asks each data
Corresponding request source can all be recorded by asking；When request data returns, also refer to judge IA according to record label
It enables data and belongs to which thread.
Step S4, according to current instruction label, by the director data of bus transfer by instructing the storage of memory arbitration device
To the corresponding memory space of on piece memory；By instructing Read Controller to be read using the instruction of polling mode arbitration different threads
Request reads the instruction on piece memory according to polling sequence, and transmits instructions to corresponding instruction by decoding selector
Decoder；The director data of the outfit instruction of equipment and device flag are sent to by commander sender by command decoder again,
Corresponding marker is instructed to be sent to signal controller the synchronous communication of equipment room, and by the corresponding interruption of interrupt instruction
Signal is sent to system；Director data is sent to corresponding equipment by commander sender.
As shown in figure 5, according to current instruction label, the director data of bus transfer is stored by instruction memory arbitration device
In the corresponding memory space of on piece memory.In the corresponding fifo controller in channel that synchronization is chosen by instruction memory arbitration device
To instructing corresponding memory space to be written and read operation.
It instructs reader using the command reading request of polling mode arbitration different threads, on piece is read according to polling sequence
Instruction in memory, and by decoding selector, corresponding command decoder is transmitted to carry out decoded operation to instruction.
Specifically, according to the different type of the instruction of reading, command decoder executes different operations：
(1) if described instruction synchronizes the instruction of communication between distinct device, command decoder after decoding will be right
The marker answered is sent to signal controller.
(2) if described instruction is the configuration-direct of equipment, command decoder sends director data and device flag together
To commander sender, so that director data is sent to corresponding equipment by commander sender.
(3) described instruction is interrupt instruction, and corresponding interrupt signal is sent to system by command decoder.
Step S5, by signal controller receiving device for the feedback signal of the director data received.
Specifically, equipment receives corresponding director data, and after carrying out relevant operation according to the device flag of itself,
Feedback signal is sent to signal controller.
Step S6, it is instructed according to the feedback signal of reception and synchronous communication, by signal controller to multiple and different threads
It switches over and sequence is executed with control device.
Specifically, signal controller is arbitrated according to the feedback signal of reception and synchronous communication instruction, to multiple and different
Thread switches over, and sequence is executed to control device.
So far, that is, primary complete multichannel instruction control is completed.Later, bus is looked by access state register
The reading situation of present instruction is ask, and new instruction block storage address is sent to status register.Repeat the above steps S1-
S6, until all instruction end of transmissions.
As shown in fig. 6, in an embodiment, the multichannel command control system packet of adjustable instruction priority of the invention
Include setup module 61, configuration module 62, arbitration modules 63, command process module 64, receiving module 65 and handover module 66.
Setup module 61 is for being arranged status register, fetching request moderator, instruction memory arbitration device, instruction reading control
Device, command decoder, signal controller and commander sender processed.
As shown in Fig. 2, creating a kind of hardware structure of the multichannel instruction control unit of adjustable instruction priority.Specifically
Ground, the framework of instruction is read in setting in SOC overall frameworks, including status register, fetching ask moderator, instruction storage secondary
Cut out device, instruction Read Controller, command decoder, signal controller and commander sender.
Configuration module 62 is connected with setup module 61, for configuring one group of state controller, the state for per thread
The quantity of the controller initial address of the memory headroom where the address of block, end address and instruction block for storing instruction,
And configure reading instruction enabling signal.
Specifically, per thread is all controlled by one group of status register.Status register is configured by cpu bus, is matched
The quantity of the initial address of the memory headroom where the address of store instruction block, end address and instruction block is set, and configures reading
Instruction fetch enabling signal.As shown in figure 3, marking off one piece of memory space in Installed System Memory, the data stored are each fingers
The actual address for enabling block obtains the actual address of instruction by accessing this memory space.The full dummy status of this memory space by
Read pointer and write pointer determine.After CPU has configured status register, instruction control unit can work independently, and not need CPU again
Configuration is participated in, to alleviate the live load of CPU.
Arbitration modules 63 are connected with configuration module 62, are read for sending descriptor pointer according to the information of status register
To bus, the initial address of the instruction segment returned according to bus and end address send control command read requests to total for request
Line, and ask moderator to arbitrate different data read requests by fetching.
Specifically, according to the information of status register, descriptor pointer read requests is sent and refer to bus, bus transfer is returned
Descriptor pointer data be instruction segment initial address and end address.According to the initial address of instruction segment and terminate ground
Location sends control command read requests bus.Wherein, two different data read requests are carried out by fetching request moderator
Request arbitration.As shown in figure 4, single thread includes the request of data of two kinds of different levels of high priority and low priority, write from memory
The sequence of low priority can be seized by recognizing high priority.For fetching asks moderator, Address requests are excellent in single thread
Prior to request of data, high priority is prior to low priority.Request of data between different threads is using polling mode realization, i.e.,
1~N number of thread intermediate rotation request, the thread of pause will be skipped directly.Fetching request moderator asks each data
Corresponding request source can all be recorded by asking；When request data returns, also refer to judge IA according to record label
It enables data and belongs to which thread.
Command process module 64 is connected with arbitration modules 63, is used for according to current instruction label, by the finger of bus transfer
Enable data by instructing memory arbitration device to store memory space corresponding on piece memory；By instructing Read Controller using wheel
Inquiry mode arbitrates the command reading request of different threads, reads the instruction on piece memory according to polling sequence, and pass through decoding
Selector transmits instructions to corresponding command decoder；The director data for again being instructed the outfit of equipment by command decoder
It is sent to commander sender with device flag, instructs corresponding marker to be sent to signal control the synchronous communication of equipment room
Device, and the corresponding interrupt signal of interrupt instruction is sent to system；Director data is sent to correspondence by commander sender
Equipment.
As shown in figure 5, according to current instruction label, the director data of bus transfer is stored by instruction memory arbitration device
In the corresponding memory space of on piece memory.In the corresponding fifo controller in channel that synchronization is chosen by instruction memory arbitration device
To instructing corresponding memory space to be written and read operation.
It instructs reader using the command reading request of polling mode arbitration different threads, on piece is read according to polling sequence
Instruction in memory, and by decoding selector, corresponding command decoder is transmitted to carry out decoded operation to instruction.
Specifically, according to the different type of the instruction of reading, command decoder executes different operations：
(1) if described instruction synchronizes the instruction of communication between distinct device, command decoder after decoding will be right
The marker answered is sent to signal controller.
(2) if described instruction is the configuration-direct of equipment, command decoder sends director data and device flag together
To commander sender, so that director data is sent to corresponding equipment by commander sender.
(3) described instruction is interrupt instruction, and corresponding interrupt signal is sent to system by command decoder.
Receiving module 65 is connected with command process module 64, for by signal controller receiving device for receiving
The feedback signal of director data.
Specifically, equipment receives corresponding director data, and after carrying out relevant operation according to the device flag of itself,
Feedback signal is sent to signal controller.
Handover module 66 is connected with receiving module 65, for being instructed according to the feedback signal of reception and synchronous communication, passes through
Signal controller switches over multiple and different threads and executes sequence with control device.
Specifically, signal controller is arbitrated according to the feedback signal of reception and synchronous communication instruction, to multiple and different
Thread switches over, and sequence is executed to control device.
So far, that is, primary complete multichannel instruction control is completed.Later, bus is looked by access state register
The reading situation of present instruction is ask, and new instruction block storage address is sent to status register.Repeat the above steps S1-
S6, until all instruction end of transmissions.
It should be noted that it should be understood that the modules of system above division be only a kind of division of logic function,
It can completely or partially be integrated on a physical entity in actual implementation, it can also be physically separate.And these modules can be with
All realized in the form of software is called by processing element；It can also all realize in the form of hardware；It can also part mould
Block calls the form of software to realize by processing element, and part of module is realized by the form of hardware.For example, x modules can be
The processing element individually set up can also be integrated in some chip of above-mentioned apparatus and realize, in addition it is also possible to program generation
The form of code is stored in the memory of above-mentioned apparatus, is called by some processing element of above-mentioned apparatus and is executed the above x moulds
The function of block.The realization of other modules is similar therewith.In addition these modules can completely or partially integrate, can also be only
It is vertical to realize.Processing element described here can be a kind of integrated circuit, the processing capacity with signal.During realization,
Each step of the above method or more modules can be by the integrated logic circuit of the hardware in processor elements or soft
The instruction of part form is completed.
For example, the above module can be arranged to implement one or more integrated circuits of above method, such as：
One or more specific integrated circuits (ApplicationSpecificIntegratedCircuit, abbreviation ASIC), or, one
Or multi-microprocessor (digitalsingnalprocessor, abbreviation DSP), or, one or more field-programmable gate array
It arranges (FieldProgrammableGateArray, abbreviation FPGA) etc..For another example, when some above module is dispatched by processing element
When the form of program code is realized, which can be general processor, such as central processing unit
(CentralProcessingUnit, abbreviation CPU) or it is other can be with the processor of caller code.For another example, these modules can
To integrate, realized in the form of system on chip (system-on-a-chip, abbreviation SOC).
As shown in fig. 7, in an embodiment, the multichannel instruction control unit of adjustable instruction priority of the invention includes
Processor 71 and memory 72.
The memory 72 is for storing computer program.
Preferably, the memory 72 includes：ROM, RAM, magnetic disc or CD etc. are various can to store program code
Medium.
The processor 71 is connected with the memory 72, the computer program for executing the storage of the memory 72,
So that the multichannel instruction control unit of the adjustable instruction priority executes the multichannel of above-mentioned adjustable instruction priority
Command control method.
Preferably, the processor 71 can be general processor, including central processing unit
(CentralProcessingUnit, abbreviation CPU), network processing unit (NetworkProcessor, abbreviation NP) etc.；It can be with
It is digital signal processor (DigitalSignalProcessing, abbreviation DSP), application-specific integrated circuit
(ApplicationSpecificIntegratedCircuit, abbreviation ASIC), field programmable gate array (Field-
ProgrammableGateArray, abbreviation FPGA) either other programmable logic device, discrete gate or transistor logic device
Part, discrete hardware components.
In an embodiment, the multichannel command control system of adjustable instruction priority of the invention include it is above-mentioned can
The multichannel instruction control unit of adjust instruction priority, fetching request moderator, instruction memory arbitration device, refers to status register
Enable Read Controller, command decoder, signal controller and commander sender；
The status register for storing instruction the initial address of the memory headroom where the address of block, end address with
And the quantity of instruction block, and configure reading instruction enabling signal；
The fetching request moderator is for arbitrating different data read requests；
Described instruction memory arbitration device is used for the instruction data storage of bus transfer is empty to the corresponding storage of on piece memory
Between；
Described instruction Read Controller is used for the command reading request using polling mode arbitration different threads, according to poll
Sequence reads the instruction on piece memory；
Described instruction decoder is used to the director data of the outfit instruction of equipment and device flag being sent to instruction and send
The synchronous communication of equipment room is instructed corresponding marker to be sent to signal controller by device, and interrupt instruction is corresponding
Interrupt signal is sent to system；
The signal controller for receiving device for the feedback signal of the director data received, and to it is multiple not
It is switched over thread and sequence is executed with control device；
Described instruction transmitter is used to the director data of equipment being sent to corresponding equipment.
In conclusion the multichannel command control method and system, controller of the adjustable instruction priority of the present invention carry
The high working performance of whole chip, and solve the problems, such as that priority is seized, in the way of single interface, realize multiple figures
Synchronization between shape processing module, control is simple, saves a large amount of interface resource and chip area；In fine granularity multithreading
In the case of, when thread pauses, the instruction in other threads can be read, so as to hide because long and short pause and
Caused loss of throughput；In fine granularity situation, the intertexture of thread can eliminate full empty slot；Since each clock cycle can
Change transmitting thread, therefore the operation of long delay can be hidden, greatly improves the performance of chip；Support two-stage chained list indirect
Addressing, it is only necessary to which one piece of minimum fixed space stores a small amount of chain table address of the first order, and the address of storage is instructed not have then
Any restrictions, to overcome memory headroom divide and managerial problem, save hardware resource, also allow for peopleware into
Row exploitation, flexibility are high.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial exploitation value
Value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (8)
1. a kind of multichannel command control method of adjustable instruction priority, which is characterized in that include the following steps：
Status register, fetching request moderator, instruction memory arbitration device, instruction Read Controller, command decoder, letter are set
Number controller and commander sender；
One group of state controller, the state controller memory where the address of block for storing instruction are configured for per thread
The quantity of the initial address in space, end address and instruction block, and configure reading instruction enabling signal；
Descriptor pointer read requests are sent to bus according to the information of status register, and the instruction segment returned according to bus rises
Beginning address and end address send control command read requests to bus, and by fetching ask moderator arbitrate different data
Read requests；
According to current instruction label, by the director data of bus transfer by instructing memory arbitration device to store on piece memory pair
The memory space answered；By instructing Read Controller using the command reading request of polling mode arbitration different threads, according to wheel
Inquiry sequence reads the instruction on piece memory, and transmits instructions to corresponding command decoder by decoding selector；Lead to again
The director data and device flag for crossing outfit instruction of the command decoder by equipment are sent to commander sender, by the same of equipment room
The corresponding marker of step communication instruction is sent to signal controller, and the corresponding interrupt signal of interrupt instruction is sent to and is
System；Director data is sent to corresponding equipment by commander sender；
By signal controller receiving device for the feedback signal of the director data received；
It is instructed according to the feedback signal of reception and synchronous communication, multiple and different threads is switched over to control by signal controller
Control equipment executes sequence.
2. the multichannel command control method of adjustable instruction priority according to claim 1, which is characterized in that described
Fetching request moderator arbitration principle be：
Address requests are prior to request of data in single thread, and high priority is prior to low priority；
Request of data between different threads realizes that the thread of pause will be skipped directly using polling mode.
3. the multichannel command control method of adjustable instruction priority according to claim 1, which is characterized in that same
The corresponding fifo controller in channel that one moment was chosen by instruction memory arbitration device is to instructing corresponding memory space to be written and read
Operation.
4. a kind of multichannel command control system of adjustable instruction priority, which is characterized in that including setup module, configuration mould
Block, arbitration modules, command process module, receiving module and handover module；
The setup module is for being arranged status register, fetching request moderator, instruction memory arbitration device, instruction reading control
Device, command decoder, signal controller and commander sender；
The configuration module is used to configure one group of state controller, state controller block for storing instruction for per thread
Address where the initial address of memory headroom, the quantity of end address and instruction block, and configure reading instruction and start letter
Number；
The arbitration modules are used to send descriptor pointer read requests to bus, according to bus according to the information of status register
The initial address of the instruction segment of return and end address send control command read requests to bus, and ask to arbitrate by fetching
Device arbitrates different data read requests；
Command process module is used for according to current instruction label, by the director data of bus transfer by instructing memory arbitration device
Store memory space corresponding on piece memory；By instructing Read Controller using the instruction of polling mode arbitration different threads
Read requests read the instruction on piece memory according to polling sequence, and are transmitted instructions to by decoding selector corresponding
Command decoder；The director data of the outfit instruction of equipment and device flag instruction is sent to by command decoder again to send
The synchronous communication of equipment room is instructed corresponding marker to be sent to signal controller by device, and interrupt instruction is corresponding
Interrupt signal is sent to system；Director data is sent to corresponding equipment by commander sender；
The receiving module is used for through signal controller receiving device for the feedback signal of the director data received；
The handover module is used to be instructed according to the feedback signal of reception and synchronous communication, by signal controller to multiple and different
Thread is switched over executes sequence with control device.
5. the multichannel command control system of adjustable instruction priority according to claim 4, which is characterized in that described
Fetching request moderator arbitration principle be：
Address requests are prior to request of data in single thread, and high priority is prior to low priority；
Request of data between different threads realizes that the thread of pause will be skipped directly using polling mode.
6. the multichannel command control system of adjustable instruction priority according to claim 4, which is characterized in that same
The corresponding fifo controller in channel that one moment was chosen by instruction memory arbitration device is to instructing corresponding memory space to be written and read
Operation.
7. a kind of multichannel instruction control unit of adjustable instruction priority, which is characterized in that including processor and memory；
The memory is for storing computer program；
The processor is used to execute the computer program of the memory storage, so that the adjustable instruction priority is more
Channel instruction controller perform claim requires the multichannel command control method of the adjustable instruction priority described in one of 1-3.
8. a kind of multichannel command control system of adjustable instruction priority, which is characterized in that including described in claim 7
The multichannel instruction control unit of adjustable instruction priority, status register, fetching request moderator, instruction memory arbitration device,
Instruct Read Controller, command decoder, signal controller and commander sender；
The status register initial address of the memory headroom where the address of block, end address and refers to for storing instruction
The quantity of block is enabled, and configures reading instruction enabling signal；
The fetching request moderator is for arbitrating different data read requests；
Described instruction memory arbitration device is used for the instruction data storage of bus transfer to the corresponding memory space of on piece memory；
Described instruction Read Controller is used for the command reading request using polling mode arbitration different threads, according to polling sequence
Read the instruction on piece memory；
Described instruction decoder is used to the director data of the outfit instruction of equipment and device flag being sent to commander sender, will
The synchronous communication of equipment room instructs corresponding marker to be sent to signal controller, and the corresponding interruption of interrupt instruction is believed
Number it is sent to system；
The signal controller is used for receiving device for the feedback signal of the director data received, and to multiple and different lines
Journey is switched over executes sequence with control device；
Described instruction transmitter is used to the director data of equipment being sent to corresponding equipment.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110362347A (en) * | 2019-07-18 | 2019-10-22 | 成都夸克光电技术有限公司 | A kind of real-time priority band-wise processing device and control method |
| CN110659072A (en) * | 2019-09-26 | 2020-01-07 | 深圳忆联信息系统有限公司 | Pluggable command issuing acceleration method and device based on Queue structure |
| CN111707851A (en) * | 2020-05-05 | 2020-09-25 | 许昌开普检测研究院股份有限公司 | Multi-channel alternating current signal state sequence sequential control generator |
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| CN114138341A (en) * | 2021-12-01 | 2022-03-04 | 海光信息技术股份有限公司 | Scheduling method, device, program product and chip of micro-instruction cache resources |
| CN114328321A (en) * | 2022-03-16 | 2022-04-12 | 宜科(天津)电子有限公司 | Data sampling and communication method in encoder, single chip microcomputer and storage medium |
| CN114584420A (en) * | 2022-05-06 | 2022-06-03 | 艾德克斯电子（南京）有限公司 | Multi-machine equipment networking architecture |
| CN115658150A (en) * | 2022-10-31 | 2023-01-31 | 海光信息技术股份有限公司 | Instruction distribution method, processor, chip and electronic equipment |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1518691A (en) * | 2001-06-22 | 2004-08-04 | ض� | Method and apparatus for assigning threal priority in multi-threaded processor |
| US20080155233A1 (en) * | 2003-04-25 | 2008-06-26 | John Wesley Ward | Apparatus for adjusting instruction thread priority in a multi-thread processor |
| CN101334766A (en) * | 2008-06-30 | 2008-12-31 | 东软飞利浦医疗设备系统有限责任公司 | Paralleling microprocessor and its realization method |
| CN101763251A (en) * | 2010-01-05 | 2010-06-30 | 浙江大学 | Instruction decode buffer device of multithreading microprocessor |
| CN102231142A (en) * | 2011-07-21 | 2011-11-02 | 浙江大学 | Multi-channel direct memory access (DMA) controller with arbitrator |
| CN102414659A (en) * | 2009-04-28 | 2012-04-11 | 想象技术有限公司 | Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor |
| CN103262030A (en) * | 2010-12-16 | 2013-08-21 | 英特尔公司 | A fast and linearizable concurrent priority queue via dynamic aggregation of operations |
-
2017
- 2017-12-26 CN CN201711433361.5A patent/CN108279927B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1518691A (en) * | 2001-06-22 | 2004-08-04 | ض� | Method and apparatus for assigning threal priority in multi-threaded processor |
| US20080155233A1 (en) * | 2003-04-25 | 2008-06-26 | John Wesley Ward | Apparatus for adjusting instruction thread priority in a multi-thread processor |
| CN101334766A (en) * | 2008-06-30 | 2008-12-31 | 东软飞利浦医疗设备系统有限责任公司 | Paralleling microprocessor and its realization method |
| CN102414659A (en) * | 2009-04-28 | 2012-04-11 | 想象技术有限公司 | Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor |
| CN101763251A (en) * | 2010-01-05 | 2010-06-30 | 浙江大学 | Instruction decode buffer device of multithreading microprocessor |
| CN103262030A (en) * | 2010-12-16 | 2013-08-21 | 英特尔公司 | A fast and linearizable concurrent priority queue via dynamic aggregation of operations |
| CN102231142A (en) * | 2011-07-21 | 2011-11-02 | 浙江大学 | Multi-channel direct memory access (DMA) controller with arbitrator |
Non-Patent Citations (1)
| Title |
|---|
| 胡孔阳 等: "一种可配优先级Round-Robin仲裁器实现", 《中国集成电路》 * |
Cited By (14)
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|---|---|---|---|---|
| CN110362347A (en) * | 2019-07-18 | 2019-10-22 | 成都夸克光电技术有限公司 | A kind of real-time priority band-wise processing device and control method |
| CN110362347B (en) * | 2019-07-18 | 2023-02-28 | 成都夸克光电技术有限公司 | Real-time priority multichannel processor and control method |
| CN110659072A (en) * | 2019-09-26 | 2020-01-07 | 深圳忆联信息系统有限公司 | Pluggable command issuing acceleration method and device based on Queue structure |
| CN110659072B (en) * | 2019-09-26 | 2021-09-14 | 深圳忆联信息系统有限公司 | Pluggable command issuing acceleration method and device based on Queue structure |
| CN111707851B (en) * | 2020-05-05 | 2022-08-16 | 许昌开普检测研究院股份有限公司 | Multi-channel alternating current signal state sequence sequential control generator |
| CN111707851A (en) * | 2020-05-05 | 2020-09-25 | 许昌开普检测研究院股份有限公司 | Multi-channel alternating current signal state sequence sequential control generator |
| CN113596867A (en) * | 2021-06-17 | 2021-11-02 | 青岛中科英泰商用系统股份有限公司 | 4g module control method and device based on FreeRTOS system |
| CN113596867B (en) * | 2021-06-17 | 2024-05-07 | 青岛中科英泰商用系统股份有限公司 | Control method and device for 4g module based on FreeRTOS system |
| CN114138341A (en) * | 2021-12-01 | 2022-03-04 | 海光信息技术股份有限公司 | Scheduling method, device, program product and chip of micro-instruction cache resources |
| CN114328321A (en) * | 2022-03-16 | 2022-04-12 | 宜科(天津)电子有限公司 | Data sampling and communication method in encoder, single chip microcomputer and storage medium |
| CN114584420A (en) * | 2022-05-06 | 2022-06-03 | 艾德克斯电子（南京）有限公司 | Multi-machine equipment networking architecture |
| CN114584420B (en) * | 2022-05-06 | 2022-08-02 | 艾德克斯电子（南京）有限公司 | Multi-machine equipment networking architecture |
| CN115658150A (en) * | 2022-10-31 | 2023-01-31 | 海光信息技术股份有限公司 | Instruction distribution method, processor, chip and electronic equipment |
| CN118171612A (en) * | 2024-05-14 | 2024-06-11 | 北京壁仞科技开发有限公司 | Method, device, storage medium and program product for optimizing instruction cache |
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