CN109471816B - Descriptor-based PCIE bus DMA controller and data transmission control method - Google Patents
Descriptor-based PCIE bus DMA controller and data transmission control method Download PDFInfo
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Abstract
The invention provides a descriptor-based PCIE bus DMA controller and a data transmission control method, which comprise the following steps: the system comprises a TLP sending engine, a TLP receiving engine, an interface access control module, a DMA transmission control module, a descriptor access control module, a multi-DMA channel control module, a control state register and a DMA channel buffer. The DMA transmission process of the DMA controller designed by the invention is completely controlled and realized by the descriptor, thereby improving the data bandwidth and the transmission efficiency; the DMA data transmission can be configured with a plurality of DMA channels, and the priority, the transmission trigger threshold value and the overtime time of each DMA channel can be programmed, so that the data transmission real-time performance of a specific channel can be ensured while the data transmission is transmitted according to the high and low priorities; the uploading/issuing data cache of all DMA channels can realize dynamic management, realize multichannel DMA concurrent transmission and ensure the use efficiency of DMA transmission bandwidth.
Description
Technical Field
The invention belongs to the field of data transmission control, and particularly relates to a descriptor-based PCIE bus DMA controller and a data transmission control method.
Background
The PCIE bus technology is a third generation I/O interconnect bus, and the PCIE bus is a high-bandwidth transmission solution with high cost performance in desktop computers, communication platforms, servers, workstations, mobile communications, and embedded devices. In recent years, the PCIE bus technology has gained more and more applications in many high-performance integrated electronic platforms and systems, and DMA (Direct Memory Access) data transmission is one of the most common technical means for exerting the high bandwidth and high performance of the PCIE bus. In many PCIE bus products on the market, DMA controllers are integrated, but they are all oriented to generalized and traditional application scenarios, and in some application scenarios requiring simultaneous transmission of multiple DMA channels and multiple data with different priorities, the DMA controllers cannot adapt to application requirements well.
Patent document CN 105988953a discloses a DMA controller and a data transmission method, which can complete external chips and data transmission according to transmission parameters configured by a CPU of a CPUData uploading and sending operations between the CPUs are carried out, and competition caused by the data uploading and sending operations is avoided through an arbitration mode. Patent document CN105320625A discloses a PCIe-based DMA transmission method for hardware packets, which obtains PayLoad through hardwaremaxParameters and use of PayLoadmaxAnd the data packets with the length are subjected to DMA transmission so as to improve the DMA transmission efficiency. Patent document CN106951388A discloses a PCIe-based DMA data transmission method and system, where the method and system can select a corresponding DMA channel from multiple DMA channels to transmit data under the control of a DMA instruction, and transmit different types of data in different channels, thereby reducing the complexity of data transmission.
As can be seen from the above, the current PCIE bus DMA controller and the related patent achievements do not relate to multi-channel transmission or do not consider performing automated processing on data of multiple channels of the DMA according to different priorities in the multi-channel DMA transmission, and cannot meet the application system requirement of simultaneous transmission of multiple DMA channels and multiple data with different priorities.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a descriptor-based PCIE bus DMA controller and a data transmission control method, which meet the requirements of multi-channel multi-priority and high-capacity data transmission.
The invention is realized by the following technical scheme:
a descriptor-based PCIE bus DMA controller, comprising:
a TLP sending engine, configured to complete framing and sending of PCIE bus transaction packets;
a TLP receive engine, configured to complete receiving and parsing of a PCIE bus transaction layer packet;
the interface access control module is used for realizing the generation of interface time sequence and data synchronous control;
the DMA transmission control module is used for realizing DMA data transmission control;
the descriptor access control module is used for realizing the interaction of the descriptor information of the DMA controller and the descriptor information of the memory of the host computer; under the control of the descriptor information, initiating a DMA transmission request to a DMA transmission control module according to the channel arbitration result of the multiple DMA channel control module;
the multi-DMA channel control module arbitrates multiple channels according to the configured DMA channel priority and channel starting threshold and the cached state information of each DMA channel, selects the DMA channel needing service and submits the DMA channel to the descriptor access control module;
DMA channel cache for temporarily storing data of the DMA channels, wherein each DMA channel is provided with a data issuing cache and a data uploading cache, each DMA channel needs to be configured with a group of descriptors, and the descriptor addresses in the same group are continuous; and configuring the priority of the DMA channel according to the real-time requirement of the data of the DMA channel on transmission.
Preferably, the controller further comprises a control status register for storing the working status information of the DMA controller.
Preferably, the DMA channel buffer is in the form of a FIFO.
A descriptor-based DMA data transmission control method for a PCIE bus comprises the following DMA data transmission control processes:
the uploading process of the data comprises the following steps:
the multiple DMA channel control module monitors the uploading cache of each DMA channel, and when a certain DMA channel threshold value or an overtime condition is met, the multiple DMA channel control module initiates a DMA transmission application of the specified DMA channel to the descriptor access control module; after receiving the DMA transmission application sent by the multi-DMA channel control module, the descriptor access control module indexes the descriptor of the appointed DMA channel, generates DMA transmission length, DMA uploading cache address and DMA target address signals, and starts the DMA transmission control module; the DMA transmission control module reads data with corresponding length from an upload data cache of a specified DMA channel according to the control information sent by the descriptor access control module and uploads the data to the interface access control module; the interface access control module receives the upload data sent by the DMA transmission control module, initiates a TLP application to a TLP sending engine, and the TLP sending engine generates a TLP written in a host memory and fills the upload data into a host memory cache region pointed by the descriptor;
when a plurality of DMA channels meet DMA transmission conditions, the multi-DMA channel control module arbitrates according to DMA channel priorities, and the DMA channel with high priority preferentially uses DMA data transmission;
the data issuing process comprises the following steps:
when a host system needs to issue data to a specified DMA channel, writing a buffer pointer and data length information of the data to be sent into an issued data descriptor, writing a control register of a DMA controller, starting DMA transmission of the specified DMA channel, judging whether the current channel can start the DMA transmission of the current channel or not by a multi-DMA channel control module according to the buffer information, and if the current channel DMA does not meet DMA transmission conditions, checking whether DMA uploading data transmission is needed or not; when DMA uploading data transmission is not needed, polling is carried out from the DMA data issuing description of the high-priority channel, and after polling is carried out to the data issuing descriptor of a certain channel, whether the issuing cache meets the DMA transmission condition is checked, if not, the next channel DMA data issuing descriptor is polled until the DMA channel with the lowest priority is polled; when the data of the issuing descriptor needs to be issued and transmitted and the multiple DMA channel control module gives the condition of meeting the DMA transmission, the descriptor access control module starts the DMA operation;
the method comprises the steps that a DMA transmission control module receives a DMA issued data request of a descriptor access control module, according to an applied DMA channel, a DMA source address and a DMA data length, the DMA transmission control module sends a TLP sending request to a TLP sending engine, the TLP sending engine sends a memory reading TLP packet to a host after receiving the request, the TLP receiving engine receives and analyzes a read-out TLP packet which is returned by the host and is packaged with issued data of a specified buffer area, the data are returned to the DMA transmission control module after being analyzed, and the DMA transmission control module conducts data sorting processing on the read-out data according to a PCIE bus timing sequence and then writes the read-out data into the issued data buffer area of the specified DMA channel.
Preferably, when the length of the uploaded data is smaller than the configured MaxPayloadSize parameter, the transmission is completed by using a write memory TLP; when the uploaded data is greater than the MaxPayloadSize parameter, the DMA transfer control module divides the uploaded data into a plurality of TLP packets for uploading.
Preferably, when the data of the low-priority DMA channel is being uploaded, and the high-priority DMA channel meets the DMA transfer condition, the high-priority DMA channel preempts the usage right of the DMA transfer control module.
Preferably, when the descriptor access control module polls the descriptor of the issued data, if the uploaded data meets the DMA transmission condition, the polling process is suspended, the descriptor access control module initiates a DMA data uploading request to the DMA transmission control module, and after the data uploading process is finished, the polling process of the descriptor of the issued data is returned.
Preferably, when the length of the downlink data is smaller than the configured MaxPayloadSize parameter, one memory-reading TLP is used to complete transmission; when the downlink data is greater than the MaxPayloadSize parameter, the DMA transfer control module divides the downlink data into a plurality of TLP packets for downlink.
Preferably, before data transmission, an initialization operation is required: initializing an upload descriptor start address and a issue descriptor start address of each DMA channel, a priority of each DMA channel, and a threshold and timeout time of each DMA.
Compared with the prior art, the invention has the following beneficial technical effects:
(1) the DMA transmission process of the DMA controller designed by the invention is completely controlled and realized by the descriptor, thereby maximally reducing the load of a CPU and improving the data bandwidth and the transmission efficiency;
(2) in the invention, the DMA data transmission can be configured with a plurality of DMA channels, and the priority, the transmission trigger threshold value and the overtime time of each DMA channel can be programmed, so that the data transmission real-time performance of a specific channel can be ensured while the data transmission is transmitted according to high and low priorities;
(3) the uploading/issuing data cache of all DMA channels can realize dynamic management, improve the transmission size of data blocks as much as possible, realize multichannel DMA concurrent transmission and ensure the use efficiency of DMA transmission bandwidth.
The invention provides a DMA data transmission control method for dynamic processing of high-capacity and multi-priority channels based on a PCIE bus architecture, which is suitable for the field of high-speed data transmission control of data of various data types and various different priorities.
Drawings
FIG. 1 is a functional block diagram of a DMA controller according to the present invention;
FIG. 2 is a block diagram of a DMA controller according to the present invention;
FIG. 3 is a DMA issued data cache descriptor;
FIG. 4 is a DMA upload data cache descriptor;
in fig. 2: the system comprises a TLP sending engine 1, a TLP receiving engine 2, an interface access control module 3, a DMA transmission control module 4, a descriptor access control module 5, a multi-DMA channel control module 6, a control status register 7, a DMA channel 1 cache 8, a DMA channel 2 cache 9 and a DMA channel 3 cache 10. The system comprises a PCIE bus TLP sending interface 11, a PCIE bus TLP receiving interface 12, a PCIE bus TLP sending request interface 13, a PCIE bus TLP sending request interface 14, a PCIE bus TLP receiving decoded read-write request and read-completion data interface signal 15, a DMA read-write request interface 16, a DMA read-return data interface 17, a host to control/status register access interface 17, a DMA transfer start interface 18, a DMA channel control module communication arbitration result signal interface 19, a control/status register module control/status signal interface 20, a DMA channel cache reading interface 21, a DMA channel cache writing interface 22, a DMA channel cache status information 23, DMA controller side access interfaces 24, 25, and 26 of each DMA channel cache, and local side access interfaces 27, 28, and 29 of each DMA channel cache.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
The descriptor-based PCIE bus DMA data transmission control method is used for a scene that a PCIE bus interface transmits various data streams with different priorities, works on a transaction layer of a PCIE bus controller, provides a standard PCIE controller transaction layer interface, and is convenient for realizing DMA control and data transmission.
The specific functions of the control method comprise: the method comprises the steps of framing and sending a PCIE bus transaction layer packet, receiving and analyzing the PCIE bus transaction layer packet, decoding a PCIE bus access operation, generating PCIE bus read-write request control, DMA transmission control, descriptor access control, multi-DMA channel management, a control status register and multi-DMA channel cache.
In order to implement the above functions, the descriptor-based PCIE bus DMA controller of the present invention mainly includes 12 portions, and specifically includes: the system comprises a host memory buffer area, a host memory descriptor table, a TLP (Transaction Layers Packages) sending engine, a TLP receiving engine, an interface access control module, a DMA transmission control module, a descriptor access control module, a multi-DMA channel control module, a control state register and a DMA channel buffer.
Fig. 1 shows functional modules of the DMA controller according to the present invention, and the functions of the sub-modules are described below.
(1) The TLP sending engine is mainly used to complete framing and sending of PCIE bus transaction packets. When the host interface accesses the internal control/status register of the DMA controller through the PCIE bus, the read data initiates an application to the TLP sending engine by the access interface control module, and the TLP sending engine generates a read completion packet containing the read data and sends the read completion packet out through the PCIE hard core. When the DMA controller starts DMA transfer, a request is sent to the TLP sending engine, and the TLP sending engine generates a corresponding read request packet or write request packet and sends the read request packet or write request packet out through the PCIE controller.
(2) The TLP receive engine is mainly used to complete the receiving and parsing of the PCIE bus transaction packet. When the host interface accesses the internal control/status register of the DMA controller through the PCIE bus, the TLP receive engine receives the access request TLP, and the TLP receive engine analyzes and decodes the access request packet of the host to become the read-write access request of the control/status register. When the controller executes the DMA data transmission process, the following steps are carried out: and carrying the data in the memory of the host to the target equipment through DMA read operation, wherein at the moment, the DMA controller initiates a read request TLP to the host, the host recovers a completion data packet carrying read data to a TLP receiving engine, the TLP receiving engine can analyze the read completion packet replied by the host and send the data to the DMA transmission control module for processing, and then the data is transmitted to the DMA data cache of the corresponding channel.
(3) And the interface access control module is used for realizing the generation of interface time sequence and data synchronization control. When the host executes a write operation, the module decodes a write request of the TLP receive engine, and generates a write interface timing that satisfies the control status register module. When the host executes a read operation, the access interface control module decodes a read request of the TLP receive engine, generates a read interface timing sequence for controlling the status register module, and lifts a send-read-complete packet request to the TLP send engine to return the read data to the host. When the DMA controller performs DMA transfer, the access interface control module may initiate a request to the TLP sending engine according to a data transfer request of the DMA controller, and send a DMA read request packet or a DMA write request packet to the host.
(4) And the DMA transmission control module is a control module for realizing DMA data transmission. When the multi-channel DMA control module arbitrates the DMA channel needing service, the DMA transmission control module takes out the descriptor of the corresponding channel from the descriptor access control module, and transmits the data uploaded from the specified DMA channel to the cache to the host system according to the descriptor control information. Or the data in the memory of the host system is carried to the appointed DMA channel to send the data cache. When the descriptor access control module needs to read a new descriptor from the host, the DMA transmission control module initiates DMA read transmission to the host after receiving a request for reading the descriptor, and transmits the descriptor of the host memory to the descriptor access module. When the descriptor access module needs to write the descriptor information back to the host memory, the DMA transfer control module initiates DMA write transfer to the host after receiving the request of writing the descriptor, and writes the descriptor information back to the host memory.
(5) The descriptor access control module mainly realizes two functions: realizing the interaction between the descriptor information of the DMA controller and the descriptor information of the host memory; and under the control of the descriptor information, initiating a DMA transfer request to the DMA transfer control module according to the channel arbitration result of the multiple DMA channel control module.
(6) And the multi-DMA channel control module arbitrates multiple channels according to the configured channel priority and channel starting threshold and the cached state information of each DMA channel, and selects the DMA transmission channel to be served and submits the selected DMA transmission channel to the descriptor access control module.
(7) And the control state register module is used for storing the control information of the host and the working state information of the DMA controller.
(8) Each DMA channel is provided with an issued data cache and an uploaded data cache, and the priority of the DMA channel is configured according to the real-time requirement of the data of the DMA channel on transmission. The buffer memory is in FIFO form and is used for temporarily storing the data of the DMA channel.
Specific examples are as follows.
According to the present invention, a detailed implementation is designed, and the structure of the DMA controller is shown in FIG. 2. The DMA controller of the invention needs to carry out initialization operation before use, and the initialization operation comprises two parts:
(1) and (3) initializing a host memory, wherein the host memory needs to open a descriptor table space and a data cache space, and two descriptor tables of each DMA channel are an upload data descriptor table and a release data descriptor table respectively. Each descriptor table contains a plurality of address-sequential descriptors, each of which points to a unique cache region in the memory of the host system.
Fig. 4 shows DMA upload data buffer descriptors (TDES), where the TDES is used for data transmission from a PCIE node device to a host memory. Fig. 3 shows a DMA issue data buffer descriptor, and an issue descriptor (RDES) is used for data transmission from a host memory to a PCIE node device. When the 'valid identifier' is 1, the descriptor belongs to the DMA controller; at 0, the descriptor belongs to the host CPU. When the tail bit of the descriptor table is 1, the descriptor table reaches the last descriptor and returns to the base address to form a descriptor ring. "cache size" means the size of bytes currently cached. The "channel number" identifies the DMA channel. The interrupt enable bit is 1, and the interrupt is started after the transmission is completed. The "data upload state" is a data upload state returned by the node device, such as error information. Each DMA channel needs to be configured with a set of descriptors, with the descriptor addresses within the same set consecutive.
(2) The DMA controller initializes the upload/issue descriptor start address of each DMA channel, the priority of each DMA channel, and the threshold and timeout time of each DMA.
After the initialization is completed, the DMA controller is started to be in a working state, the descriptor access control module 5 starts descriptor reading operation, and the DMA upload/issue descriptors of each channel are read from the memory of the host into the DMA controller.
The uploading process of the data comprises the following steps:
when data is filled in a certain DMA channel data uploading data cache, the multiple DMA channel control module 6 monitors each channel uploading cache, and when the threshold value or the overtime condition of the channel is met, the multiple DMA channel control module 6 initiates a DMA transmission application to the descriptor access control module 5.
After receiving the DMA transfer application sent by the multiple DMA channel control module 6, the descriptor access control module 5 indexes the descriptor of the designated channel and generates signals such as DMA transfer length, DMA upload buffer address, DMA destination address, and the like, and starts the DMA transfer control module 4 through the DMA transfer start interface 18 to start the DMA transfer operation. The DMA transfer control module 4 reads data with corresponding length from the upload data buffer of the specified channel according to the control information sent by the descriptor access control module 5, and uploads the data to the interface access control module 3 through the DMA read-write request interface 15. The interface access control module 3 receives the upload data sent by the DMA transfer control module 4, and then initiates a TLP application to the TLP sending engine 1 through the PCIE bus TLP sending request interface 13, the TLP sending engine 1 generates a TLP written in the host memory, and fills the upload data into the host memory buffer area pointed by the descriptor.
When the length of the uploaded data is smaller than the configured Max Payload Size parameter, the transmission can be completed by using one write memory TLP. When the uploaded data is greater than the Max Payload Size parameter, the DMA transfer control module 4 divides the uploaded data into a plurality of TLP packets for uploading.
When a plurality of DMA channels meet the DMA transmission condition, the multi-DMA channel control module 6 arbitrates according to the DMA channel priority, and the channel with high priority preferentially uses DMA data transmission. When the data of the low-priority DMA channel is being uploaded, the high-priority DMA channel meets the DMA transmission condition, and the channel with high priority preempts the use right of the DMA transmission control module 4. If the data of a certain DMA channel has higher requirement on the real-time property of transmission, the priority of the channel can be set to be the highest, and the triggering threshold value and the timeout time are set to be a smaller value, so that the residence time of the data of the channel in the cache is short, and the real-time property of the data transmission of the channel can be effectively improved.
The data issuing process comprises the following steps:
when a host system needs to issue data to a certain DMA channel, a buffer pointer and data length information of the data to be sent are written in an issued data descriptor, a control register of a DMA controller is written, DMA transmission of a specified channel is started, the multiple DMA channel control module 6 judges whether the DMA transmission of the current channel can be started by the current channel according to the buffer information, and if the DMA of the current channel does not meet DMA transmission conditions, whether DMA uploading data transmission is needed is checked. When DMA uploading data transmission is not needed, polling is carried out from the DMA data issuing description of the high-priority channel, after polling is carried out to the data issuing descriptor of a certain channel, whether the issuing cache meets the DMA transmission condition is checked, if not, the next channel DMA data issuing description is polled until the DMA channel with the lowest priority is polled. When the sending descriptor has data to send and transmit and the multiple DMA channel control module 6 gives that the DMA transmission condition is satisfied, the descriptor access control module 5 starts the DMA operation.
The DMA transfer control module 4 receives the DMA send-down data request from the descriptor access control module 5, according to the DMA channel, the DMA source address, and the DMA data length that are applied for, the DMA transfer control module 4 sends a TLP send request to the TLP sending engine 1 through the interface access control module 3, the TLP sending engine 1 sends a read memory TLP packet to the host after receiving the request, the host packages the send-down data of the specified buffer region in the read completion TLP packet and returns the read completion TLP packet to the TLP receiving engine 2 through the PCIE bus TLP receiving interface 12, the TLP receiving engine 2 receives the read completion packet returned by the host to analyze and return the data to the DMA transfer control module 4, and the DMA transfer control module 4 performs data sorting processing on the read completion data according to the PCIE bus timing sequence and then writes the data into the send-down data buffer region of the specified DMA channel through the DMA channel cache writing.
When the descriptor access control module 5 polls the descriptor of the issued data, if the uploaded data meets the DMA transmission condition, the polling process is suspended, the descriptor access control module 5 initiates a DMA data uploading request to the DMA transmission control module 4, and after the data uploading process is finished, the polling process of the descriptor of the issued data is returned. The operation of preferentially processing the data uploading service can ensure that the data uploading cache in the DMA controller cannot overflow, and prevent data loss.
When the length of the downlink data is smaller than the configured Max Payload Size parameter, the transmission can be completed by using one memory TLP. When the downlink data is greater than the Max PayloadSize parameter, the DMA transfer control module 4 divides the downlink data into a plurality of TLP packets for uploading.
According to the scheme, a logic design of the controller is described by using a Verilog HDL language, and logic synthesis and layout wiring are completed; meanwhile, a DMA controller is designed, and the functions of the controller are tested. The test result shows that the invention has good implementability and the performance meets the expectation.
Claims (6)
1. A descriptor-based PCIE bus DMA data transmission control method is characterized in that based on a descriptor-based PCIE bus DMA controller, the descriptor-based PCIE bus DMA controller comprises:
a TLP sending engine, configured to complete framing and sending of PCIE bus transaction packets;
a TLP receive engine, configured to complete receiving and parsing of a PCIE bus transaction layer packet;
the interface access control module is used for realizing the generation of interface time sequence and data synchronous control;
the DMA transmission control module is used for realizing DMA data transmission control;
the descriptor access control module is used for realizing the interaction of the descriptor information of the DMA controller and the descriptor information of the memory of the host computer; under the control of the descriptor information, initiating a DMA transmission request to a DMA transmission control module according to the channel arbitration result of the multiple DMA channel control module;
the multi-DMA channel control module arbitrates multiple channels according to the configured DMA channel priority and channel starting threshold and the cached state information of each DMA channel, selects the DMA channel needing service and submits the DMA channel to the descriptor access control module;
DMA channel cache for temporarily storing data of the DMA channels, wherein each DMA channel is provided with a data issuing cache and a data uploading cache, each DMA channel needs to be configured with a group of descriptors, and the descriptor addresses in the same group are continuous; configuring DMA channel priority according to the real-time requirement of the data of the DMA channel on transmission;
the DMA data transmission control flow is as follows:
the uploading process of the data comprises the following steps:
the multiple DMA channel control module monitors the uploading cache of each DMA channel, and when a certain specified DMA channel threshold value or an overtime condition is met, the multiple DMA channel control module initiates a DMA transmission application of the specified DMA channel to the descriptor access control module; after receiving the DMA transmission application sent by the multi-DMA channel control module, the descriptor access control module indexes the descriptor of the appointed DMA channel, generates DMA transmission length, DMA uploading cache address and DMA target address signals, and starts the DMA transmission control module; the DMA transmission control module reads data with corresponding length from an upload data cache of a specified DMA channel according to the control information sent by the descriptor access control module and uploads the data to the interface access control module; the interface access control module receives the upload data sent by the DMA transmission control module, initiates a TLP application to a TLP sending engine, and the TLP sending engine generates a TLP written in a host memory and fills the upload data into a host memory cache region pointed by the descriptor;
when a plurality of DMA channels meet DMA transmission conditions, the multi-DMA channel control module arbitrates according to DMA channel priorities, and the DMA channel with high priority preferentially uses DMA data transmission;
the data issuing process comprises the following steps:
when a host system needs to issue data to a specified DMA channel, writing a buffer pointer and data length information of the data to be sent into an issued data descriptor, writing a control register of a DMA controller, starting DMA transmission of the specified DMA channel, judging whether the current channel can start the DMA transmission of the current channel or not by a multi-DMA channel control module according to the buffer information, and if the current channel DMA does not meet DMA transmission conditions, checking whether DMA uploading data transmission is needed or not; when DMA uploading data transmission is not needed, polling is carried out from the DMA data issuing description of the high-priority channel, and after polling is carried out to the data issuing descriptor of a certain channel, whether the issuing cache meets the DMA transmission condition is checked, if not, the next channel DMA data issuing descriptor is polled until the DMA channel with the lowest priority is polled; when the data of the issuing descriptor needs to be issued and transmitted and the multiple DMA channel control module gives the condition of meeting the DMA transmission, the descriptor access control module starts the DMA operation;
the method comprises the steps that a DMA transmission control module receives a DMA issued data request of a descriptor access control module, according to an applied DMA channel, a DMA source address and a DMA data length, the DMA transmission control module sends a TLP sending request to a TLP sending engine, the TLP sending engine sends a memory reading TLP packet to a host after receiving the request, the TLP receiving engine receives and analyzes a read-out TLP packet which is returned by the host and is packaged with issued data of a specified buffer area, the data are returned to the DMA transmission control module after being analyzed, and the DMA transmission control module conducts data sorting processing on the read-out data according to a PCIE bus timing sequence and then writes the read-out data into the issued data buffer area of the specified DMA channel.
2. A PCIE bus DMA data transfer control method according to claim 1, wherein when the length of the uploaded data is smaller than the configured Max Payload Size parameter, the transfer is completed using one write memory TLP; when the uploaded data is larger than the Max Payload Size parameter, the DMA transmission control module divides the uploaded data into a plurality of TLP packets for uploading.
3. The descriptor-based PCIE bus DMA data transfer control method of claim 1, wherein when data of a low priority DMA channel is being uploaded, and a high priority DMA channel meets a DMA transfer condition, the high priority DMA channel preempts a DMA transfer control module right of use.
4. The method according to claim 1, wherein when the descriptor access control module polls the descriptor for the issued data, if there is uploaded data satisfying the DMA transfer condition, the polling process is suspended, the descriptor access control module initiates a DMA data upload request to the DMA transfer control module, and after the data upload process is completed, the process returns to the polling process for the issued data descriptor.
5. A PCIE bus DMA data transfer control method according to claim 1, wherein when a downlink data length is smaller than a configured Max Payload Size parameter, a read memory TLP is used to complete the transfer; when the downlink data is greater than the Max Payload Size parameter, the DMA transmission control module divides the downlink data into a plurality of TLP packets for downlink.
6. The descriptor-based PCIE bus DMA data transfer control method of claim 1, wherein an initialization operation is required before data transfer: initializing an upload descriptor start address and a issue descriptor start address of each DMA channel, a priority of each DMA channel, and a threshold and timeout time of each DMA.
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| CN110083461B (en) * | 2019-03-29 | 2021-09-24 | 郑州信大捷安信息技术股份有限公司 | Multitasking system and method based on FPGA |
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