CN114584420B - Multi-machine equipment networking architecture - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/403—Bus networks with centralised control, e.g. polling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/423—Loop networks with centralised control, e.g. polling
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Abstract
The invention discloses a multi-machine equipment networking framework which comprises a host machine and a plurality of slave machine equipment, wherein the host machine and the slave machine equipment form an annular network, each slave machine equipment is mounted on a data bus of a multi-thread script processor, and the host machine utilizes the multi-thread script processor to control each slave machine equipment to complete a multi-machine user testing process. The invention utilizes the multi-thread script processor to control each equipment module to complete the multi-machine user test flow, the multi-thread script processor is used in the multi-machine equipment networking, the main CPU can also utilize the multi-thread function to send read-write instructions to the multi-thread script processor to complete the temporary read-write function, and the operation of the user test flow is not influenced.
Description
Technical Field
The invention relates to the technical field of networking architectures, in particular to a multi-machine equipment networking architecture.
Background
The conventional source meter multi-machine synchronization and multi-machine networking is mainly realized by GPIO (general purpose input/output) or network cables on physical media, so that the GPIO has poor anti-interference performance, more wire harnesses and high driving capability requirement, and is difficult to wire in a long distance; compared with optical fiber transmission, the network cable has the disadvantages of low speed and poor anti-interference performance.
In networking technology, the host CPU is used for decoding the instruction, and then the instruction is forwarded to each slave machine through a network according to the instruction operation object and the content. Generally realized by software, the method has great dependence on the performance and the running state of the main CPU, and when the data throughput rate is higher, the real-time and the stability are difficult to guarantee, and even the main CPU is slowed down to run.
And distributing the script to be run and the preset parameters of each machine to each channel by using a network in a multi-machine cooperation mode. Each channel operates independently, and then multi-machine synchronization is carried out by utilizing the Trig signals. The method can reduce the transmission of burst big data, and can be used for completing a certain test task by cooperation of multiple machines, the programming is troublesome, the test flow of each machine cannot be edited in one program, multiple different programs need to be written, and Trig signals are designed among the different programs to cooperate.
The conventional processor flow includes four stages of fetch, decode, execute, write back, pipeline execution, and instruction source fixing. Network devices cannot be addressed directly by machine code.
Disclosure of Invention
The invention aims to: in order to solve the defects of the prior art, a multi-machine equipment networking architecture is provided.
The invention discloses a multi-machine equipment networking framework which comprises a host and a plurality of slave machines, wherein the host and the slave machines form an annular network, each slave machine is mounted on a data bus of a multi-thread script processor of the host, and the host controls each slave machine to complete a multi-machine test flow by utilizing the multi-thread script processor.
Furthermore, the multi-thread script processor comprises a script processing core, an instruction fetching controller and a plurality of instruction fetching ports, wherein each instruction fetching port corresponds to one thread, the instruction fetching controller identifies the thread setting state and the current execution state to perform round-robin switching, the script processing core has a network routing function, and machine codes can directly address each module of the slave device on the network.
Further, the threads include a Normal thread, a system chunk thread, and a batch thread,
the Normal thread fetch is from FIFO and is used for loading parameters and programs for each slave device;
the system program block thread is used for supplementing a Normal thread or executing a local system task;
and the batch processing thread runs a complete script which is edited in advance, a complete test flow is executed, and the host machine utilizes the batch processing thread to directly control each module of the slave machine equipment to cooperatively complete a complex test task.
Further, the system program block thread is used as a supplement of the Normal thread, the circularly executed instruction block is sent to a specified address of the system program block, the Normal thread starts execution or the ARM directly starts execution, when the Normal thread finishes execution, the system program block thread automatically executes an exit instruction, and before the exit, the system program block thread calls an interrupt instruction to notify the ARM.
Further, the multi-threaded script processor instruction fetch instructions include true instructions and pseudo instructions,
the real instruction is executed and completed by the multi-thread script processor, the source operand is obtained through a data bus of the multi-thread script processor according to a data addressing mode, the target operand is generated by the multi-thread script processor, and then the target operand is sent to a target address;
the pseudo-instructions are triggered to execute by the multithreaded script processor ARM.
Furthermore, the pseudo instructions comprise blocking pseudo instructions and non-blocking pseudo instructions, when the blocking pseudo instructions are executed, the multi-thread script processor stops running, an interrupt signal is generated to the ARM, when the ARM processes an interrupt program, the current pseudo instructions of the multi-thread script processor are obtained, corresponding instruction operation is completed, and then the running of the multi-thread script processor is recovered; when the non-blocking pseudo-instruction is executed, the multi-thread script processor writes the non-blocking pseudo-instruction into the pseudo-instruction FIFO and generates an interrupt at the same time, and when the ARM processes the interrupt program, the cached pseudo-instruction is read from the FIFO to complete the corresponding instruction operation.
Furthermore, the host and the slave devices can be configured into one or more groups, and when the host and the slave devices are configured into one group, the host sends instructions to the slave devices in the group to realize the synchronization of the operation in the group; when the synchronous data is configured into a plurality of groups, the occupation right of the instruction bit is switched by the host rotation in the plurality of groups, and the groups are synchronized through the independent synchronization bit, so that the synchronization of the plurality of groups and the plurality of scripts is realized.
Furthermore, each slave device is mounted on a data bus of the multi-thread script processor of the host through an optical fiber, and the host controls each slave device to complete a multi-machine user test process through the optical fiber communication by using the multi-thread script processor. The optical fiber communication bit comprises an optical fiber instruction bit, an independent synchronization bit and a CAN bus bit which are mapped by a digital bus of the multi-thread script processor.
The invention has the beneficial effects that:
1. the invention discloses a multi-machine equipment networking architecture, which utilizes a multi-thread script processor to control each equipment module to complete a multi-machine user testing process, the multi-thread script processor is used in the multi-machine equipment networking, and a main CPU (central processing unit) can also utilize a multi-thread function to send a read-write instruction to the multi-thread script processor to complete a temporary read-write function without influencing the running of the user testing process;
2. even if the three threads are fully opened, the processing rate of each thread is also greater than the network communication rate, so that the system rate loss is avoided, the transmission speed is high, the response processing real-time performance of each channel is strong, the anti-interference performance is strong, and due to the multiplexing of the processing core and the interface, the resource overhead of the FPGA is low, and the efficiency is high;
3. the compatibility of a control mode of a host (an upper computer) is good, and both a batch processing mode and an instruction stream mode (interpretation and execution) can be supported;
4. under the working mode of the multi-machine equipment, the host can execute the local test script by using the batch processing thread, and load parameters and read back the parameters for each piece of the slave equipment by using the normal thread and the system program thread or temporarily interpenetrate the local operation task.
Drawings
Fig. 1 is a schematic diagram of a source table product networking structure through an optical fiber.
FIG. 2 is a block diagram of a multithreaded script processor as disclosed in the present invention.
Fig. 3 is a schematic diagram of group synchronization of multiple devices according to the present disclosure.
Fig. 4 is a block diagram of host information flow as disclosed herein.
Fig. 5 is a block diagram of the information flow of the slave device disclosed by the present invention.
Detailed Description
The following examples are given for the detailed implementation and specific operation of the present invention, but the scope of the present invention is not limited to the following examples.
The invention discloses a multi-machine equipment networking architecture, which comprises a host and a plurality of slave machines, wherein as shown in figure 1, in the embodiment, the host is equipment connected with an upper computer, if the host is not connected with the upper computer, one optional equipment can be used as the host, and the host and the upper computer can communicate through a network cable or GPIB (general purpose interface bus) and the like. The host (equipment 1) and each slave (equipment 2, 3 and 4) adopt optical fiber ring networking, the host forwards data and instructions issued by the host for each slave, and a plurality of pieces of equipment can be mounted on a data bus of a multithreading script processor of one piece of equipment. The device 2, the device 3 and the device 4 are mounted on a data bus of a multi-thread script processor of the device 1 through optical fibers, and the host machine controls each module of the slave machine to complete a multi-machine user test flow through optical fiber communication by using the multi-thread script processor. The optical fiber communication bit comprises an independent synchronization bit, a CAN bus bit and an optical fiber instruction bit mapped by a digital bus of the multi-thread script processor, and the independent synchronization bit CAN be configured into a Trig signal and used for transmitting the real-time Trig signal among multiple machine devices, so that multi-thread script synchronization of the multiple machine devices is realized. According to the script program setting, the signal synchronization of various application scenes is supported. The master or slave device is an electronic test device, such as a source meter. The communication material medium is not limited to optical fiber, but also includes coaxial cable, fiber optic cable, air, or any other medium suitable for electro-optical radio frequency, infrared, or other types of communications.
As shown in FIG. 2, the multithreaded script processor includes a script processing core, an instruction fetch controller, and a plurality of instruction fetches. Each instruction fetching port corresponds to one thread. And the instruction fetching controller identifies the thread setting state and the current execution state and performs round-robin switching. The script processing core has a network routing function and is used for decoding, executing and writing back, machine codes can directly address each module of the slave equipment on the optical fiber network, extra instruction configuration is not needed, and a slave CPU is not needed to participate in execution. In the multi-machine collaborative test script, programming can be simplified, and the code execution efficiency is higher.
The modules of the host and the slave devices comprise Fiber, Math, RAM, FIFO and the like. The Fiber module is an optical Fiber communication module, and the Math module is a mathematical operation module. Other English RAMs, FIFOs, ARM and CPUs are special terms of computers.
The use of a multi-threaded script processor in a multi-machine device networking, wherein the thread tasks comprise:
(1) normal thread:
taking the index source: FIFO;
the instruction flow is executed in sequence, so that the blocking can be avoided temporarily, and the address jumping is not supported;
instruction range: setting basic functions such as source and measurement;
in networking, parameters and programs can be loaded for each device through the thread.
(2) System program block thread:
in addition to the Normal instruction, since the Normal instruction fetches an instruction from the FIFO, an instruction jump cannot be performed. A circularly executed instruction block (which can be regarded as a program function) can be sent to a specified address of a system program block, and is started by a Normal thread or directly started by an ARM; when the system program block thread finishes, the system program block thread executes the quit instruction by itself. Before exiting, calling an interrupt instruction and informing the ARM.
The thread can also be used for executing the local system task, and the thread can not be blocked because other threads are blocked during operation.
(3) Batch processing thread:
compared with a system program block thread, the instruction area has larger storage space, and can run a complete script edited in advance and execute a complete test flow.
The networking architecture takes a multi-thread script processor as a processing center, and all functional modules of the equipment, including a main CPU (central processing unit), are taken as execution modules and mounted on the multi-thread script processor for uniform addressing execution.
In the working mode of the multi-machine equipment, the host machine can execute the local test script by using the batch processing thread, and load parameters and read back the parameters for each piece of the slave machine by using the normal thread and the system program thread or temporarily insert the local operation task. Compared with the method of realizing multithreading scheduling through software, the method has the advantages of no blocking processing, field protection, recovery and other problems, and is simpler, more efficient, flexible and reliable. Because the speed bottleneck is in network communication under the multi-machine system, even if three threads are fully opened, the processing speed of each thread is also greater than the network communication speed, and the system speed loss can not be brought. Due to the multiplexing of the processing core and the interface, the resource overhead of the FPGA is small.
As shown in fig. 3, a plurality of devices (master and slave devices) may be configured into one Group (Group). The group leader (the host in the group) can send instructions to the devices in the group in a group without sending the instructions respectively, so that the synchronization of the operation in the group is realized. Compared with a Trig signal synchronization mode, the script programming is simple and the efficiency is higher. In the optical fiber loop, when the host and the slave equipment are configured into a plurality of groups, the occupation right of the optical fiber instruction bit is switched by a plurality of group length turns, and the groups are synchronized through the independent synchronization bit, so that the synchronization of the plurality of groups and the plurality of scripts is realized. The external device can be controlled by the host, and the local UI/PI independent operation or composite control can be selected according to the application occasion of the user.
The specific embodiment is that the source-meter multi-machine equipment is networked, the host machine is connected with the slave machine through an optical fiber module, and a networking signal flow chart is as follows:
specifically, as shown in fig. 4, the host signal flow:
an ARM layer: and (5) completing the flow by the main CPU.
Downloading the complete batch processing program to a multi-thread script processor program code area, and starting operation; the upper computer issues a high-level language instruction, a program block instruction and/or a flow instruction are issued by converting UI/PI/feedback operation into machine code, and during the execution of the multi-thread script processor, a normal thread and a system program thread are utilized to load parameters for each slave computer, read back the parameters, or temporarily insert the operation task of the host computer.
Bottom layer mixing system: and the working system consists of various functional modules built by FPGA, a multi-thread script processor (soft core) and the like.
Each function module built by the FPGA comprises an RAM, an FIFO, an RAM, a MUX and other function modules, and the like, and the multithreading script processor is used as a processing center to execute multithreading tasks and control each function module in the network. Specifically, the instruction fetching controller of the multithread script processor identifies the setting state and the current execution state of the normal thread, the system program thread and the batch processing thread and carries out rotation switching. The multithreading script processor directly addresses each module of the slave equipment on the optical fiber network and loads parameters and programs for each equipment through normal threads; through the batch processing thread, each device can run a complete script edited in advance at the same time to execute a complete test flow; the dynamic loading instruction block is circularly executed by the system program thread executing the local system task or supplementing the Normal instruction, and the dynamic loading instruction block program is loaded by the ARM, can be started and executed by the Normal thread, and can also be directly started by the ARM. The specific instruction execution process of the multi-thread script processor is as follows: the instruction fetching port fetches the source operand through the data bus of the multi-thread script processor, generates the target operand after being processed by the multi-thread script processor, and the multi-thread script processor sends the target operand to the target address.
The functional modules are interconnected through the multi-thread script processor, for example, the MOV instruction can be used for sending the parameter of one module to another module, specifically, the multi-thread script processor sends a read instruction to the data bus of the multi-thread script processor, the data of the appointed module address is obtained through the data bus of the multi-thread script processor, and then the data is written into the appointed module address of the data bus of the multi-thread script processor, so that the MOV carrying function is completed.
As shown in fig. 5, the slave signal flow:
an ARM layer: downloading the complete batch processing program to a multi-thread script processor program code area, and starting operation; and issuing a program block instruction and/or a flow instruction through the UI/PI machine-to-machine code, and transmitting the exception and the state of the slave machine back to the host machine during the execution of the multi-thread script processor.
Bottom layer mixing system: and the working system consists of various functional modules built by FPGA, a multi-thread script processor (soft core) and the like. Each function module built by the FPGA comprises an RAM, an FIFO, an RAM, a MUX and other function modules.
The instruction fetching instruction of the multi-thread script processor comprises a true instruction and a false instruction:
the real instruction is executed and completed by the multi-thread script processor, and the operation flow is as follows: analyzing the operation code, acquiring a source operand through a data bus of the multi-thread script processor according to a data addressing mode, and writing the source operand into a destination operation address through the data bus according to a destination operand addressing mode when the instruction is a Mov instruction; when the instruction is a goto type instruction, after a source operand is obtained, comparing operation is carried out on the source operation according to a goto jump condition, a PC pointer executed in the next step is generated according to an operation result, and jumping is carried out; when the instruction is operation, the corresponding operation is carried out to the source operand, and the operation result is written into the corresponding address according to the addressing mode of the target operand.
The pseudo-instructions are triggered to execute by the multithreaded script processor ARM. The pseudo-instruction includes two types, one is a blocking pseudo-instruction and the other is a non-blocking pseudo-instruction. When the blocking pseudo-instruction is executed, the multi-thread script processor stops running and generates an interrupt signal to the ARM at the same time, and when the ARM processes an interrupt program, the current pseudo-instruction of the multi-thread script processor is obtained, and corresponding operation is completed. And then resumes operation of the multithreaded processor. And when the ARM processes an interrupt program, the cached pseudo instructions are read from the FIFO to complete corresponding instruction operation.
When a plurality of devices execute a test script, i.e., are configured as a Group (Group), it is a Group mode. In this mode, the slave computer mainly executes the host script instruction from the optical fiber without running its own script instruction. When the host runs the main script, the host can send a writing instruction to the Group (Group) of the devices through the data bus, and when the Group members receive the instruction, the Group members can execute the instruction at the same time. Parameters needing to be operated do not need to be sent to each device one by one, and then a public trig signal is generated to inform each module to start executing the parameters loaded in advance. Such an operation may replace trig write synchronization.
When multiple devices operate independently, i.e., are configured into multiple groups, there is a multiple-group mode. In the mode, the host can inquire the state parameters of the slave through the optical fiber or temporarily intervene in the operation and the operation of the slave according to the requirement, and the occupation right of the optical fiber instruction bit is switched by the host in a plurality of groups in a rotating way. The groups are synchronized through independent synchronization bits, and multi-group multi-script synchronization is achieved. The independent synchronization bit may be configured as a Trig signal for transmission of multiple sets of real-time Trig signals, or a set may include only one device. Each group uses one device as a master, a plurality of devices are slaves, and the slaves can only contain one device. The external device can be controlled by the host, and the local UI/PI independent operation or composite control can be selected according to the application occasion of the user.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (8)
1. A multi-machine device networking architecture, characterized by: the multi-machine test system comprises a host machine and a plurality of slave machine devices, wherein the host machine and the slave machine devices form an annular network, each slave machine device is mounted on a data bus of a multi-thread script processor of the host machine, the host machine utilizes the multi-thread script processor to control each slave machine device to complete a multi-machine test flow, the multi-thread script processor comprises a script processing core, an instruction fetching controller and a plurality of instruction fetching ports, each instruction fetching port corresponds to one thread, the instruction fetching controller identifies a thread setting state and a current execution state to carry out cycle switching, the script processing core has a network routing function, and machine codes can directly address each module of the slave machine devices on the network.
2. The multi-machine networking architecture of claim 1, wherein: the threads include a Normal thread, a system chunk thread, and a batch thread,
the Normal thread fetch is from FIFO and is used for loading parameters and programs for each slave device;
the system program block thread is used for supplementing a Normal thread or executing a local system task;
and the batch processing thread runs a complete script which is edited in advance, a complete test flow is executed, and the host machine utilizes the batch processing thread to directly control each module of the slave machine equipment to cooperatively complete a complex test task.
3. The multi-machine networking architecture of claim 2, wherein: the system program block thread is used as supplement of the Normal thread, the circularly executed instruction block is sent to a specified address of the system program block, the Normal thread starts execution or the ARM is directly started, when the Normal thread finishes the execution, the system program block thread started by the Normal thread automatically executes an exit instruction, before exiting, the system program block thread calls an interrupt instruction to inform the ARM, the system program block thread directly started by the ARM automatically executes the exit instruction, and before exiting, the system program block thread calls the interrupt instruction to inform the ARM.
4. The multi-machine networking architecture of claim 3, wherein: the multithreaded script processor instruction fetch includes true instructions and pseudo instructions,
the real instruction is executed and completed by the multi-thread script processor, the source operand is obtained through a data bus of the multi-thread script processor according to a data addressing mode, the target operand is generated by the multi-thread script processor, and then the target operand is sent to a target address;
the pseudo-instructions are triggered to execute by the multithreaded script processor ARM.
5. The multi-machine networking architecture of claim 4, wherein: the pseudo instructions comprise blocking pseudo instructions and non-blocking pseudo instructions, when the blocking pseudo instructions are executed, the multi-thread script processor stops running, an interrupt signal is generated to the ARM, when the ARM processes an interrupt program, the ARM acquires the current pseudo instructions of the multi-thread script processor, corresponding instruction operation is completed, and then the running of the multi-thread script processor is recovered; when the non-blocking pseudo-instruction is executed, the multi-thread script processor writes the non-blocking pseudo-instruction into the pseudo-instruction FIFO and generates an interrupt at the same time, and when the ARM processes the interrupt program, the cached pseudo-instruction is read from the FIFO to complete the corresponding instruction operation.
6. The multi-machine networking architecture of claim 1, wherein: the host and the slave devices can be configured into one group or a plurality of groups, and when the host and the slave devices are configured into one group, the host sends instructions to the slave devices in the group in a group manner to realize the synchronization of the operation in the group; when the synchronous data is configured into a plurality of groups, the occupation right of the instruction bit is switched by the host rotation in the plurality of groups, and the groups are synchronized through the independent synchronization bit, so that the synchronization of the plurality of groups and the plurality of scripts is realized.
7. The multi-machine networking architecture of claim 1, wherein: each slave device is mounted on a data bus of a multi-thread script processor of the host through an optical fiber, and the host controls each slave device to complete a multi-machine user test process through optical fiber communication by using the multi-thread script processor.
8. The multi-machine networking architecture of claim 7, wherein: the optical fiber communication bits of the optical fiber communication comprise optical fiber instruction bits, independent synchronization bits and CAN bus bits mapped by a digital bus of the multi-thread script processor.
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