CN108279927B - Multi-channel instruction control method and system capable of adjusting instruction priority and controller - Google Patents
Multi-channel instruction control method and system capable of adjusting instruction priority and controller Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/327—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for interrupts
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
Abstract
The invention provides a multi-channel instruction control method, a system and a controller capable of adjusting instruction priority, which comprises the steps of configuring a group of state controllers for each thread; arbitrating different data reading requests by an instruction fetch request arbitrator; storing the instruction data to a storage space corresponding to the on-chip memory through an instruction storage arbiter; reading the instructions in the on-chip memory according to the polling sequence through an instruction reading controller; transmitting the instruction data of the equipment configuration instruction and the equipment mark to an instruction transmitter through an instruction decoder; sending the instruction data to corresponding equipment through an instruction sender; and receiving a feedback signal of the equipment through the signal controller, and switching a plurality of different threads to control the execution sequence of the equipment. The multi-channel instruction control method, the multi-channel instruction control system and the multi-channel instruction control controller capable of adjusting the instruction priority solve the problems of priority preemption, instruction transmission efficiency and multi-thread operation synchronization.
Description
Technical Field
The present invention relates to the field of instruction control technologies, and in particular, to a multi-channel instruction control method, a multi-channel instruction control system, and a multi-channel instruction control controller capable of adjusting instruction priorities.
Background
With the rapid development of the internet of things and the artificial intelligence technology, the demand for high-performance and low-power-consumption chips is increasing. In the prior art, the multi-core and multi-thread parallel processing technology is widely applied to various processors. In the multi-thread scenario, the synchronous operation between the instruction fetch module inside the chip and each processing unit has become one of the bottlenecks in the performance of the chip.
Currently, the common ways of reading instructions can be roughly divided into two types:
(1) direct instruction fetch and configuration of internal registers by a CPU
This approach has the advantage of being simple to implement. Many of the current embedded application chips use bus direct addressing to read instructions. Due to the large number of applications of the AMBA (advanced Microcontroller Bus architecture) Bus in low-power embedded chips, direct addressing of the AMBA Bus is a frequently used addressing mode in chips. This is done by connecting the CPU to the instruction memory, and to the devices receiving the instructions, using the AMBA bus to increase the rate and efficiency of the transfer of single instructions. However, since the information exchange between the device and the instruction memory must be transferred by the CPU, the work efficiency of the CPU is reduced, and the work performance of the CPU is significantly reduced when a large number of instructions are read. This is a major drawback of the CPU-oriented dual bus architecture. Meanwhile, in order to manage the instructions conveniently, a space specially divided for the instructions is needed so as to facilitate the operation of software, and the pre-occupied mode increases the expenditure of a memory. If the size of the established space is too large or too small, the problem of memory is easily caused. Generally, all instructions in the chip are directly addressed and transferred by using the bus, and in the case of a large number of instructions, instruction reading becomes a performance bottleneck of the whole chip. Thus, for large numbers of instruction reads and writes, it is clearly less appropriate to use direct addressing.
(2) Indirect collocation method
Currently, many high performance System on Chip (SoC) chips employ a dedicated instruction fetch module. Usually, a technology of a first-level linked list is adopted, a CPU configures an instruction reading module, the address and the number of instructions are sent to an instruction fetching module, the instruction fetching module sends a request to a memory controller, the memory controller directly accesses data from a memory and transmits the data to the instruction fetching module when a bus is idle, and information is fed back to the CPU after the data transmission is finished, so that the occupation rate of CPU resources is reduced to a great extent, and system resources can be greatly saved. However, this approach has disadvantages: if a complete operation requires multiple sections of instructions, and the instructions are scattered at different positions, the CPU needs to perform multiple operations similar to direct addressing, thereby reducing the work efficiency of the CPU.
In addition to performance issues, the conventional single port approach also has priority preemption issues. Due to the time-sharing nature of bus transmission, arbitration of the bus is necessary when there are multiple masters simultaneously applying for use of the bus. When a low priority device reads an instruction earlier than a high priority device, the bus will be occupied by the low priority device, and the high priority device must wait until the low priority device reads the instruction to obtain the bus resource. The hardware device without the resource regulation mechanism is easy to cause information delay, and forms a performance bottleneck at an application with strong immediate demand. For the artificial intelligence chip, a plurality of neural network units and a graphic processor are arranged in the artificial intelligence chip. If a conventional implementation is used to send instructions to multiple hardware processing modules, when one of the processing modules is blocked, the remaining processing modules cannot receive new instructions. A common solution is to introduce interrupt modules, and interrupts with a high preemptive priority can be responded to during interrupt processing with a low preemptive priority, i.e. interrupt nesting, or interrupts with a high preemptive priority can nest interrupts with a low preemptive priority. However, in this way, each hardware processing module is collocated with one instruction reading module, which occupies a lot of interface resources, occupies a large area, and the synchronous communication between the hardware processing modules becomes complicated and is difficult to control. Frequent handling of interrupts also increases the overhead of the CPU, resulting in an excessive CPU load.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a multi-channel instruction control method, a multi-channel instruction control system, and a multi-channel instruction controller, which can adjust the instruction priority, improve the working performance of the whole chip, solve the problem of priority preemption, have simple control, and save a large amount of interface resources and chip area.
To achieve the above and other related objects, the present invention provides a multi-channel instruction control method capable of adjusting instruction priority, including the steps of: setting a state register, an instruction fetching request arbiter, an instruction storage arbiter, an instruction reading controller, an instruction decoder, a signal controller and an instruction transmitter; configuring a group of state controllers for each thread, wherein the state controllers are used for storing the initial address, the end address and the number of the instruction blocks of a memory space where the addresses of the instruction blocks are located, and configuring reading instruction starting signals; sending a descriptor pointer reading request to a bus according to the information of the state register, sending a control command reading request to the bus according to the starting address and the ending address of an instruction segment returned by the bus, and arbitrating different data reading requests through an instruction fetching request arbitrator; according to the current instruction label, storing the instruction data transmitted by the bus into a storage space corresponding to the on-chip memory through an instruction storage arbiter; arbitrating instruction reading requests of different threads by an instruction reading controller in a polling mode, reading instructions in an on-chip memory according to a polling sequence, and transmitting the instructions to a corresponding instruction decoder by a decoding selector; then, sending the instruction data of the equipment configuration instruction and the equipment mark to an instruction sender through an instruction decoder, sending a signal mark corresponding to the synchronous communication instruction between the equipment to a signal controller, and sending an interrupt signal corresponding to the interrupt instruction to a system; sending the instruction data to corresponding equipment through an instruction sender; receiving a feedback signal of the equipment to the received instruction data through a signal controller; and switching a plurality of different threads through the signal controller according to the received feedback signal and the synchronous communication instruction so as to control the execution sequence of the equipment.
In an embodiment of the present invention, the arbitration principle of the fetch request arbiter is:
the address request is prior to the data request in the single thread, and the high priority is prior to the low priority;
data requests between different threads are realized in a polling mode, and the thread with the pause is directly skipped.
In an embodiment of the present invention, the FIFO controller corresponding to the channel selected by the instruction storage arbiter performs read/write operations on the storage space corresponding to the instruction at the same time.
Correspondingly, the invention provides a multi-channel instruction control system capable of adjusting instruction priority, which comprises a setting module, a configuration module, an arbitration module, an instruction processing module, a receiving module and a switching module, wherein the setting module is used for setting the priority of instructions;
the setting module is used for setting a state register, an instruction fetching request arbiter, an instruction storage arbiter, an instruction reading controller, an instruction decoder, a signal controller and an instruction transmitter;
the configuration module is used for configuring a group of state controllers for each thread, and the state controllers are used for storing the starting address, the ending address and the number of the instruction blocks of the memory space where the addresses of the instruction blocks are located and configuring reading instruction starting signals;
the arbitration module is used for sending a descriptor pointer reading request to the bus according to the information of the state register, sending a control command reading request to the bus according to the starting address and the ending address of the instruction segment returned by the bus, and arbitrating different data reading requests through the instruction fetching request arbiter;
the instruction processing module is used for storing the instruction data transmitted by the bus to a storage space corresponding to the on-chip memory through the instruction storage arbiter according to the current instruction label; arbitrating instruction reading requests of different threads by an instruction reading controller in a polling mode, reading instructions in an on-chip memory according to a polling sequence, and transmitting the instructions to a corresponding instruction decoder by a decoding selector; then, sending the instruction data of the equipment configuration instruction and the equipment mark to an instruction sender through an instruction decoder, sending a signal mark corresponding to the synchronous communication instruction between the equipment to a signal controller, and sending an interrupt signal corresponding to the interrupt instruction to a system; sending the instruction data to corresponding equipment through an instruction sender;
the receiving module is used for receiving a feedback signal of the equipment for the received instruction data through the signal controller;
the switching module is used for switching a plurality of different threads through the signal controller according to the received feedback signal and the synchronous communication instruction so as to control the execution sequence of the equipment.
In an embodiment of the present invention, the arbitration principle of the fetch request arbiter is:
the address request is prior to the data request in the single thread, and the high priority is prior to the low priority;
data requests between different threads are realized in a polling mode, and the thread with the pause is directly skipped.
In an embodiment of the present invention, the FIFO controller corresponding to the channel selected by the instruction storage arbiter performs read/write operations on the storage space corresponding to the instruction at the same time.
The invention provides a multi-channel instruction controller capable of adjusting instruction priority, which comprises a processor and a memory, wherein the processor is used for processing a plurality of instructions;
the memory is used for storing a computer program;
the processor is used for executing the computer program stored in the memory so as to enable the multi-channel instruction controller capable of adjusting the instruction priority to execute the multi-channel instruction control method capable of adjusting the instruction priority.
Finally, the invention provides a multi-channel instruction control system capable of adjusting instruction priority, which comprises the multi-channel instruction controller capable of adjusting instruction priority, a state register, an instruction fetch request arbiter, an instruction storage arbiter, an instruction read controller, an instruction decoder, a signal controller and an instruction transmitter;
the state register is used for storing the starting address, the ending address and the number of the instruction blocks of the memory space where the address of the instruction block is located, and configuring a read instruction starting signal;
the fetch request arbiter is used for arbitrating different data read requests;
the instruction storage arbiter is used for storing the instruction data transmitted by the bus to a storage space corresponding to the on-chip memory;
the instruction reading controller is used for arbitrating instruction reading requests of different threads in a polling mode and reading instructions in the on-chip memory according to a polling sequence;
the instruction decoder is used for sending instruction data and an equipment mark of equipment equipped instructions to the instruction sender, sending a signal mark corresponding to a synchronous communication instruction between the equipment to the signal controller, and sending an interrupt signal corresponding to an interrupt instruction to the system;
the signal controller is used for receiving a feedback signal of the equipment for the received instruction data and switching a plurality of different threads to control the execution sequence of the equipment;
the instruction transmitter is used for transmitting the instruction data of the equipment to the corresponding equipment.
As described above, the multi-channel instruction control method, system and controller capable of adjusting instruction priority according to the present invention have the following advantages:
(1) the working performance of the whole chip is improved, the problem of priority preemption is solved, the synchronization among a plurality of graphic processing modules is realized by utilizing a single-interface mode, the control is simple, and a large amount of interface resources and chip area are saved;
(2) under the condition of fine-grained multithreading, when one thread is stopped, instructions in other threads can be read, so that the loss of throughput caused by long and short stops can be hidden;
(3) in the fine-grained case, the interleaving of threads can eliminate the empty slots;
(4) because the emitting stroke is changed in each clock period, the operation with longer delay can be hidden, and the performance of the chip is greatly improved;
(5) the method supports two-stage linked list indirect addressing, only needs a small fixed space to store a small number of linked list addresses of the first stage, and the addresses stored by the instructions are not limited, so that the problems of memory space division and management are solved, hardware resources are saved, software personnel can develop conveniently, and the flexibility is high.
Drawings
FIG. 1 is a flow chart illustrating a multi-channel instruction control method for adjusting instruction priority according to an embodiment of the present invention;
FIG. 2 is a system architecture diagram illustrating an embodiment of a multi-channel instruction control method for adjusting instruction priorities according to the present invention;
FIG. 3 is a diagram illustrating an exemplary secondary linked list of instructions according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a fine-grained multithread request of the present invention in one embodiment;
FIG. 5 is a diagram illustrating an embodiment of a command read/write control architecture according to the present invention;
FIG. 6 is a block diagram of a multi-channel instruction control system with adjustable instruction priorities according to an embodiment of the present invention;
FIG. 7 is a block diagram of a multi-channel instruction controller with adjustable instruction priorities according to an embodiment of the present invention.
Description of the element reference numerals
61 setting module
62 configuration module
63 arbitration module
64 instruction processing module
65 receiving module
66 switching module
71 processor
72 memory
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The multi-channel instruction control method and system capable of adjusting the instruction priority and the controller improve the working performance of the whole chip, solve the problem of priority preemption, are simple to control, and save a large amount of interface resources and chip area.
As shown in FIG. 1, in one embodiment, the multi-channel instruction control method for adjusting instruction priority of the present invention comprises the following steps:
step S1, setting a status register, an instruction fetch request arbiter, an instruction storage arbiter, an instruction fetch controller, an instruction decoder, a signal controller, and an instruction transmitter.
As shown in fig. 2, a hardware architecture for a multi-channel instruction controller that can adjust instruction priority is created. Specifically, an architecture for reading instructions is provided within the overall framework of the SOC, including a status register, an instruction fetch request arbiter, an instruction storage arbiter, an instruction read controller, an instruction decoder, a signal controller, and an instruction transmitter.
Step S2, configuring a set of state controllers for each thread, where the state controllers are used to store the start address, the end address, and the number of instruction blocks of the memory space where the address of the instruction block is located, and configure a read instruction start signal.
In particular, each thread is controlled by a set of status registers. The state register is configured by a CPU bus, configures the starting address, the ending address and the number of the instruction blocks of the memory space where the address of the storage instruction block is located, and configures a read instruction starting signal. As shown in fig. 3, a block of memory space is partitioned in the system memory, the stored data is the real address of each instruction block, and the real address of the instruction is obtained by accessing the memory space. The full state of the memory space is determined by the read pointer and the write pointer. After the CPU configures the state register, the instruction controller can work independently without the CPU participating in the configuration, thereby reducing the work load of the CPU.
Step S3, sending a descriptor pointer read request to the bus according to the information of the status register, sending a control command read request to the bus according to the start address and the end address of the command segment returned by the bus, and arbitrating different data read requests by the instruction fetch request arbiter.
Specifically, according to the information of the status register, a descriptor pointer read request is sent to the bus, and descriptor pointer data transmitted back by the bus are the starting address and the ending address of the instruction segment. And sending a control command read request bus according to the starting address and the ending address of the instruction segment. Wherein, two different data reading requests are arbitrated by the request arbitrator. As shown in fig. 4, a single thread includes two different levels of data requests, a high priority and a low priority, and the default is that the high priority preempts the low priority. For an instruction fetch request arbiter, address requests are prioritized over data requests in a single thread, with high priority over low priority. The data requests among different threads are realized by a polling mode, namely the requests are alternately requested among 1-N threads, and the stopped threads are directly skipped. The instruction fetch request arbiter records the corresponding request source for each data request; when the request data is returned, whether the request data is an instruction address or instruction data and which thread belongs to is determined according to the record label.
Step S4, storing the instruction data transmitted by the bus to the storage space corresponding to the on-chip memory through the instruction storage arbiter according to the current instruction label; arbitrating instruction reading requests of different threads by an instruction reading controller in a polling mode, reading instructions in an on-chip memory according to a polling sequence, and transmitting the instructions to a corresponding instruction decoder by a decoding selector; then, sending the instruction data of the equipment configuration instruction and the equipment mark to an instruction sender through an instruction decoder, sending a signal mark corresponding to the synchronous communication instruction between the equipment to a signal controller, and sending an interrupt signal corresponding to the interrupt instruction to a system; and transmitting the instruction data to the corresponding equipment through the instruction transmitter.
As shown in fig. 5, according to the current instruction label, the instruction data transmitted by the bus is stored in the storage space corresponding to the on-chip memory by the instruction storage arbiter. And at the same time, the FIFO controller corresponding to the channel selected by the instruction storage arbiter performs read-write operation on the storage space corresponding to the instruction.
The instruction reader arbitrates instruction reading requests of different threads in a polling mode, reads instructions in the on-chip memory according to a polling sequence, and transmits the instructions to a corresponding instruction decoder through the decoding selector so as to perform decoding operation on the instructions.
Specifically, depending on the different types of instructions being fetched, the instruction decoder performs different operations:
(1) and if the command is a command for synchronous communication between different devices, the command decoder sends a corresponding signal mark to the signal controller after decoding.
(2) If the instruction is a configuration instruction of the equipment, the instruction decoder sends the instruction data and the equipment mark to the instruction sender together, so that the instruction sender sends the instruction data to the corresponding equipment.
(3) The instruction is an interrupt instruction, and the instruction decoder sends a corresponding interrupt signal to the system.
Step S5, receiving a feedback signal of the device to the received instruction data through the signal controller.
Specifically, the device receives corresponding instruction data according to its own device identifier, and after performing a related operation, sends a feedback signal to the signal controller.
And step S6, switching a plurality of different threads through the signal controller according to the received feedback signal and the synchronous communication instruction so as to control the execution sequence of the equipment.
Specifically, the signal controller arbitrates according to the received feedback signal and the synchronous communication instruction, switches a plurality of different threads, and thereby controls the execution sequence of the device.
Thus, complete multi-channel instruction control is completed. Then, the bus inquires the reading status of the current instruction by accessing the status register, and sends the new instruction block storage address to the status register. The above steps S1-S6 are repeated until all the commands are transmitted.
As shown in fig. 6, in one embodiment, the multi-channel command control system capable of adjusting command priority of the present invention includes a setting module 61, a configuration module 62, an arbitration module 63, a command processing module 64, a receiving module 65, and a switching module 66.
The setting module 61 is used for setting a status register, an instruction fetch request arbiter, an instruction storage arbiter, an instruction fetch controller, an instruction decoder, a signal controller and an instruction transmitter.
As shown in fig. 2, a hardware architecture for a multi-channel instruction controller that can adjust instruction priority is created. Specifically, an architecture for reading instructions is provided within the overall framework of the SOC, including a status register, an instruction fetch request arbiter, an instruction storage arbiter, an instruction read controller, an instruction decoder, a signal controller, and an instruction transmitter.
The configuration module 62 is connected to the setting module 61, and is configured to configure a group of state controllers for each thread, where the state controllers are configured to store a start address, an end address, and the number of instruction blocks of a memory space where addresses of the instruction blocks are located, and configure a read instruction start signal.
In particular, each thread is controlled by a set of status registers. The state register is configured by a CPU bus, configures the starting address, the ending address and the number of the instruction blocks of the memory space where the address of the storage instruction block is located, and configures a read instruction starting signal. As shown in fig. 3, a block of memory space is partitioned in the system memory, the stored data is the real address of each instruction block, and the real address of the instruction is obtained by accessing the memory space. The full state of the memory space is determined by the read pointer and the write pointer. After the CPU configures the state register, the instruction controller can work independently without the CPU participating in the configuration, thereby reducing the work load of the CPU.
The arbitration module 63 is connected to the configuration module 62, and configured to send a descriptor pointer read request to the bus according to the information of the status register, send a control command read request to the bus according to the start address and the end address of the instruction segment returned by the bus, and arbitrate different data read requests by the instruction fetch request arbiter.
Specifically, according to the information of the status register, a descriptor pointer read request is sent to the bus, and descriptor pointer data transmitted back by the bus are the starting address and the ending address of the instruction segment. And sending a control command read request bus according to the starting address and the ending address of the instruction segment. Wherein, two different data reading requests are arbitrated by the request arbitrator. As shown in fig. 4, a single thread includes two different levels of data requests, a high priority and a low priority, and the default is that the high priority preempts the low priority. For an instruction fetch request arbiter, address requests are prioritized over data requests in a single thread, with high priority over low priority. The data requests among different threads are realized by a polling mode, namely the requests are alternately requested among 1-N threads, and the stopped threads are directly skipped. The instruction fetch request arbiter records the corresponding request source for each data request; when the request data is returned, whether the request data is an instruction address or instruction data and which thread belongs to is determined according to the record label.
The instruction processing module 64 is connected with the arbitration module 63 and is used for storing the instruction data transmitted by the bus to a storage space corresponding to the on-chip memory through the instruction storage arbiter according to the current instruction label; arbitrating instruction reading requests of different threads by an instruction reading controller in a polling mode, reading instructions in an on-chip memory according to a polling sequence, and transmitting the instructions to a corresponding instruction decoder by a decoding selector; then, sending the instruction data of the equipment configuration instruction and the equipment mark to an instruction sender through an instruction decoder, sending a signal mark corresponding to the synchronous communication instruction between the equipment to a signal controller, and sending an interrupt signal corresponding to the interrupt instruction to a system; and transmitting the instruction data to the corresponding equipment through the instruction transmitter.
As shown in fig. 5, according to the current instruction label, the instruction data transmitted by the bus is stored in the storage space corresponding to the on-chip memory by the instruction storage arbiter. And at the same time, the FIFO controller corresponding to the channel selected by the instruction storage arbiter performs read-write operation on the storage space corresponding to the instruction.
The instruction reader arbitrates instruction reading requests of different threads in a polling mode, reads instructions in the on-chip memory according to a polling sequence, and transmits the instructions to a corresponding instruction decoder through the decoding selector so as to perform decoding operation on the instructions.
Specifically, depending on the different types of instructions being fetched, the instruction decoder performs different operations:
(1) and if the command is a command for synchronous communication between different devices, the command decoder sends a corresponding signal mark to the signal controller after decoding.
(2) If the instruction is a configuration instruction of the equipment, the instruction decoder sends the instruction data and the equipment mark to the instruction sender together, so that the instruction sender sends the instruction data to the corresponding equipment.
(3) The instruction is an interrupt instruction, and the instruction decoder sends a corresponding interrupt signal to the system.
The receiving module 65 is connected to the instruction processing module 64, and is used for receiving a feedback signal of the device for the received instruction data through the signal controller.
Specifically, the device receives corresponding instruction data according to its own device identifier, and after performing a related operation, sends a feedback signal to the signal controller.
The switching module 66 is connected to the receiving module 65, and is configured to switch, through the signal controller, the plurality of different threads according to the received feedback signal and the synchronous communication instruction, so as to control the execution sequence of the device.
Specifically, the signal controller arbitrates according to the received feedback signal and the synchronous communication instruction, switches a plurality of different threads, and thereby controls the execution sequence of the device.
Thus, complete multi-channel instruction control is completed. Then, the bus inquires the reading status of the current instruction by accessing the status register, and sends the new instruction block storage address to the status register. The above steps S1-S6 are repeated until all the commands are transmitted.
It should be noted that the division of the modules of the above system is only a logical division, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated. And these modules can be realized in the form of software called by processing element; or may be implemented entirely in hardware; and part of the modules can be realized in the form of calling software by the processing element, and part of the modules can be realized in the form of hardware. For example, the x module may be a processing element that is set up separately, or may be implemented by being integrated in a chip of the apparatus, or may be stored in a memory of the apparatus in the form of program code, and the function of the x module may be called and executed by a processing element of the apparatus. Other modules are implemented similarly. In addition, all or part of the modules can be integrated together or can be independently realized. The processing element described herein may be an integrated circuit having signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software.
For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), etc. For another example, when one of the above modules is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
As shown in FIG. 7, in one embodiment, the multi-channel instruction controller with adjustable instruction priorities of the present invention includes a processor 71 and a memory 72.
The memory 72 is used for storing computer programs.
Preferably, the memory 72 includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The processor 71 is connected to the memory 72, and is configured to execute the computer program stored in the memory 72, so that the multi-channel instruction controller with adjustable instruction priority executes the multi-channel instruction control method with adjustable instruction priority.
Preferably, the processor 71 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; the integrated circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components.
In one embodiment, the multi-channel command control system capable of adjusting command priorities of the present invention comprises the above multi-channel command controller capable of adjusting command priorities, a status register, a fetch request arbiter, a command storage arbiter, a command fetch controller, a command decoder, a signal controller and a command transmitter;
the state register is used for storing the starting address, the ending address and the number of the instruction blocks of the memory space where the address of the instruction block is located, and configuring a read instruction starting signal;
the fetch request arbiter is used for arbitrating different data read requests;
the instruction storage arbiter is used for storing the instruction data transmitted by the bus to a storage space corresponding to the on-chip memory;
the instruction reading controller is used for arbitrating instruction reading requests of different threads in a polling mode and reading instructions in the on-chip memory according to a polling sequence;
the instruction decoder is used for sending instruction data and an equipment mark of equipment equipped instructions to the instruction sender, sending a signal mark corresponding to a synchronous communication instruction between the equipment to the signal controller, and sending an interrupt signal corresponding to an interrupt instruction to the system;
the signal controller is used for receiving a feedback signal of the equipment for the received instruction data and switching a plurality of different threads to control the execution sequence of the equipment;
the instruction transmitter is used for transmitting the instruction data of the equipment to the corresponding equipment.
In summary, the multi-channel instruction control method and system and the controller capable of adjusting the instruction priority of the invention improve the working performance of the whole chip, solve the problem of priority preemption, realize the synchronization among a plurality of graphic processing modules by using a single interface mode, have simple control and save a large amount of interface resources and chip area; under the condition of fine-grained multithreading, when one thread is stopped, instructions in other threads can be read, so that the loss of throughput caused by long and short stops can be hidden; in the fine-grained case, the interleaving of threads can eliminate the empty slots; because the emitting stroke is changed in each clock period, the operation with longer delay can be hidden, and the performance of the chip is greatly improved; the method supports two-stage linked list indirect addressing, only needs a small fixed space to store a small number of linked list addresses of the first stage, and the addresses stored by the instructions are not limited, so that the problems of memory space division and management are solved, hardware resources are saved, software personnel can develop conveniently, and the flexibility is high. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. A multi-channel instruction control method capable of adjusting instruction priority is characterized by comprising the following steps:
setting a state register, an instruction fetching request arbiter, an instruction storage arbiter, an instruction reading controller, an instruction decoder, a signal controller and an instruction transmitter;
configuring a group of state controllers for each thread, wherein the state controllers are used for storing the initial address, the end address and the number of the instruction blocks of a memory space where the addresses of the instruction blocks are located, and configuring reading instruction starting signals;
sending a descriptor pointer reading request to a bus according to the information of the state register, sending a control command reading request to the bus according to the starting address and the ending address of an instruction segment returned by the bus, and arbitrating different data reading requests through an instruction fetching request arbitrator;
according to the current instruction label, storing the instruction data transmitted by the bus into a storage space corresponding to the on-chip memory through an instruction storage arbiter; arbitrating instruction reading requests of different threads by an instruction reading controller in a polling mode, reading instructions in an on-chip memory according to a polling sequence, and transmitting the instructions to a corresponding instruction decoder by a decoding selector; then, sending the instruction data of the equipment configuration instruction and the equipment mark to an instruction sender through an instruction decoder, sending a signal mark corresponding to the synchronous communication instruction between the equipment to a signal controller, and sending an interrupt signal corresponding to the interrupt instruction to a system; sending the instruction data to corresponding equipment through an instruction sender;
receiving a feedback signal of the equipment to the received instruction data through a signal controller;
and switching a plurality of different threads through the signal controller according to the received feedback signal and the synchronous communication instruction so as to control the execution sequence of the equipment.
2. The method as claimed in claim 1, wherein the arbitration rule of the fetch request arbiter is:
the address request is prior to the data request in the single thread, and the high priority is prior to the low priority;
data requests between different threads are realized in a polling mode, and the thread with the pause is directly skipped.
3. The method as claimed in claim 1, wherein the FIFO controller corresponding to the channel selected by the instruction storage arbiter performs read/write operations on the storage space corresponding to the instruction at the same time.
4. A multi-channel instruction control system capable of adjusting instruction priority is characterized by comprising a setting module, a configuration module, an arbitration module, an instruction processing module, a receiving module and a switching module;
the setting module is used for setting a state register, an instruction fetching request arbiter, an instruction storage arbiter, an instruction reading controller, an instruction decoder, a signal controller and an instruction transmitter;
the configuration module is used for configuring a group of state controllers for each thread, and the state controllers are used for storing the starting address, the ending address and the number of the instruction blocks of the memory space where the addresses of the instruction blocks are located and configuring reading instruction starting signals;
the arbitration module is used for sending a descriptor pointer reading request to the bus according to the information of the state register, sending a control command reading request to the bus according to the starting address and the ending address of the instruction segment returned by the bus, and arbitrating different data reading requests through the instruction fetching request arbiter;
the instruction processing module is used for storing the instruction data transmitted by the bus to a storage space corresponding to the on-chip memory through the instruction storage arbiter according to the current instruction label; arbitrating instruction reading requests of different threads by an instruction reading controller in a polling mode, reading instructions in an on-chip memory according to a polling sequence, and transmitting the instructions to a corresponding instruction decoder by a decoding selector; then, sending the instruction data of the equipment configuration instruction and the equipment mark to an instruction sender through an instruction decoder, sending a signal mark corresponding to the synchronous communication instruction between the equipment to a signal controller, and sending an interrupt signal corresponding to the interrupt instruction to a system; sending the instruction data to corresponding equipment through an instruction sender;
the receiving module is used for receiving a feedback signal of the equipment for the received instruction data through the signal controller;
the switching module is used for switching a plurality of different threads through the signal controller according to the received feedback signal and the synchronous communication instruction so as to control the execution sequence of the equipment.
5. The multi-channel instruction control system capable of adjusting instruction priorities as claimed in claim 4, wherein the arbitration principle of the instruction fetch request arbiter is:
the address request is prior to the data request in the single thread, and the high priority is prior to the low priority;
data requests between different threads are realized in a polling mode, and the thread with the pause is directly skipped.
6. The multi-channel instruction control system capable of adjusting instruction priorities as claimed in claim 4, wherein the FIFO controller corresponding to the channel selected by the instruction storage arbiter performs read/write operations on the storage space corresponding to the instruction at the same time.
7. A multi-channel instruction controller capable of adjusting instruction priority is characterized by comprising a processor and a memory;
the memory is used for storing a computer program;
the processor is configured to execute the memory-stored computer program to cause the adjustable instruction priority multi-channel instruction controller to perform the adjustable instruction priority multi-channel instruction control method of any one of claims 1-3.
8. A multi-channel command control system capable of adjusting command priorities, comprising the multi-channel command controller capable of adjusting command priorities, a status register, an instruction fetch request arbiter, a command storage arbiter, a command fetch controller, a command decoder, a signal controller, and a command transmitter according to claim 7;
the state register is used for storing the starting address, the ending address and the number of the instruction blocks of the memory space where the address of the instruction block is located, and configuring a read instruction starting signal;
the fetch request arbiter is used for arbitrating different data read requests;
the instruction storage arbiter is used for storing the instruction data transmitted by the bus to a storage space corresponding to the on-chip memory;
the instruction reading controller is used for arbitrating instruction reading requests of different threads in a polling mode and reading instructions in the on-chip memory according to a polling sequence;
the instruction decoder is used for sending instruction data and an equipment mark of equipment equipped instructions to the instruction sender, sending a signal mark corresponding to a synchronous communication instruction between the equipment to the signal controller, and sending an interrupt signal corresponding to an interrupt instruction to the system;
the signal controller is used for receiving a feedback signal of the equipment for the received instruction data and switching a plurality of different threads to control the execution sequence of the equipment;
the instruction transmitter is used for transmitting the instruction data of the equipment to the corresponding equipment.
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| CN110362347B (en) * | 2019-07-18 | 2023-02-28 | 成都夸克光电技术有限公司 | Real-time priority multichannel processor and control method |
| CN110659072B (en) * | 2019-09-26 | 2021-09-14 | 深圳忆联信息系统有限公司 | Pluggable command issuing acceleration method and device based on Queue structure |
| CN111707851B (en) * | 2020-05-05 | 2022-08-16 | 许昌开普检测研究院股份有限公司 | Multi-channel alternating current signal state sequence sequential control generator |
| CN113596867A (en) * | 2021-06-17 | 2021-11-02 | 青岛中科英泰商用系统股份有限公司 | 4g module control method and device based on FreeRTOS system |
| CN114138341B (en) * | 2021-12-01 | 2023-06-02 | 海光信息技术股份有限公司 | Micro instruction cache resource scheduling method, micro instruction cache resource scheduling device, program product and chip |
| CN114328321B (en) * | 2022-03-16 | 2022-05-31 | 宜科(天津)电子有限公司 | Data sampling and communication method in encoder, single chip microcomputer and storage medium |
| CN114584420B (en) * | 2022-05-06 | 2022-08-02 | 艾德克斯电子（南京）有限公司 | Multi-machine equipment networking architecture |
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