CN106959929B - Multi-port access memory and working method thereof - Google Patents
Multi-port access memory and working method thereof Download PDFInfo
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- CN106959929B CN106959929B CN201710159815.8A CN201710159815A CN106959929B CN 106959929 B CN106959929 B CN 106959929B CN 201710159815 A CN201710159815 A CN 201710159815A CN 106959929 B CN106959929 B CN 106959929B
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
Abstract
The invention relates to a multiport memory and an access method thereof, comprising two or more ports, a finite state machine, a time slice round-robin scheduling core and a memory module; one end of each port is coupled to a module for reading and writing data in the memory module, and the other end of each port is connected to the finite-state machine through a bidirectional data line; the finite state machine is connected to the memory module by a bidirectional data line. The invention adopts a simple port data transmission protocol, provides a certain cache space for each port, optimizes arbitration logic, greatly improves arbitration efficiency of multi-port requests, has high equivalent read-write bandwidth and small delay of each port and certain cache capacity when each module of a processor of the communication gateway equipment accesses a memory, realizes rapid processing of high-speed data streams by each module of the communication gateway processor, improves the overall efficiency of the communication gateway equipment, and meets the performance requirements of a high-speed communication network on the gateway equipment.
Description
Technical Field
The invention relates to the technical field of networks, in particular to a multi-port access memory and a working method thereof.
Background
The multi-port access memory is a main mode for caching and exchanging data by each module in a processor in the communication gateway device, and the access efficiency of different ports to the memory determines the processing performance of the whole communication network. With the continuous development and evolution of communication networks, the network bandwidth is continuously improved, and the requirement on the access efficiency of the memory port of the processor in the communication gateway equipment is higher and higher.
The core of the multi-port access memory is a request scheduling mode of multi-port access, and the traditional multi-port access memory is characterized in that each port is allocated with an independent data bus and an independent address bus, and the multi-port access memory is driven by logic and under the drive of the same clock to concurrently access a shared memory module. When the read-write requests of all ports conflict, the access conflict is set through the priority of the hardware ports and the priority of the hardware read-write. However, the problems of no cache capacity of each port, complex bus protocol, low arbitration efficiency and the like exist.
The improved dual-channel memory sets the read-write working signal frequency of the shared memory to be twice of the read-write working signal frequency of the logic module connected to the outside, and sets the switching control signal frequency of the shared memory to be the frequency of the switching control signal of the logic module connected to the outside, so that the memory with a single port is equivalent to the memory with two ports, different external logic modules obtain independent memory access interfaces, but the priority setting of different ports can cause the ports with high priority to occupy the memory interfaces for a long time, and the read-write delay of other ports is overlarge. The problem that each port inside a communication gateway device processor can not efficiently access the memory can not be solved.
Disclosure of Invention
In view of the foregoing analysis, the present invention aims to provide a method for implementing a multi-port access memory, so as to solve various problems of complex port protocols, low arbitration efficiency, no cache capability of a port, and the like when a multi-module accesses a memory in a processor.
The purpose of the invention is mainly realized by the following technical scheme:
in one aspect according to embodiments of the present invention, a multi-port accessed memory is provided, which includes two or more ports, a finite state machine, a slice round robin scheduling core, and a memory module; wherein the content of the first and second substances,
one end of each port is coupled to a module for reading and writing data in the memory module, and the other end of each port is connected to the finite-state machine through a bidirectional data line; the finite state machine is connected to the memory module through a bidirectional data line;
in addition, each port is also connected to a time slice round-robin scheduling core through a signal line, the time slice round-robin scheduling core is connected to a finite state machine through a bidirectional signal line, and the finite state machine is connected to the memory module through the signal line.
In another embodiment of a multi-port access memory according to the invention, the ports use a FIFO interface.
In another aspect according to an embodiment of the present invention, there is provided a method for operating a multi-port access memory, including the steps of:
s1, waiting for response when the read-write request enters the port cache;
s2, setting a port cache non-empty mark to be 1;
s3, after the time slice round robin scheduling core obtains the port cache non-empty identification information, the time slice round robin scheduling core enters the response state of the port from the idle state and sends a notice to the finite state machine;
s4, the finite state machine receives the notice sent by the time slice round dispatching core, and takes out the read/write request from the port cache to carry out corresponding read/write operation;
s5, completing the read/write operation, sending a completion mark to the time slice round-robin scheduling core by the finite state machine, and enabling the time slice round-robin scheduling core to exit the response state of the port;
s6, the time slice round robin scheduling core judges whether there is a port cache non-empty identification which is not responded, if yes, the time slice round robin scheduling core enters the response state of the port, and the step S4 is executed; and if not, the time slice round-robin scheduling core returns to an idle state.
In another embodiment based on the method of the present invention, in step S3, when the slot round robin scheduling core simultaneously acquires the non-empty identification information of multiple port caches, the slot round robin scheduling core randomly selects a port to enter the response state of the port.
In another embodiment of the method according to the present invention, in step S6, when there are a plurality of non-responding port cache non-empty flags, the slot round robin scheduling core randomly selects one response state to enter the port.
In another embodiment of the method according to the present invention, in step S1, when the operation is a read request, the write address bit and the read request bit are required in the FIFO; when operating as a write request, the data bits, address bits, and write request bits need to be written into the FIFO.
In another embodiment based on the method of the present invention, after the time slice round robin scheduling core enters the response state of a certain port, the state is locked, and the non-empty identification of the other port cache is shielded.
The invention has the following beneficial effects:
the invention adopts a simple port data transmission protocol, provides a certain cache space for each port, optimizes arbitration logic, greatly improves arbitration efficiency of multi-port requests, has high equivalent read-write bandwidth and small delay of each port and certain cache capacity when each module of a processor of the communication gateway equipment accesses a memory, realizes rapid processing of high-speed data streams by each module of the communication gateway processor, improves the overall efficiency of the communication gateway equipment, and meets the performance requirements of a high-speed communication network on the gateway equipment.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a block diagram of a multi-port access memory implementation;
FIG. 2 is a diagram of the starting state jump of a time slice round robin scheduling core;
FIG. 3 is a time slice round robin scheduling core operating state jump diagram.
Detailed Description
The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form a part hereof, and which together with the embodiments of the invention serve to explain the principles of the invention.
According to an embodiment of the present invention, a multi-port memory is disclosed, as shown in fig. 1, including: two or more ports, a finite state machine, a time slice round-robin scheduling core and a memory module; wherein the content of the first and second substances,
one end of each port is coupled to a module which is to access data in the memory module, where the module is a service processing module, and in a typical system design, different service modules are provided to perform different service functions, such as a central processing unit and a graphic processor;
the other end of each port is connected to a finite-state machine through a bidirectional data line; the finite state machine is connected to the memory module through a bidirectional data line to realize bidirectional data circulation;
in addition, each port is also connected to a time slice round-robin scheduling core through a signal line, the time slice round-robin scheduling core is connected to a finite-state machine through a bidirectional signal line, and the finite-state machine is also connected to a memory module through a signal line; the time slice rotation scheduling core obtains port cache non-empty identification information, and sends a control instruction to a finite state machine to schedule a read-write request of each port, and the finite state machine sends a control signal to a memory module to control the memory to read and write data;
the port uses a standard first-in first-out queue (FIFO) interface and sets a buffer capacity, specifically, the buffer is a bidirectional buffer, and the buffer capacity is generally 512 bits.
The FIFO interface is used to reduce the operation complexity during read-write access; the cache capacity is set so that each port has certain cache capacity, and the problem of system blockage caused by burst data is effectively solved; the time slice round-robin scheduling method and the finite state machine are used for completing the moving of read-write data of each port and the access of the memory, so that the arbitration efficiency and the equivalent bandwidth of each port are effectively improved.
The working method comprises the following steps:
s1, waiting for response when the read-write request enters the port cache;
the port receives a read-write request from a module connected to the port, and the read request and the write request are executed separately. When the operation is a read request, an Address bit (Address) and a read request bit (R) need to be written into the port FIFO; when operating as a write request, a write Data bit (Data), an Address bit (Address), and a write request bit (W) are required in the port FIFO.
The module is referred to as a service processing module, and in a typical system design, different service modules are used for completing different service functions.
S2, setting a port cache non-empty mark to be 1;
the non-empty flag set to 1 indicates that there is a data read/write request in the port cache.
The port buffer is used for receiving external read-write requests, the port buffer is provided with a 1-bit signal line for indicating whether data exists in the buffer, and when no data exists in the port buffer, the signal line is '0'; when there is data (read/write request) in the port buffer, the signal line is "1".
Therefore, the signal line is also called a port cache non-empty flag for indicating whether there is a read/write request in the cache.
S3, after the time slice round robin scheduling core obtains the port cache non-empty identification information, the time slice round robin scheduling core enters the response state of the port from the idle state and sends a notice to the finite state machine;
the input of the time slice round-robin scheduling core is a non-empty identifier of each port cache, and when each port has no request, the time slice round-robin scheduling core is in an idle state.
Further, when the time slice round-robin scheduling core simultaneously acquires the non-empty identification information of the plurality of port caches, the time slice round-robin scheduling core randomly selects one port to enter the response state of the port, locks the state, shields the non-empty identification information of other port caches, and waits for the indication information of the port requesting response completion;
s4, the finite state machine receives the notice sent by the time slice round dispatching core, and takes out the read/write request from the corresponding port cache to carry out corresponding read/write operation;
the finite state machine is in an idle state when not receiving the notice of the time slice round-robin scheduling core, enters a working state after receiving the notice, and enters the idle state after the processing of all the port requests is completed, and waits for a new port read-write request.
Specifically, for a read request of a port, the finite state machine fetches an address bit from a port cache, reads data of a corresponding address according to a read timing sequence of the memory, returns the data to the cache of the corresponding port, and waits for a module sending the read request to read the data. For the write request of the port, the finite state machine takes out the data bit and the address bit from the port cache, and writes the data into the corresponding address according to the write time sequence of the memory to finish the write operation.
S5, completing the read-write operation, transmitting a completion mark to the time slice round-robin scheduling core by the finite state machine, and enabling the time slice round-robin scheduling core to exit the response state of the port;
s6, the time slice round robin scheduling core judges whether there is a port cache non-empty identification which is not responded, if yes, the time slice round robin scheduling core enters the response state of the port, locks the state, shields the non-empty identifications of other port caches, and executes the step S4 to wait for a port request response completion mark; if not, the time slice round-robin scheduling core returns to an idle state, and the finite-state machine simultaneously enters the idle state to wait for a new port read-write request;
further, when there are a plurality of non-responding port cache non-empty identifiers, the time slice round robin scheduling core randomly selects one response state entering the port.
And after the read-write requests of all the ports are processed, the time slice round-robin scheduling core returns to the idle state.
The beneficial effects of the invention include:
the invention adopts a simple port data transmission protocol, provides a certain cache space for each port, optimizes arbitration logic, greatly improves arbitration efficiency of multi-port requests, has high equivalent read-write bandwidth and small delay of each port and certain cache capacity when each module of a processor of the communication gateway equipment accesses a memory, realizes rapid processing of high-speed data streams by each module of the communication gateway processor, improves the overall efficiency of the communication gateway equipment, and meets the performance requirements of a high-speed communication network on the gateway equipment.
Those skilled in the art will appreciate that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program, which is stored in a computer readable storage medium, to instruct related hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (5)
1. A multi-port access memory is characterized by comprising two or more ports, a finite state machine, a time slice round-robin scheduling core and a memory module; wherein the content of the first and second substances,
one end of each port is coupled to a module for reading and writing data in the memory module, and the other end of each port is connected to the finite-state machine through a bidirectional data line; the finite state machine is connected to the memory module through a bidirectional data line;
in addition, each port is also connected to a time slice round-robin scheduling core through a signal line, the time slice round-robin scheduling core is connected to a finite-state machine through a bidirectional signal line, and the finite-state machine is connected to a memory module through the signal line;
after the time slice round-robin scheduling core acquires the non-empty identification information cached by the port, the time slice round-robin scheduling core enters a response state of the port from an idle state and sends a notice to the finite-state machine;
the finite state machine receives a notice sent by the time slice round-robin scheduling core, takes out a read/write request from a corresponding port cache and carries out corresponding read/write operation;
when the read-write operation is finished, the finite state machine transmits a finishing mark to the time slice round-robin scheduling core, so that the time slice round-robin scheduling core exits the response state of the port;
when the time slice round-robin scheduling core simultaneously acquires the non-empty identification information of the plurality of port caches, the time slice round-robin scheduling core randomly selects one port to enter the response state of the port, locks the state, shields the non-empty identification information of other port caches, and waits for the indication information of the port requesting response completion;
the port cache non-empty identification information is a cache identification of which the signal line is '1' when the port receives a read-write request.
2. A multi-port access memory as claimed in claim 1, wherein the ports use FIFO interfaces.
3. A method of operating a multi-port access memory as claimed in claim 1, comprising the steps of:
s1, waiting for response when the read-write request enters the port cache;
s2, setting a port cache non-empty mark to be 1;
s3, after the time slice round robin scheduling core obtains the port cache non-empty identification information, the time slice round robin scheduling core enters the response state of the port from the idle state and sends a notice to the finite state machine; when the time slice round-robin scheduling core simultaneously obtains the non-empty identification information cached by a plurality of ports, the time slice round-robin scheduling core randomly selects one port to enter the response state of the port; after the time slice round-robin scheduling core enters a response state of a certain port, locking the state and shielding non-empty identifiers cached by other ports;
s4, the finite state machine receives the notice sent by the time slice round dispatching core, and takes out the read/write request from the port cache to carry out corresponding read/write operation;
s5, completing the read/write operation, sending a completion mark to the time slice round-robin scheduling core by the finite state machine, and enabling the time slice round-robin scheduling core to exit the response state of the port;
s6, the time slice round robin scheduling core judges whether there is a port cache non-empty identification which is not responded, if yes, the time slice round robin scheduling core enters the response state of the port, and the step S4 is executed; and if not, the time slice round-robin scheduling core returns to an idle state.
4. The operating method of claim 3, wherein in step S6, when there are more than one port cache non-empty flags that do not respond, the time slice round robin scheduling core randomly selects a response state to enter the port.
5. The method of claim 3, wherein in step S1, when the operation is a read request, the FIFO needs a write address bit and a read request bit; when operating as a write request, the data bits, address bits, and write request bits need to be written into the FIFO.
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| CN107613529B (en) * | 2017-07-31 | 2021-06-01 | 上海华为技术有限公司 | Message processing method and base station |
| CN108897696B (en) * | 2018-06-15 | 2022-11-29 | 西安微电子技术研究所 | Large-capacity FIFO controller based on DDRx memory |
| CN112035383B (en) * | 2019-06-04 | 2023-01-03 | 北京邮电大学 | Data scheduling method, device and system |
| CN110519181B (en) * | 2019-07-23 | 2022-09-06 | 中国航空无线电电子研究所 | Exchange method based on cross-frequency-band time-triggered communication |
| CN115017093B (en) * | 2022-05-06 | 2023-03-24 | 北京中科昊芯科技有限公司 | Method and device for on-chip external bus communication |
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