CN109981431B

CN109981431B - CAN bus controller data storage circuit and data storage method

Info

Publication number: CN109981431B
Application number: CN201910198926.9A
Authority: CN
Inventors: 黄九余; 苏若皓; 娄冕; 郭娜娜
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2019-03-15
Filing date: 2019-03-15
Publication date: 2021-09-14
Anticipated expiration: 2039-03-15
Also published as: CN109981431A

Abstract

The invention discloses a CAN bus controller data storage circuit and a data storage method, which realize data interaction between a CAN kernel data buffer area and a mailbox by arranging an information processing module; the register and the mailbox access module realize information interaction between the processor and the mailbox; the RAM access arbitration module controls access to the mailbox; the invention adopts a dual-port RAM which is divided into 128 mailboxes, and the control of the information processing module ensures that for any one sending mailbox, if ID and frame information do not need to be changed, only data bits need to be updated every time; for a receiving mailbox, after the received data is read by a processor, the processor can reconfigure the ID and mask bit of the receiving mailbox through a mirror register so that the mailbox can receive the data of a new ID node; by numbering mailboxes to store data, the processor can know clearly which mailbox the data comes from, without ID decoding.

Description

CAN bus controller data storage circuit and data storage method

Technical Field

The invention belongs to the field of integrated circuit design, and particularly relates to a CAN bus controller data storage circuit and a data storage method.

Background

A currently widely used CAN bus controller chip is a SJA1000 chip manufactured by PHILIPS corporation, which sets a node reception ID and an ID mask (mask) in a reset mode, and stores reception data using a FIFO having a capacity of 64 bytes. A data buffer is formed using 13 registers having a bit width of 8bits, and is shared for transmission and reception. In the transmission, since the buffer is shared for transmission and reception, it is necessary to write the frame information and the frame ID into the transmission buffer in the same manner every time except for writing new frame data into the transmission buffer, even if the frame information and the ID of the two transmissions are completely the same. When receiving, the processor reads the received data including the frame information, the frame ID and the frame data from the FIFO through the receiving buffer, and then the processor needs to analyze the frame ID to know from which node the read frame data is transmitted, and further, determines how to process the frame data according to the system configuration. After reading one frame of data, if the next frame of data needs to be read continuously, the processor needs to send a command of releasing the receiving buffer to the CAN controller, move the window of the receiving buffer to the position of the next frame of data, and map the frame of data into the receiving buffer.

There are four significant disadvantages to this manner of storing received and transmitted data in the face of multiple nodes and large data volumes. One is that the receiving ID and mask of the node can only be set in the reset mode, and the receiving ID and mask can not be flexibly changed in the working process. The other is that since the buffer is shared for transmission and reception, the frame information and frame ID must be updated every time transmission takes into account the possibility of transmission and reception interleaving. Obviously, this is not necessary for a node to send a fixed ID and frame information. Thirdly, if a node receives data from multiple nodes, all the node data are stored together indiscriminately, and the processor needs to decode the frame ID for each frame of data read back, determine where the frame comes from, and then determine how to process the frame, which causes a large programming burden to the processor in the application. And fourthly, the capacity of the receiving FIFO is too small, if an extended frame of 8-byte data is received, 4 frames of data can be stored at most, and during continuous receiving, if the processor cannot read the data in time, the FIFO is easy to overflow. For the four defects, the data storage mode is adopted, so that the use of the user is more convenient and concise, and no good solution is provided at present after relevant documents are retrieved.

Disclosure of Invention

The invention aims to provide a CAN bus controller data storage circuit, which establishes a perfect mailbox and register configuration and access method, solves the defects in the background technology, enables the data sending and receiving operation to be simpler and faster and is convenient for users to use.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a CAN bus controller data storage circuit comprises a data storage unit and an access module, wherein the data storage unit comprises 128 mailboxes, and the access module comprises an information processing module, a register, a mailbox access module and an RAM access arbitration module; the information processing module is used for realizing data interaction between the CAN kernel data buffer area and the mailbox; the register and the mailbox access module are used for realizing information interaction between the processor and the mailbox; the RAM access arbitration module is used for arbitrating when the information processing module, the register and the mailbox access module simultaneously access the mailbox so as to control the access to the mailbox.

Furthermore, the information processing module comprises a mailbox reading circuit, a mailbox writing circuit, a register reading circuit, a register writing circuit, a receiving filter circuit and a CAN kernel state monitoring module; the mailbox reading circuit is used for reading the ID and the mask relevant bit of the receiving mailbox and matching the read ID and the mask relevant bit of the receiving mailbox with the received ID; the mailbox writing circuit is used for writing the received frame data and the ID and the mask thereof into the currently received mailbox and updating the corresponding state bit in the register; the register reading circuit is used for reading the state and data of the CAN kernel state register; the register writing circuit is used for writing the data of the CAN kernel buffer into the mailbox; the receiving filter circuit is used for carrying out filter processing on the received frame when the CAN kernel is in a receiving state and sending a filter result to the mailbox writing circuit; the CAN kernel state monitoring module is used for judging whether the CAN bus is idle or not.

Furthermore, the register and mailbox access module comprises a mirror image register and a control and state register; the mirror image register is used for caching data in the process of reading and writing access of the mailbox by the processor; the control and status register is for storing control and status bits for the mailbox, the mailbox control and status bits including: interrupt enable, frame data length, ID mask enable, mailbox data valid flag, interrupt flag, and send request flag.

Further, the control and status registers comprise 13 128-bit registers for implementing configuration and status monitoring of the mailbox by the processor; wherein each register corresponds to a control bit or status bit of the mailbox.

Furthermore, the data storage unit is a dual-port RAM, the dual-port RAM is divided into 128 mailboxes, and the mailboxes are used for storing frame data, frame IDs, masks, mailbox valid flag bits and mailbox configuration bits.

Furthermore, in the register and mailbox access module, all mailboxes are configured into sending mailboxes or receiving mailboxes according to requirements; and under the working mode of the CAN controller, dynamically configuring the mailbox according to the requirement when the mailbox is idle, and changing the ID, the mask, the data and the control bit of the mailbox.

A CAN bus controller data storage method comprises the following steps:

establishing mapping between mailbox ID and mailbox RAM address;

when the CAN kernel receives data, the information processing module reads out frame data, a frame ID and a frame mask thereof from a receiving buffer of the CAN kernel; after acquiring the mailbox access right, the information processing module accesses the receiving mailboxes one by one, writes frame data, a frame ID and a frame mask into the receiving mailboxes, and matches the ID of the receiving mailboxes with the frame ID; meanwhile, a mailbox write circuit of the information processing module updates corresponding status bits in a register and a status register in the mailbox access module;

when the processor sends data through the CAN kernel, the processor writes frame data of a frame to be sent, a frame ID and a frame mask into a sending mailbox through a register and a mirror image register in a mailbox access module, and the ID of the sending mailbox is matched with the frame ID; when the CAN bus is idle, a mailbox reading circuit of the information processing module sends frame data of a mailbox to be sent and an ID (identity) of the frame data to be sent to a CAN kernel; meanwhile, a mailbox write circuit of the information processing module updates the corresponding status bit of the mailbox in a status register in the mailbox access module.

Further, after the mailbox writing circuit of the information processing module obtains the mailbox access right, the receiving filter circuit of the information processing module judges whether receiving filtering is needed or not according to the mailbox receiving filtering control bit; when receiving filtering is not needed, the CAN kernel writes the received frame data and the ID and the mask of the frame data into a receiving mailbox, updates the corresponding state bit in the state register and finishes mailbox access and receiving data storage; when receiving and filtering are needed, the CAN kernel reads the ID of the receiving mailbox and the relevant bits of the mask from the mailbox and matches the ID of the received frame data, if the two IDs are matched, the received ID, the mask and the data are stored in the mailbox, the corresponding state bits in a state register in a register and a mailbox access module are updated, and the subsequent mailbox is not accessed any more after the received data are stored; if the two IDs do not match, continuously inquiring the next receiving mailbox until a matching mailbox is found; if the received ID and the IDs of all receiving mailboxes do not match, the data is stored in the last mailbox through configuration.

Further, a specific method for the processor to send data through the CAN core is as follows: the processor writes the frame data to be sent, the ID, the mask and the control bit into a register and a mirror image register in a mailbox access module partially or completely based on the updating requirement, and then a mailbox writing circuit of the information processing module writes the updated mirror image register data into a mailbox after acquiring the mailbox access right; when the CAN kernel state monitoring module judges that the CAN bus is idle through the corresponding state bit of the CAN kernel register, a sending circuit of the information processing module inquires the sending request flag bits of all sending mailboxes, a mailbox reading circuit of the information processing module sequentially reads frame data and IDs (identity) of the mailboxes with effective sending request flag bits according to the sequence of the mailbox numbers from small to large and sends the frame data and the IDs to the CAN kernel for framing and sending, and a mailbox writing circuit of the information processing module updates the corresponding state bits in the register and a mailbox access module.

Furthermore, in the process of receiving and sending the data, the priority of the access of the processor to the mailbox is higher than the priority of the access of the information processing module to the mailbox.

Compared with the prior art, the invention has at least the following beneficial effects:

the data storage method adopted by the invention can effectively avoid the problems of troublesome receiving configuration change, redundant sending configuration, fussy ID analysis and small receiving FIFO capacity in the using process of the SJA1000 chip, and is specifically represented as follows:

(1) the bus receiving and sending data are stored separately, and the frames with different IDs can be stored in different mailboxes.

(2) For a receiving mailbox, after the received data is read by the processor, the processor can reconfigure the ID and mask bits thereof through the mirror register so that the mailbox can receive the data of a new ID node.

(3) Because the data received from different nodes are all stored in the receiving mailbox with corresponding ID, the processor can clearly know which node the data comes from when reading the data from the mailbox, does not need to carry out ID decoding, and directly carries out corresponding processing on the data after reading the data.

(4) The data of the frame can be stored by using 128 mailboxes, each mailbox can store one complete frame of data, and 128 complete frames of data can be stored, and the storage capacity is larger than that of SJA 1000.

Drawings

FIG. 1 is a block diagram of a data storage circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram of an information processing module according to an embodiment of the present invention;

FIG. 3 is a block diagram of a register and mailbox access module according to an embodiment of the present invention;

fig. 4 is a diagram of a RAM access arbitration logic structure according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

In order to solve the problems of configuration of receiving ID and mask, repeated operation during transmission, analysis of receiving ID and small capacity of receiving FIFO, a data storage circuit structure of a CAN bus controller is shown in figure 1. The memory circuit consists of a data memory unit and an access module thereof. The CAN kernel is used for generating CAN bit time sequence and assembling and analyzing frames according with CAN2.0 protocol. The information processing module is used for realizing data transmission between the CAN kernel and the mailbox, mainly reading transmission data from the mailbox in a transmission state, transmitting the transmission data to the CAN kernel for framing transmission, and storing the data received by the CAN kernel into the mailbox matched with the ID in a receiving state. The register and mailbox access module is used for realizing the configuration and access of the processor to the mailbox. In the reset mode, the processor has direct access to the RAM unit. The RAM access logic mainly realizes the arbitration control when the sending, receiving and processor indirectly access the mailbox through the mirror image register, and avoids access conflict. And each mailbox is used for storing 127bits of valid data, wherein the valid data comprises data7-data0 eight bytes of frame data, a frame ID, a mask and other relevant bits.

The data storage unit is composed of a dual-port RAM and a group of registers. The RAM unit capacity is 512 x 32bits, and is divided into 128 mailboxes, each mailbox storage space is 4 x 32bits, and the mailboxes are used for storing the received frame ID, the ID mask code and the data of at most 8 bytes.

The registers in the register group are divided into two types, one is a mailbox mirror register, and the other is each mailbox control and status register. The mailbox mirror register comprises an ID mirror register, an ID mask mirror register and a data mirror register, and the bit definition of the mailbox mirror register is completely the same as the data bit definition stored in the mailbox. The mailbox mirror image register is used for caching data in the process of reading and writing access of the mailbox by the processor, when the processor reads data from the mailbox, the read data is stored in the mirror image register and is used by the processor, when the processor writes data into the mailbox, the data is written into the mirror image register firstly, and then the mailbox access module writes the data into the corresponding mailbox. The control register and status controller is implemented using a set of 128-bit registers for storing mailbox control and status flags including interrupt enable, frame data length, ID mask enable, mailbox data valid flag, interrupt flag, send request flag, etc., each control and status register corresponding to a control or status bit of a mailbox, each bit of the register corresponding to a corresponding bit of a mailbox. The processor realizes the configuration and the state monitoring of the mailbox through the group of registers.

The data storage unit access module comprises an information processing module, a register and mailbox access module and a RAM access arbitration module in the figure 1. The information processing module realizes data interaction between the CAN kernel data buffer area and the mailbox, and consists of a sending logic, a receiving logic and a CAN kernel state monitoring module, and the structure of the information processing module is shown in a dotted line frame in figure 2.

During sending, the sending logic needs to judge whether the CAN bus is idle through the CAN kernel state monitoring module so as to determine whether the CAN bus CAN be sent immediately; during receiving, the receiving logic needs to judge whether a frame of data is received from the bus through the CAN kernel state monitoring module. In summary, the CAN core status monitor module is used to provide the transmit and receive logic with whether the current bus CAN transmit data or whether data is received.

When receiving (when the node receives data from the bus), the CAN kernel monitoring module judges that the CAN kernel successfully receives a frame of data from the CAN bus through a relevant register and an interrupt zone bit in the CAN kernel; a register reading circuit of the information processing module reads data from a receiving buffer of a CAN kernel; then, after acquiring the mailbox access right, a mailbox writing circuit of the information processing module accesses receiving mailboxes one by one according to the priority, and a receiving filter circuit judges whether receiving filtering is needed or not by using a mailbox receiving filtering control bit;

if the receiving and filtering are not needed, a mailbox writing circuit of the information processing module writes the frame data received from the bus, the ID and the mask thereof into the currently received mailbox, meanwhile, the mailbox writing circuit of the information processing module updates the corresponding status bit in the status register, and the received data is stored and the subsequent mailbox is not accessed;

if receiving filtering is needed, a mailbox reading circuit of the information processing module reads the ID and the mask related bit of the receiving mailbox, and matches the read ID and the mask related bit of the receiving mailbox with the ID of the received frame data:

if the two IDs are matched, the mailbox writing circuit of the information processing module writes the received frame data and the ID and the mask thereof into the matched receiving mailbox, meanwhile, the mailbox writing circuit of the information processing module updates the corresponding state bit in the register, and the subsequent mailbox is not accessed after the received data is stored.

If the two IDs are not matched, the mailbox reading circuit of the information processing module continuously reads the next receiving mailbox and performs matching until a matched mailbox is found; and if the received ID is not matched with the IDs of all the receiving mailboxes, the processor stores the data in the last mailbox through preset configuration, so that the data loss is avoided.

When the node sends data to the bus, the processor partially or completely writes the ID, the mask, the frame data and the control bit of the frame to be sent into the mirror image register based on the updating requirement, then the mailbox writing circuit of the information processing module writes the updated content of the mirror image register into the mailbox after acquiring the mailbox access right, and the valid flag bit of the mailbox data and the sending request flag bit are set; when the CAN kernel state monitoring module judges that a CAN bus is idle through the corresponding state bit of a CAN kernel register, the sending module inquires the sending request flag bits of all sending mailboxes, a mailbox reading circuit of the information processing module sequentially reads out the frame data and the IDs of the mailboxes with effective sending request flag bits and sends the frame data and the IDs to the CAN kernel for framing and sending according to the mode that the number of the mailboxes is from small to large, and a mailbox writing circuit of the information processing module updates the corresponding state bit in the state register. If the bus is occupied, monitoring continues, waiting for it to be idle.

Fig. 3 shows a block diagram of a register and mailbox access module, which includes a mailbox access module, mirror registers, and other registers. The other registers comprise a mailbox control register and a mailbox state register, the mailbox control register is used for the processor to realize the configuration of the mailbox, and the mailbox state register is used for the information processing module to judge the mailbox state; the mailbox access module is used for realizing the indirect access of the processor to the mailbox through the mirror image register. After the CAN controller enters a working mode, the processor writes a mailbox number and control information into the mailbox control register, writes the ID, mask, data and other relevant bits corresponding to the frame of the mailbox with the number to be written into the mirror image register, and then the mailbox access module automatically writes the configuration information belonging to the mailbox into the RAM area corresponding to the mailbox number and writes other control information bits into the control register corresponding to the mailbox number.

The register and mailbox access module realizes information interaction between the processor and the mailbox, and is composed of a mirror image register, a control register, a state register and a mailbox access module, as shown in fig. 3. The mailbox access module establishes the mapping of the mailbox number and the mailbox RAM address, the processor assigns the mailbox number and the related configuration data through the configuration mirror image register and the control register, and under the control of the mailbox access module, the information in the mailbox is read out to the corresponding register, or the configuration data is transmitted to the mailbox needing to be configured and the corresponding control register through the register. All the mailboxes can be configured into a sending mailbox or a receiving mailbox according to needs, each mailbox can be independently used for storing one frame of data, and a plurality of mailboxes can be connected in series to form a FIFO for storing multi-frame data. In the operational mode, each mailbox may be reconfigured on the fly to change all or part of its ID, mask, data and control bits.

Fig. 4 shows a structure diagram of the RAM access arbitration module. The RAM access arbitration module is used for processing the arbitration of the mailbox access right in the receiving module, the sending module and the register in the information processing module and the mailbox access module in the mailbox access module. In order to ensure that the mailbox can be accessed and configured by the processor at any time, the access priority of the processor to the RAM is higher than that of the information processing module. And finally, the priority of the RAM access arbitration module sequentially comprises processor writing logic, processor reading logic, information processing module receiving logic and information processing module sending logic from high to low.

The RAM read-write signals and data comprise RAM read-write enable and read-write data with bit width of 32 bits. Each module (including a receiving module, a sending module and a register in the information processing module and a mailbox access module in the mailbox access module) must judge whether the RAM port is occupied before initiating access to the RAM, if not, the RAM access is carried out and the RAM occupation state position is set until the access is finished and then the RAM port is cleared, and if the RAM port is occupied, the RAM port is waited to be free, and then which module obtains the RAM access right according to arbitration logic.

While the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments, which are illustrative, instructional and not restrictive, and various changes and modifications may be made without departing from the spirit and scope of the invention as set forth in the appended claims. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A CAN bus controller data storage circuit is characterized by comprising a data storage unit and an access module, wherein the data storage unit comprises 128 mailboxes, and the access module comprises an information processing module, a register and mailbox access module and a RAM access arbitration module; wherein the content of the first and second substances,

the information processing module is used for realizing data interaction between the CAN kernel data buffer area and the mailbox;

the register and the mailbox access module are used for realizing information interaction between the processor and the mailbox;

the RAM access arbitration module is used for arbitrating when the information processing module, the register and the mailbox access module simultaneously access the mailbox so as to control the access to the mailbox;

the register and mailbox access module comprises a mailbox access module, a mirror image register and a control and status register; wherein the content of the first and second substances,

the mirror image register is used for caching data in the process of read-write access of the mailbox by the processor;

the control and status register is for storing control and status bits for a mailbox, the mailbox control and status bits including: interrupt enable, frame data length, ID shielding enable, mailbox data valid flag, interrupt flag and send request flag;

the mailbox access module establishes the mapping of the mailbox number and the mailbox RAM address, the processor designates the mailbox number and the related configuration data through the configuration mirror image register and the control and state register, and under the control of the mailbox access module, the information in the mailbox is read out to the corresponding register, or the configuration data is transmitted to the mailbox needing to be configured and the corresponding control and state register through the register.

2. The CAN bus controller data storage circuit of claim 1, wherein the information processing module comprises a mailbox read circuit, a mailbox write circuit, a register read circuit, a register write circuit, a receive filter circuit, and a CAN core status monitor module; wherein the content of the first and second substances,

the mailbox reading circuit is used for reading the ID and the mask relevant bit of the receiving mailbox and matching the read ID and the mask relevant bit of the receiving mailbox with the received ID;

the mailbox writing circuit is used for writing the received frame data and the ID and the mask thereof into the currently received mailbox and updating the corresponding state bit in the register;

the register reading circuit is used for reading the state and data of the CAN kernel state register;

the register writing circuit is used for writing the data of the CAN kernel buffer into the mailbox;

the receiving filter circuit is used for carrying out filter processing on a received frame when the CAN kernel is in a receiving state and sending a filter result to the mailbox writing circuit;

the CAN kernel state monitoring module is used for judging whether a CAN bus is idle or not.

3. The CAN bus controller data storage circuit of claim 1, wherein the control and status registers comprise 13 128-bit registers for enabling configuration and status monitoring of mailboxes by the processor; wherein each register corresponds to a control bit or status bit of the mailbox.

4. The CAN-bus-controller data-storage circuit of claim 1, wherein the data-storage unit is a dual-port RAM divided into 128 mailboxes, and the mailboxes are used for storing frame data, a frame ID, a mask, a mailbox valid flag bit, and a send-receive mailbox configuration bit.

5. The CAN bus controller data storage circuit of claim 1, wherein in the register and mailbox access module, all mailboxes are configured as send mailboxes or receive mailboxes as needed; and under the working mode of the CAN controller, dynamically configuring the mailbox according to the requirement when the mailbox is idle, and changing the ID, the mask, the data and the control bit of the mailbox.

6. A method for storing the CAN bus controller data storage circuit according to any one of claims 1 to 5, comprising:

establishing mapping between mailbox ID and mailbox RAM address;

when the CAN kernel receives data, the information processing module reads out frame data, a frame ID and a frame mask thereof from a receiving buffer of the CAN kernel; after acquiring mailbox access rights, the information processing module accesses receiving mailboxes one by one and writes frame data, a frame ID and a frame mask into the receiving mailboxes, wherein the ID of the receiving mailboxes is matched with the frame ID; meanwhile, a mailbox write circuit of the information processing module updates corresponding status bits in a register and a status register in the mailbox access module;

when the processor sends data through the CAN kernel, the processor writes frame data of a frame to be sent, a frame ID and a frame mask into a sending mailbox through a register and a mirror image register in a mailbox access module, wherein the ID of the sending mailbox is matched with the frame ID; when the CAN bus is idle, a mailbox reading circuit of the information processing module sends frame data of a mailbox to be sent and an ID (identity) of the frame data to be sent to a CAN kernel; meanwhile, a mailbox write circuit of the information processing module updates a corresponding status bit of the mailbox in a status register in the mailbox access module.

7. The CAN bus controller data storage method of claim 6, wherein after the mailbox write circuit of the information processing module obtains the mailbox access right, the receive filter circuit of the information processing module judges whether the receive filter is needed according to the mailbox receive filter control bit;

when receiving filtering is not needed, the CAN kernel writes the received frame data and the ID and the mask of the frame data into a receiving mailbox, updates the corresponding state bit in the state register and finishes mailbox access and receiving data storage;

when receiving and filtering are needed, the CAN kernel reads the ID of the receiving mailbox and the relevant bits of the mask from the mailbox and matches the ID of the received frame data, if the two IDs are matched, the received ID, the mask and the data are stored in the mailbox, the corresponding state bits in a state register in a register and a mailbox access module are updated, and the subsequent mailbox is not accessed any more after the received data are stored; if the two IDs do not match, continuously inquiring the next receiving mailbox until a matching mailbox is found; if the received ID and the IDs of all receiving mailboxes do not match, the data is stored in the last mailbox through configuration.

8. The CAN bus controller data storage method of claim 6, wherein the specific method for the processor to send data through the CAN core is as follows: the processor writes the frame data to be sent, the ID, the mask and the control bit into a register and a mirror image register in a mailbox access module partially or completely based on the updating requirement, and then a mailbox writing circuit of the information processing module writes the updated mirror image register data into a mailbox after acquiring the mailbox access right; when the CAN kernel state monitoring module judges that the CAN bus is idle through the corresponding state bit of the CAN kernel register, a sending circuit of the information processing module inquires the sending request flag bits of all sending mailboxes, a mailbox reading circuit of the information processing module sequentially reads frame data and IDs (identity) of the mailboxes with effective sending request flag bits according to the sequence of the mailbox numbers from small to large and sends the frame data and the IDs to the CAN kernel for framing and sending, and a mailbox writing circuit of the information processing module updates the corresponding state bits in the register and a mailbox access module.

9. The CAN-bus-controller data storage method of claim 6, wherein the access of the mailbox by the processor is prioritized over the access of the mailbox by the information processing module during the reception and transmission of the data.