CN109981431A - A kind of CAN controller data storage circuitry and date storage method - Google Patents
A kind of CAN controller data storage circuitry and date storage method Download PDFInfo
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- CN109981431A CN109981431A CN201910198926.9A CN201910198926A CN109981431A CN 109981431 A CN109981431 A CN 109981431A CN 201910198926 A CN201910198926 A CN 201910198926A CN 109981431 A CN109981431 A CN 109981431A
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- mailbox
- data
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- frame
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
Abstract
The invention discloses a kind of CAN controller data storage circuitry and date storage methods, pass through the data interaction between the setting information kernel data buffer processing modules implement CAN and mailbox；Register and mailbox access module realize the information exchange between processor and mailbox；RAM access arbitration module controls the access to mailbox；The present invention uses one piece of two-port RAM, which is divided into 128 mailboxes, by the control of message processing module, so that sending mailbox for any one, if sending ID, frame information without changing, only needs more new bit every time；For a reception mailbox, after received data are read by processor, processor can be reconfigured its ID and mask by mirror registers, so that the mailbox can receive the data of new ID node；By the way that storing data is numbered in mailbox, enable a processor to clearly know data from which mailbox, without carrying out ID decoding.
Description
Technical field
The invention belongs to IC design fields, and in particular to a kind of CAN controller data storage circuitry and number
According to storage method.
Background technique
Now widely used CAN controller chip is the SJA1000 chip of PHILIPS company production, the chip
Node is set under reset mode and receives ID and ID mask off code (mask), is connect using the FIFO that a capacity is 64 bytes to store
Receive data.Data buffer is constituted using the register that 13 bit wides are 8bits, sends and receives and shares the buffer.It sends
When, due to sending and receiving common buffer, every time other than transmission buffer is written in new frame data, it is necessary to by frame
Transmission buffer is equally written in information and frame ID, even if the frame information sent twice is identical with ID.When reception, processor is logical
It crosses reception buffer to read the reception data including frame information, frame ID and frame data from FIFO, then processor needs
Frame ID is parsed just can know reading this frame data be sent from which node, and then according to system structure come
Determine how to handle the frame data.After running through a frame data, continue to read next frame data if necessary, then processor need to
CAN controller sends release and receives buffer order, will receive buffer window and moves on to next frame Data Position, by the frame data
It is mapped to and receives in buffer.
When receiving in face of multinode and big data quantity, this storage mode for sending and receiving data is obvious there are four
It is insufficient.One is the reception ID and mask of node can only be arranged under reset mode, it cannot flexibly change it during the work time
Receive ID and mask.The second is due to sending and receiving common buffer, it is contemplated that progress may be interted by sending and receiving, therefore
Frame information and frame ID must be all updated when sending every time.It is sent clearly for one for the node that ID and frame information are fixed, this
It is unnecessary.The third is all node datas are deposited by indiscriminate if a node receives the data of multiple nodes
Together, processor requires first to decode frame ID to each frame data to read back for storage, determines that the frame data come wherefrom,
Then it just can determine that how this is handled, cause larger programming to bear to processor in application.The fourth is receiving FIFO capacity mistake
It is small, if receiving the extension frame of 8 byte datas, 4 frame data can be at most stored, when continuously receiving, if processor cannot be timely
Data are read, FIFO is easily caused to overflow.For this four drawbacks, when which kind of data storage method can user be used using
It is more convenient succinct, through retrieving pertinent literature, at present still without good solution.
Summary of the invention
It is an object of the invention to propose a kind of CAN controller data storage circuitry, establish perfect mailbox and
Register configuration and access method solve the deficiency in background technique, so that it is simpler quick to send and receive data manipulation,
It is user-friendly.
To achieve the goals above, the technical scheme adopted by the invention is as follows:
A kind of CAN controller data storage circuitry, including data storage cell and access modules, data storage cell
Including 128 mailboxes, access modules include message processing module, register and mailbox access module and RAM access arbitration mould
Block；Wherein, message processing module is for realizing the data interaction between the kernel data buffer CAN and mailbox；Register and mailbox
Access modules are for realizing the information exchange between processor and mailbox；RAM access arbitration module be used for message processing module with
Register and mailbox access module are arbitrated when accessing mailbox simultaneously, to control the access to mailbox.
Further, message processing module includes mailbox reading circuit, mailbox write circuit, register reading circuit, register write
Circuit, wave reception filtering circuit and CAN kernel state monitoring module；Wherein, mailbox reading circuit be used for reads receive mailbox ID with
Mask relevant bits, and the read ID and mask relevant bits for receiving mailbox are matched with the ID received；Mailbox writes electricity
Frame data and its ID, mask write-in that road is used to receive are current to be received in mailbox, while updating corresponding state in register
Position；Register reading circuit is used to read the state and data of CAN kernel status register；Register write circuit is used for CAN kernel
Mailbox is written in the data of buffer；Wave reception filtering circuit is used for when CAN kernel is in reception state, is carried out to the frame received
Filtering processing, and filter result is sent to mailbox write circuit；Whether CAN kernel state monitoring module is for judging CAN bus
It is idle.
Further, register and mailbox access module include mirror registers, control and status register；Wherein, mirror
As register is written and read the data in access process to mailbox for cache processor；Control and status register are for storing
The control of mailbox and mode bit, mailbox control and mode bit include: to interrupt enabled, frame data length, ID to shield enabled, mailbox number
According to effective marker, interrupt identification and send request flag.
Further, it controls and status register includes 13 128 registers, for realizing processor to mailbox
Configuration and condition monitoring；Wherein, each register pair answers a kind of control bit or mode bit of mailbox.
Further, data storage cell is one piece of two-port RAM, and two-port RAM is divided into 128 mailboxes, and mailbox is used for
Store frame data, frame ID, mask and mailbox effective marker position, transmitting-receiving mailbox configurations position.
Further, in register and mailbox access module, all mailboxes are configured as needed to send mailbox or reception
Mailbox；Under CAN controller operating mode, carry out dynamic configuration according to demand during idle time in mailbox, change mailbox ID,
Mask, data and control bit.
A kind of CAN controller date storage method, comprising:
Establish the mapping between mailbox ID and mailbox address ram；
When CAN kernel receives data, message processing module read from the reception buffer of CAN kernel frame data and
Its frame ID and frame mask；Message processing module is after obtaining mailbox access power, and access receives mailbox one by one, and by frame data and
Frame ID, frame mask write-in receive mailbox, and the ID and frame ID for receiving mailbox match；Meanwhile the mailbox of message processing module writes electricity
Road updates corresponding state position in the status register in register and mailbox access module；
When processor sends data by CAN kernel, processor is by the frame data of frame to be sent and its frame ID and frame
Mask is sent in mailbox by the mirror registers write-in in register and mailbox access module, sends the ID and frame ID phase of mailbox
Matching；In the CAN bus free time, the mailbox reading circuit of message processing module sends the frame data of mailbox to be sent and its ID to
In CAN kernel；Meanwhile the mailbox write circuit of message processing module updates mailbox in the status register in mailbox access module
Corresponding state position.
Further, after the mailbox write circuit of message processing module obtains mailbox access power, the reception of message processing module
Filter circuit judges whether to accept filter according to the mailbox control bit that accepts filter；When not needing to accept filter
When, the ID and mask of the frame data received and frame data are written and receive mailbox by CAN kernel, update phase in status register
Mode bit is answered, mailbox access is completed and receives data storage；When being accepted filter, CAN kernel will receive mailbox ID
It reads from mailbox with mask relevant bits and is matched with the ID of the frame data received, if two ID matchings, will receive
To ID, mask and data be stored in the mailbox, update in register and mailbox access module corresponding state position in status register,
It receives data storage to finish, does not visit again subsequent mailbox；If two ID are mismatched, continue to inquire next reception mailbox,
Until finding matching mailbox；If the ID and all ID for receiving mailbox that receive all are mismatched, data are deposited by configuring
Storage is in the last one mailbox.
Further, processor sends data by CAN kernel method particularly includes: processor is by frame data to be sent
And its ID, mask and control bit are posted based on the mirror image in upgrade demand partly or entirely write-in register and mailbox access module
Storage, then the mailbox write circuit of message processing module is after obtaining mailbox access power, the mailbox write circuit of message processing module
Updated mirror registers data are written in mailbox；When CAN kernel state monitoring module passes through the phase of CAN core register
When mode bit being answered to judge the CAN bus free time, the transmitting line of message processing module inquires all transmission request marks for sending mailbox
Will position, sequence of the mailbox reading circuit of message processing module according to mailbox number from small to large will successively send request flag position
The frame data and its ID of effective mailbox, which read and are sent in CAN kernel, carries out framing transmission, while message processing module
Mailbox write circuit updates corresponding state position in the status register in register and mailbox access module.
Further, in data during sending and receiving, processor is higher than information to the priority of the access of mailbox
Priority of the processing module to the access of mailbox.
Compared with prior art, the present invention at least has the following beneficial effects:
Date storage method of the present invention, can effectively avoid that SJA1000 chip is existing in use to be connect
It receives configuration change trouble, transmission configuring redundancy, ID and parses problem cumbersome and that reception FIFO capacity is small, specific manifestation are as follows:
(1) bus sends and receivees data and is stored separately, and the different frame of ID can be stored into different mailboxes, for one
It sends for mailbox, if sending ID, frame information without changing, only needs more new bit every time.
(2) for a reception mailbox, after received data are read by processor, processor can be deposited by mirror image
Device reconfigures its ID and mask, so that the mailbox can receive the data of new ID node.
(3) due to handling from the reception mailbox that the data that different nodes receive all can be stored in corresponding ID
Device can clearly know which node is data come from when reading data from mailbox, without carrying out ID decoding, after can reading back directly
Respective handling is carried out to data.
(4) frame data are stored using 128 mailboxes, each mailbox can store a frame partial data, it is complete can to store 128 frames
Data are bigger than SJA1000 memory capacity.
Detailed description of the invention
Fig. 1 is data storage circuitry structure chart provided in an embodiment of the present invention；
Fig. 2 is message processing module structure chart provided in an embodiment of the present invention；
Fig. 3 is register provided in an embodiment of the present invention and mailbox access module structure chart；
Fig. 4 is RAM access arbitration building-block of logic provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing.
Repetitive operation, reception ID parsing and reception FIFO capacity when in order to solve reception ID and mask configuration, send is small
The problem of, a kind of CAN controller data storage circuitry structure is as shown in Figure 1.This storage circuit by data storage cell and
Its access modules composition.The assembling that CAN kernel is used to generate CAN bit timing and meet CAN2.0 agreement to frame is conciliate
Analysis.Message processing module is mainly read from mailbox in the state of transmission for realizing the data transmission between CAN kernel and mailbox
It takes to send data and pass to CAN kernel and carries out framing transmission, the data storage received CAN kernel when reception is matched to ID
In mailbox.The configuration and access of register and mailbox access module for realizing processor to mailbox.Under reset mode, processor
Ram cell can directly be accessed.RAM access logic mainly realizes that transmission, reception and processor pass through receiving between mirror registers
It asks arbitration control when mailbox, avoids access conflict.128 mailboxes in RAM, storage 127bits has in each mailbox
Data are imitated, valid data include the frame data of eight bytes of data7-data0, frame ID, mask and other relevant bits.
Wherein, data storage cell is made of one piece of two-port RAM and one group of register.Ram cell capacity be 512 ×
32bits is divided into 128 mailboxes, and each mailbox memory space is 4 × 32bits, and mailbox is for storing the shielding of receiving frame ID, ID
The data of code and most 8 bytes.
Register in register group is divided into two classes, and one kind is mailbox mirror registers, it is another kind of be the control of each mailbox and
Status register.Mailbox mirror registers include ID mirror registers, ID mask off code mirror registers and data mirror registers,
Its definition defines identical with the data bit stored in mailbox.Mailbox mirror registers read mailbox for processor
The caching of data during write access, when processor reads data from mailbox, the data of reading are stored in mirror registers,
It is used for processor, when processor writes data into mailbox, mirror registers is first write data into, then by mailbox access mould
Block writes data into respective mailbox.It controls register and state controller to realize using one group 128 registers, for depositing
Storage includes interruption is enabled, frame data length, ID shield enabled, mailbox data effective marker, interrupt identification, send request flag etc.
Mailbox control and Status Flag, it is each to control a kind of control that mailbox is corresponded to status register or mode bit, register it is every
One corresponding with the corresponding positions of a mailbox.Processor realizes configuration and the condition monitoring to mailbox by this group of register.
Data storage cell access modules include message processing module, register and mailbox access module and RAM in Fig. 1
Three modules of access arbitration module.Message processing module realizes the data interaction between the kernel data buffer CAN and mailbox, by sending out
It send logic, receive logic and CAN kernel state monitoring module composition, structure is as shown in dotted line frame in Fig. 2.
When transmission, sending logic need to judge whether CAN bus is idle by CAN kernel state monitoring module, be with determination
It is no to send immediately；When reception, receiving logic need to judge whether to receive from bus by CAN kernel state monitoring module
One frame data.In short, CAN kernel state monitoring module be used for send and receive logic provide Current bus whether can send out
Data are sent, or whether have received data.
When reception (when this node receives data from bus), CAN kernel monitoring module is posted by the correlation in CAN kernel
After storage and interrupt flag bit judge that the success of CAN kernel receives a frame data from CAN bus；The deposit of message processing module
Device reading circuit reads data from the reception buffer of CAN kernel；Then the mailbox write circuit of message processing module is obtaining
Mailbox access power after, according to priority one by one access receive mailbox, wave reception filtering circuit using mailbox accept filter control bit judge
Whether accept filter；
If you do not need to accept filter, then the frame that the mailbox write circuit of message processing module will be received from bus
In data and its current reception mailbox of ID, mask write-in, while the mailbox write circuit of message processing module updates status register
Middle corresponding state position receives data storage and finishes, do not visit again subsequent mailbox；
It accepts filter if necessary, then the mailbox reading circuit of message processing module reads the ID and mask for receiving mailbox
Relevant bits, and the read ID and mask relevant bits for receiving mailbox are matched with the ID of the frame data received:
If two ID matching, the mailbox write circuit of message processing module is by the frame data received and its ID, mask
In the matched reception mailbox of write-in institute, while the mailbox write circuit of message processing module updates corresponding state position in register, connects
It receives data storage to finish, does not visit again subsequent mailbox.
If two ID are mismatched, the mailbox reading circuit of message processing module continues to read next reception mailbox, go forward side by side
Row matching, until finding matched mailbox；If the ID and all ID for receiving mailbox that receive are mismatched entirely, processor passes through
Preset configuration stores data in the last one mailbox, avoids loss of data.
When transmission (when this node sends data in bus), processor by ID, mask of frame to be sent, frame data and
Control bit, which is based on upgrading demand, is partly or entirely written mirror registers, and then message processing module mailbox write circuit is obtaining postal
After case access right, the mirror registers content of update is written in mailbox, mailbox data effective marker position and transmission request flag
Position position；When CAN kernel state monitoring module judges the CAN bus free time by the corresponding state position of CAN core register, then send out
Module is sent to inquire all transmission request flag positions for sending mailbox, the mailbox reading circuit of message processing module is according to mailbox
The mode of number from small to large, the frame data for sending the effective mailbox in request flag position and its ID successively read and be sent to
Framing transmission is carried out in CAN kernel, while the mailbox write circuit of message processing module updates corresponding state position in status register.
If bus is occupied, continue to monitor, waits its free time.
Fig. 3 gives register and mailbox access function structure chart, and register and mailbox access module include mailbox access
Module, mirror registers and other registers.Wherein, other registers include mailbox control register and mail box state deposit
Device, mailbox control configuration of the register for processor realization to mailbox, and mailbox status register is used for message processing module pair
The judgement of mail box state；Mailbox access module is for realizing processor by mirror registers to the dereference of mailbox.CAN control
After device processed enters operating mode, mailbox number and control information is written by controlling register to mailbox in processor, is deposited to mirror image
Device write-in is intended to that the corresponding ID, mask of frame, data and other relevant bits of the number mailbox are written, then mailbox access module can will belong to
It is automatically write in the corresponding area RAM of mailbox number in the configuration information of mailbox, while other control information bit write-in respective mailbox being compiled
Number control register.
Register and mailbox access module realize the information exchange between processor and mailbox, by mirror registers, control
Register and status register and mailbox access module composition, as shown in Figure 3.Mailbox access module establish mailbox number and
The mapping of mailbox address ram, processor specify mailbox number and relevant configuration number by configuration mirroring register and control register
According under the control of mailbox access module, the information in mailbox is read into corresponding registers by realization, or configuration data is led to
Register is crossed to be transmitted in the mailbox needed to configure and its corresponding control register.All mailboxes can be configured as needed to send out
It sending mailbox or receives mailbox, each mailbox can be used alone, and a frame data are stored, several mailboxes can also be together in series,
A FIFO is formed, multiframe data are stored.In the operational mode, each mailbox can be during idle time by flexible configuration again, change
The all or part of its ID, mask, data and control bit.
Fig. 4 gives RAM access arbitration function structure chart.RAM access arbitration module is for handling in message processing module
Receiving module, sending module and register and mailbox access module in mailbox access module, to mailbox access power arbitration.
To ensure that processor can access and configure to mailbox at any time, thus processor to its priority of the access of RAM compared with information
Processing module priority wants high.The priority of final RAM access arbitration module is followed successively by processor from high to low and writes logic, processing
Device reads logic, message processing module receives logic, message processing module sending logic.
Wherein RAM read-write and data include the enabled read-write data for being 32bits with bit wide of RAM read-write.Each module
(including the mailbox access in receiving module, sending module and the register and mailbox access module in processing message processing module
Module) to RAM initiate access before must judge whether ram port occupied, if unoccupied, carry out RAM access and will
RAM occupied state position position, resets after access, if ram port is occupied, after waiting ram port idle, according to
Arbitrated logic determines which module obtains RAM access right.
Embodiments of the present invention are expounded in conjunction with attached drawing above, but the present invention is not limited to above-mentioned specific reality
Mode is applied, above-mentioned specific embodiment is only schematical, and it is guiding, and not restrictive, do not departing from the present invention
Under the premise of spirit and scope, the present invention be will have various changes and improvements, these changes and improvements belong to claimed
In range.The scope of the present invention is defined by the appended claims and its equivalents.
Claims (10)
1. a kind of CAN controller data storage circuitry, which is characterized in that including data storage cell and access modules, institute
Stating data storage cell includes 128 mailboxes, and the access modules include message processing module, register and mailbox access mould
Block and RAM access arbitration module；Wherein,
The message processing module is for realizing the data interaction between the kernel data buffer CAN and mailbox；
The register and mailbox access module are for realizing the information exchange between processor and mailbox；
The RAM access arbitration module is used for when message processing module and register and mailbox access module access mailbox simultaneously
It is arbitrated, to control the access to mailbox.
2. a kind of CAN controller data storage circuitry as described in claim 1, which is characterized in that the information processing
Module includes mailbox reading circuit, mailbox write circuit, register reading circuit, register write circuit, wave reception filtering circuit and CAN kernel
State monitoring module；Wherein,
Mailbox reading circuit be used for reads receive mailbox ID and mask relevant bits, and by it is read reception mailbox ID and mask
Relevant bits are matched with the ID received；
Frame data and its ID, mask write-in that the mailbox write circuit is used to receive are current to be received in mailbox, is updated simultaneously
Corresponding state position in register；
The register reading circuit is used to read the state and data of CAN kernel status register；
The register write circuit is used to the data of CAN kernel mailbox is written；
The wave reception filtering circuit is used for when CAN kernel is in reception state, is filtered to the frame received, and will
Filter result is sent to mailbox write circuit；
The CAN kernel state monitoring module is for judging whether CAN bus is idle.
3. a kind of CAN controller data storage circuitry as described in claim 1, which is characterized in that the register and
Mailbox access module includes mirror registers, control and status register；Wherein,
The mirror registers are written and read the data in access process to mailbox for cache processor；
The control and status register are used to store control and the mode bit of mailbox, and the mailbox control and mode bit include:
Enabled, frame data length, ID is interrupted to shield enabled, mailbox data effective marker, interrupt identification and send request flag.
4. a kind of CAN controller data storage circuitry as claimed in claim 3, which is characterized in that the control and shape
State register includes 13 128 registers, configuration and condition monitoring for realizing processor to mailbox；Wherein, each
Register pair answers a kind of control bit or mode bit of mailbox.
5. a kind of CAN controller data storage circuitry as described in claim 1, which is characterized in that the data storage
Unit is one piece of two-port RAM, and the two-port RAM is divided into 128 mailboxes, the mailbox for store frame data, frame ID,
Mask and mailbox effective marker position, transmitting-receiving mailbox configurations position.
6. a kind of CAN controller data storage circuitry as described in claim 1, which is characterized in that the register and
In mailbox access module, all mailboxes are configured as needed to send mailbox or receive mailbox；In CAN controller operating mode
Under, dynamic configuration is carried out according to demand during idle time in mailbox, changes ID, mask, data and the control bit of mailbox.
7. a kind of storage method based on CAN controller data storage circuitry described in any one of claims 1-6, special
Sign is, comprising:
Establish the mapping between mailbox ID and mailbox address ram；
When CAN kernel receives data, message processing module reads frame data and its frame from the reception buffer of CAN kernel
ID and frame mask；Message processing module is after obtaining mailbox access power, and access receives mailbox one by one, and by frame data and frame
ID, frame mask write-in receive mailbox, and the ID and frame ID for receiving mailbox matches；Meanwhile the mailbox of message processing module is write
Circuit updates corresponding state position in the status register in register and mailbox access module；
When processor sends data by CAN kernel, processor leads to the frame data of frame to be sent and its frame ID and frame mask
The mirror registers write-in crossed in register and mailbox access module is sent in mailbox, the ID and frame ID phase for sending mailbox
Match；In the CAN bus free time, the mailbox reading circuit of message processing module sends the frame data of mailbox to be sent and its ID to
In CAN kernel；Meanwhile the mailbox write circuit of message processing module updates postal described in the status register in mailbox access module
The corresponding state position of case.
8. a kind of CAN controller date storage method as claimed in claim 7, which is characterized in that message processing module
Mailbox write circuit obtain mailbox access power after, the wave reception filtering circuit of message processing module accepts filter control bit according to mailbox
Judge whether to accept filter；
When not needing to be accepted filter, CAN kernel connects the ID and mask of the frame data received and frame data write-in
Mailbox is received, corresponding state position in status register is updated, complete mailbox access and receives data storage；
When being accepted filter, CAN kernel will receive mailbox ID and mask relevant bits read from mailbox and with reception
To the ID of frame data matched, if two ID matchings, are stored in the mailbox for ID, mask for receiving and data, update
Corresponding state position in status register in register and mailbox access module receives data storage and finishes, do not visit again subsequent postal
Case；If two ID are mismatched, continue to inquire next reception mailbox, until finding matching mailbox；If the ID received
It is all mismatched with all ID for receiving mailbox, stores data in the last one mailbox by configuring.
9. a kind of CAN controller date storage method as claimed in claim 7, which is characterized in that processor passes through CAN
Kernel sends data method particularly includes: frame data and its ID, mask to be sent and control bit are based on updating by processor
The mirror registers in register and mailbox access module are partly or entirely written in demand, and then the mailbox of message processing module is write
For circuit after obtaining mailbox access power, postal is written in updated mirror registers data by the mailbox write circuit of message processing module
In case；When CAN kernel state monitoring module judges the CAN bus free time by the corresponding state position of CAN core register, information
The transmitting line of processing module inquires all transmission request flag positions for sending mailbox, and the mailbox reading circuit of message processing module is pressed
According to the sequence of mailbox number from small to large, successively the frame data for sending the effective mailbox in request flag position and its ID are read concurrent
It is sent to progress framing transmission in CAN kernel, while the mailbox write circuit of message processing module updates register and mailbox access mould
Corresponding state position in status register in block.
10. a kind of CAN controller date storage method as claimed in claim 7, which is characterized in that in the reception of data
In transmission process, processor is higher than message processing module to the priority of the access of mailbox to the priority of the access of mailbox.
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| CN111650915A (en) * | 2019-10-14 | 2020-09-11 | 摩登汽车有限公司 | CAN bus control method and device, vehicle control unit, storage medium and vehicle |
| CN112118125A (en) * | 2020-08-05 | 2020-12-22 | 东风电驱动系统有限公司 | CAN message high load rate receiving method and system |
| CN113141288A (en) * | 2021-04-23 | 2021-07-20 | 北京航天发射技术研究所 | Mailbox message receiving and sending method and device of CAN bus controller |
| CN114417780A (en) * | 2021-12-16 | 2022-04-29 | 北京百度网讯科技有限公司 | State synchronization method and device, electronic equipment and storage medium |
| CN114979058A (en) * | 2022-06-30 | 2022-08-30 | 东风电驱动系统有限公司 | CAN multi-mailbox multiplexing processing method and system |
| CN115065572A (en) * | 2022-02-28 | 2022-09-16 | 西安电子科技大学 | CAN FD controller for vehicle-mounted electronic system |
| CN115460035A (en) * | 2022-08-08 | 2022-12-09 | 武汉海微科技有限公司 | File transceiving method, system, medium and device based on CAN controller |
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| CN114417780A (en) * | 2021-12-16 | 2022-04-29 | 北京百度网讯科技有限公司 | State synchronization method and device, electronic equipment and storage medium |
| CN114417780B (en) * | 2021-12-16 | 2022-11-01 | 北京百度网讯科技有限公司 | State synchronization method and device, electronic equipment and storage medium |
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| CN115065572B (en) * | 2022-02-28 | 2023-09-29 | 西安电子科技大学 | CAN FD controller for vehicle-mounted electronic system |
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