CN109656851A - A kind of multipath high-speed bus run and shared interface that the time is determining - Google Patents
A kind of multipath high-speed bus run and shared interface that the time is determining Download PDFInfo
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- CN109656851A CN109656851A CN201811347595.2A CN201811347595A CN109656851A CN 109656851 A CN109656851 A CN 109656851A CN 201811347595 A CN201811347595 A CN 201811347595A CN 109656851 A CN109656851 A CN 109656851A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0012—High speed serial bus, e.g. IEEE P1394
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/36—Arbitration
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Abstract
The multipath high-speed bus run and shared interface determined the invention discloses a kind of time, including multiple high-speed bus channel modules, channel control module, arbitration modules, host state machine module and shared interface.Each high-speed bus channel is interacted by unique shared interface with outside, and arbitration modules select high-speed bus channel according to fair arbitration algorithm and timeslice timing strategies, realizes that the data between multichannel, polymorphic type bus and shared interface are transmitted.The invention avoids the data transmission conflict problems of the corresponding interface in each channel, realize the high efficiency of transmission of multi-channel data, improve the utilization rate in high-speed bus channel, reduce the complexity of system application.Fair arbitration mechanism and timeslice timing strategies are taken simultaneously, improves data transmission efficiency and time determinability.
Description
Technical field
The multipath high-speed bus run and shared interface determined the present invention relates to a kind of time, particular for applied to space
The high-speed serial bus such as SpaceWire, SpaceFibre and RapidIO of environment take fair arbitration algorithm and timeslice fixed
When strategy, realize that the data between multichannel, polymorphic type bus and shared interface signal are transmitted, belong to the communications field.
Background technique
For space mission feature, it is desirable that used bussing technique has high transfer rate, low-power consumption, scalable, high
The features such as reliable.In carrying out bus circuit development process, should meet the needs of system is to high-property transmission, while also wanting simultaneous
Gu is easy to the system requirements such as Redundancy Design, low-power consumption.In the transmission of spaceborne data, it is to provide transmission reliability using channel redundancy
One of effective ways.
In addition, causing to carry out connecing for data exchange with bus circuit since space application has higher requirements to resource is occupied
Mouth resource is limited, to there are problems that interface and multibus interchannel data transmission conflict, needs to share using interface
The high efficiency of transmission of method realization multi-pass circuit-switched data.
Summary of the invention
Technical problem solved by the present invention is overcome the deficiencies in the prior art, proposes a kind of multipath high-speed that the time determines
Bus run and shared interface realize that the data between multichannel, polymorphic type bus and shared interface are transmitted.
The technical solution of the invention is as follows: a kind of multipath high-speed bus run and shared interface that the time is determining, including
Multiple high-speed bus channel modules, channel control module, arbitration modules, host state machine module and shared interface；
Each high-speed bus channel module is connect with a high-speed bus, and is controlled according to the state of high-speed bus by channel
Molding block sends read-write requests to arbitration modules；
Channel control module is selected according to the arbitration control signal of arbitration modules and the channel switching signal of host state machine module
Some high-speed bus channel module is selected to carry out data transmission with shared interface；
Arbitration modules are sent out according to the read-write requests of high-speed bus channel module to channel control module and host state machine module
Send arbitration control signal；When receiving channel pressure selection instruction, force selection instruction to channel control module according to channel
Arbitration control signal is sent with host state machine module；
Host state machine module sends read write command to shared interface according to external demand；Receive the arbitration control of arbitration modules
After signal processed, to channel control module sendaisle switching signal；
Shared interface realizes the high-speed bus currently chosen and external data exchange according to read write command；Outside receiving
Selection instruction is forced in channel, and is sent to arbitration modules.
High-speed bus channel module includes SpaceWire, SpaceFibre and RapidIO high-speed bus protocol module, energy
It is enough that corresponding high-speed bus protocol module is selected according to the high-speed bus type currently connected.
Read-write requests of the arbitration modules according to high-speed bus channel module, foundation fair arbitration algorithm and timeslice timing plan
Slightly, arbitration control signal is sent to channel control module and host state machine module.
The fair arbitration algorithm is as follows:
For each high-speed bus channel module, identical selection initial value is set；
When some high-speed bus channel module is selected to carry out data transmission with shared interface, corresponding selection is initial
Value subtracts 1；
When multiple high-speed bus channel modules send read-write requests simultaneously, arbitration modules are to above-mentioned high-speed bus channel mould
Initial value is descending is ranked up by selection for block, obtains arbitration control signal accordingly, the arbitration control signal is will be current
High-speed bus channel module is switched to the selection maximum high-speed bus channel module of initial value.
The timeslice timing strategies, which refer to, sets transmission time threshold value for each high-speed bus channel module, when current choosing
In the high-speed bus channel module actual transmissions time be more than transmission time threshold value when, arbitration modules according to according to fair arbitration calculate
Normal direction channel control module and host state machine module send arbitration control signal.
The channel control module includes channel selecting module and data conversion module；
Channel selecting module: it is selected according to the arbitration control signal of arbitration modules and the channel switching signal of host state machine module
Some high-speed bus channel module is selected to carry out data transmission with shared interface；
Data conversion module: the high-speed bus data currently chosen are converted to the data format of shared interface receiving；It will
The data format for currently high-speed bus being chosen to receive is converted to by the received external data of shared interface.
It further include register module, selection instruction is forced in the channel outside shared interface reception, and is sent to register mould
Block storage, while status information of the register module for modules in storage circuit.
The channel control module is cut in the channel of the arbitration control signal and host state machine module that receive arbitration modules
After changing signal, the status information received respectively to arbitration modules and host state machine module feedback, when host state machine module receives
To after the arbitration control signal of arbitration modules, the status information that is arrived to arbitration modules feedback reception.
Shared interface can support the access of 8,16 and 32 bit wide data.
The high-speed bus refers to that transmission rate is greater than the bus of 200Mbps.
Compared with the prior art, the invention has the advantages that:
(1) present invention supports a variety of high-speed bus agreements such as SpaceWire, SpaceFibre and RapidIO, is convenient for system
Flexible configuration bus type is carried out using as needed.
(2) the high-speed bus port number flexibly configurable that the present invention is supported, it is different logical convenient for being carried out according to different demands
The design of road number.
(3) fair arbitration mechanism is taken in the selection in high-speed bus channel of the present invention, and takes timeslice timing strategies, improves
Data transmission efficiency and time determinability.
(4) each high-speed bus channel of the present invention is interacted by unique shared interface with outside, is avoided each logical
The data transmission conflict problem of the corresponding interface in road, realizes the high efficiency of transmission of multi-channel data, it is logical to improve high-speed bus
The utilization rate in road reduces the complexity of system application.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of multipath high-speed bus run and shared interface；
Fig. 2 is the structural schematic diagram of channel control module；
Fig. 3 is the state diagram of host state machine module.
Specific embodiment
The present invention proposes a kind of multipath high-speed bus run and shared interface that the time is determining, particular for applied to space
The high-speed serial bus such as SpaceWire, SpaceFibre and RapidIO of environment take fair arbitration algorithm and timeslice fixed
When strategy, realize that the data between multichannel, polymorphic type bus and shared interface signal are transmitted.
As shown in Figure 1, the present invention includes high-speed bus channel module, channel control module, arbitration modules, host state machine mould
Block, shared interface control module and register module.
Wherein, each high-speed bus channel module is connect with a high-speed bus, and is passed through according to the state of high-speed bus
Channel control module sends read-write requests to arbitration modules, and high-speed bus refers to that transmission rate is greater than the bus of 200Mbps.At a high speed
Bus run module includes SpaceWire, SpaceFibre and RapidIO high-speed bus protocol module, can be according to currently connecting
The high-speed bus type connect selects corresponding high-speed bus protocol module.It, can be clever according to actual needs in specific example design
High-speed bus port number needed for customization living.
Channel control module is selected according to the arbitration control signal of arbitration modules and the channel switching signal of host state machine module
Some high-speed bus channel module is selected to carry out data transmission with shared interface.
Read-write requests of the arbitration modules according to high-speed bus channel module, foundation fair arbitration algorithm and timeslice timing plan
Slightly, arbitration control signal is sent to channel control module and host state machine module；When choosing is forced in the channel for receiving shared interface
When selecting instruction, selection instruction is forced to send arbitration control signal to channel control module and host state machine module according to channel.
Fair arbitration algorithm is as follows:
For each high-speed bus channel module, identical selection initial value is set；
When some high-speed bus channel module is selected to carry out data transmission with shared interface, corresponding selection is initial
Value subtracts 1；
When multiple high-speed bus channel modules send read-write requests simultaneously, arbitration modules are to above-mentioned high-speed bus channel mould
Initial value is descending is ranked up by selection for block, obtains arbitration control signal accordingly, the arbitration control signal is will be current
High-speed bus channel module is switched to the selection maximum high-speed bus channel module of initial value.
Timeslice timing strategies, which refer to, sets transmission time threshold value for each high-speed bus channel module, when what is currently chosen
The high-speed bus channel module actual transmissions time be more than transmission time threshold value when, arbitration modules according to according to fair arbitration algorithm to
Channel control module and host state machine module send arbitration control signal.
Host state machine module sends read write command to shared interface according to external demand；Receive the arbitration control of arbitration modules
After signal processed, to channel control module sendaisle switching signal；
When shared interface receives the reading instruction of host state machine module, the high speed by channel control module and currently chosen
Bus run module reads corresponding high-speed bus data, and is output to the outside；When shared interface receives host state machine module
Write command when, high-speed bus channel mould that shared interface will be chosen from external data by channel control module and currently
Corresponding high-speed bus is written in block；It receives the external channel sent and forces selection instruction, and export to arbitration modules and register
Module.
Selection instruction is forced in channel outside shared interface reception, and is sent to register module storage, while register
Status information of the module for modules in storage circuit.
Shared interface can support the access of 8,16 and 32 bit wide data.
As shown in Figure 1, channel control module is in the arbitration control signal and host state machine module for receiving arbitration modules
After channel switching signal, the status information received respectively to arbitration modules and host state machine module feedback, when host state machine mould
After block receives the arbitration control signal of arbitration modules, the status information that is arrived to arbitration modules feedback reception.
As shown in Fig. 2, channel control module includes channel selecting module and data conversion module.Channel selecting module: root
Some high-speed bus channel module is selected according to the arbitration control signal of arbitration modules and the channel switching signal of host state machine module
Carry out data transmission with shared interface；Data conversion module: the high-speed bus data currently chosen are converted into shared interface and are connect
The data format received；The data lattice for currently high-speed bus being chosen to receive will be converted to by the received external data of shared interface
Formula.
As shown in figure 3, host state machine module working condition is as follows:
1)idle
It operates after system reset or every time state machine when completing and enters idle state.If in this state host state machine module
It detects chip selection signal effectively, in read/write enable signal one effectively and smcsadr is identical as smcsid value, illustrate outside
The beginning that host operates host state machine module.If read operation, then state machine enters rd_data state, if write operation,
Then state machine enters wr_ready state.
2)wr_ready
In this state, answer signal is effective.If external host completes operation, state machine enters wr_data state, if
External host does not complete operation, then state machine enters wr_wait state.
3)wr_wait
This is wait state, as long as external host completes write operation, state machine advances to wr_data state.
4)wr_data
In this state, control logic module generates the read-write control signal for register, sending and receiving FIFO.It is external right
When this host state machine module carries out continuous read-write operation, if read signal is effective, state machine enters wr_rd_data state；If
Write signal is effective, and state machine enters wr_ready state, opens new write operation.For single operation, then state machine enters
To idle state.
5)wr_rd_data
When continuous operation of this state in order to carry out write-then-read, it is inserted into the wait state of a cycle, it is therefore an objective to complete
Register value with new, so available new data of read operation.State machine is not stopped in the state, enters directly into rd_
data。
6)rd_data
In this state, answer signal is effective, and reading data, which are latched, is sent to output end.State machine enters rd_wait state.
7)rd_wait
This is wait state, as long as external host completes read operation, state machine advances to rd_end state.
8)rd_end
In this state, show that current read operation has been completed, if not new operation requests, state machine enter ilde
State.State machine enters rd_data if having new read operation, if there is new write operation state machine to enter wr_ready
State.
The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the well-known technique of professional and technical personnel in the field.
Claims (10)
1. multipath high-speed bus run and shared interface that a kind of time determines, it is characterised in that: logical including multiple high-speed buses
Road module, channel control module, arbitration modules, host state machine module and shared interface；
Each high-speed bus channel module is connect with a high-speed bus, and controls mould by channel according to the state of high-speed bus
Block sends read-write requests to arbitration modules；
Channel control module selects certain according to the arbitration control signal of arbitration modules and the channel switching signal of host state machine module
A high-speed bus channel module carries out data transmission with shared interface；
Arbitration modules are sent secondary according to the read-write requests of high-speed bus channel module to channel control module and host state machine module
Cut out control signal；When receiving channel pressure selection instruction, force selection instruction to channel control module and master according to channel
State machine module sends arbitration control signal；
Host state machine module sends read write command to shared interface according to external demand；Receive the arbitration control letter of arbitration modules
After number, to channel control module sendaisle switching signal；
Shared interface realizes the high-speed bus currently chosen and external data exchange according to read write command；Channel outside receiving
Selection instruction is forced, and is sent to arbitration modules.
2. multipath high-speed bus run and shared interface that a kind of time according to claim 1 determines, it is characterised in that:
High-speed bus channel module includes SpaceWire, SpaceFibre and RapidIO high-speed bus protocol module, can be according to working as
The high-speed bus type of preceding connection selects corresponding high-speed bus protocol module.
3. a kind of time determines according to claim 1 multipath high-speed bus run and shared interface, it is characterised in that: secondary
Module is cut out according to the read-write requests of high-speed bus channel module, according to fair arbitration algorithm and timeslice timing strategies, Xiang Tongdao
Control module and host state machine module send arbitration control signal.
4. a kind of time determines according to claim 3 multipath high-speed bus run and shared interface, it is characterised in that: institute
It is as follows to state fair arbitration algorithm:
For each high-speed bus channel module, identical selection initial value is set；
When some high-speed bus channel module is selected to carry out data transmission with shared interface, corresponding selection initial value subtracts
1；
When multiple high-speed bus channel modules send read-write requests simultaneously, arbitration modules press above-mentioned high-speed bus channel module
Initial value is descending is ranked up for selection, obtains arbitration control signal accordingly, and the arbitration control signal is will current high speed
Bus run module is switched to the selection maximum high-speed bus channel module of initial value.
5. a kind of time determines according to claim 3 multipath high-speed bus run and shared interface, it is characterised in that: institute
State timeslice timing strategies refer to for each high-speed bus channel module set transmission time threshold value, when the high speed currently chosen is total
When the line passage module actual transmissions time is more than transmission time threshold value, arbitration modules are controlled according to according to fair arbitration algorithm to channel
Molding block and host state machine module send arbitration control signal.
6. a kind of time determines according to claim 1 multipath high-speed bus run and shared interface, it is characterised in that: institute
Stating channel control module includes channel selecting module and data conversion module；
Channel selecting module: certain is selected according to the channel switching signal of the arbitration control signal of arbitration modules and host state machine module
A high-speed bus channel module carries out data transmission with shared interface；
Data conversion module: the high-speed bus data currently chosen are converted to the data format of shared interface receiving；It will pass through
The received external data of shared interface is converted to the data format for currently choosing high-speed bus to receive.
7. a kind of time determines according to claim 1 multipath high-speed bus run and shared interface, it is characterised in that: also
Including register module, selection instruction is forced in the channel outside shared interface reception, and is sent to register module storage, simultaneously
Status information of the register module for modules in storage circuit.
8. a kind of time determines according to claim 1 multipath high-speed bus run and shared interface, it is characterised in that: institute
Channel control module is stated after the channel switching signal of the arbitration control signal and host state machine module that receive arbitration modules, point
The status information not received to arbitration modules and host state machine module feedback, when host state machine module receives arbitration modules
After arbitration control signal, the status information that is arrived to arbitration modules feedback reception.
9. a kind of time determines according to claim 1 multipath high-speed bus run and shared interface, it is characterised in that: altogether
The access of 8,16 and 32 bit wide data can be supported by enjoying interface.
10. a kind of time determines according to claim 1 multipath high-speed bus run and shared interface, it is characterised in that:
The high-speed bus refers to that transmission rate is greater than the bus of 200Mbps.
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| CN201811347595.2A CN109656851B (en) | 2018-11-13 | 2018-11-13 | System with time determination and comprising multiple high-speed bus channels and shared interface |
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| CN201811347595.2A CN109656851B (en) | 2018-11-13 | 2018-11-13 | System with time determination and comprising multiple high-speed bus channels and shared interface |
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| CN109656851B CN109656851B (en) | 2020-10-16 |
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| CN113051198A (en) * | 2021-03-08 | 2021-06-29 | 惠州Tcl移动通信有限公司 | Mobile terminal module processing method and device, mobile terminal and storage medium |
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| CN114880258A (en) * | 2022-05-26 | 2022-08-09 | 重庆长安汽车股份有限公司 | Intelligent driving interaction arbitration method, system, vehicle and storage medium |
| CN114880258B (en) * | 2022-05-26 | 2024-05-07 | 重庆长安汽车股份有限公司 | Intelligent driving interaction arbitration method, system, vehicle and storage medium |
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