CN115037413A

CN115037413A - SpaceFibre protocol-oriented standardized configurable multi-rate switching system and method

Info

Publication number: CN115037413A
Application number: CN202210577254.4A
Authority: CN
Inventors: 郑静雅; 安军社; 江源源
Original assignee: National Space Science Center of CAS
Current assignee: National Space Science Center of CAS
Priority date: 2022-05-25
Filing date: 2022-05-25
Publication date: 2022-09-09
Anticipated expiration: 2042-05-25
Also published as: CN115037413B

Abstract

The invention relates to a standardized configurable multi-rate switching system and a method facing a SpaceFibre protocol, wherein the system comprises a standardized AXI-Lite interface, a synchronization module, a rate switching module, a configuration module, a master control module, a slave control module, a write cycle control module, a read cycle control module, a state recording module, a timer, a retry number counter, an address selection module and a Xilinx GTX transceiver module. The method adopts master-slave cooperative control to complete all read operations and write operations of the rate switching request, thereby generating a rate switching mark; the synchronization module generates a rate switching request signal when detecting the change of the rate switching instruction and outputs a rate mode signal; the configuration module waits to be written into the Xilinx GTX transceiver according to the corresponding relation between the rate mode signal and the attribute to be modified according to the rate switching instruction; and the rate switching module generates the current line rate according to the rate switching mark and the rate mode signal and reports the current line rate to the processor core through the standardized AXI-Lite interface.

Description

Standard configurable multi-rate switching system and method for SpaceFibre protocol

Technical Field

The invention belongs to the technical field of spacecraft high-speed data transmission, and particularly relates to a spaceFibre-oriented standardized configurable multi-rate switching system and method.

Background

The increasing difficulty of space exploration tasks puts new demands on the amount and rate of data transmission between payloads. The SpaceFibre protocol is a new generation of high-speed serial bus proposed by the European space office, the highest single-channel speed can reach 6.25Gbps, a single physical link supports 16 physical channels at most, and the requirements of high-speed and large-scale data transmission among effective loads are effectively met. The SpaceFibre interface implementation scheme adopts a Xilinx GTX transceiver to realize the whole functions of a physical layer and partial functions of a channel layer in a protocol.

In the prior art, the SpaceFibre interface only supports a single transmission rate and does not support dynamic configuration of the interface rate, and the rate switching process can only be completed by complicated steps of reconfiguring a GTX transceiver, recompiling, re-realizing, re-loading and the like, so that the problems of significant increase of development cost and significant reduction of user friendliness are caused.

Disclosure of Invention

In order to solve the above problems, the invention provides a standardized configurable multi-rate switching system and method facing to the SpaceFibre protocol.

The invention provides a standardized configurable multi-rate switching system facing a SpaceFibre protocol, which is connected with a processor core through a standardized AXI-Lite interface, and is characterized by comprising the following components: the device comprises a master control module, a slave control module, a write cycle control module, a read cycle control module, a configuration module, a synchronization module, a rate switching module and a Xilinx GTX transceiver;

the main control module is used for outputting a switching rate mark after completing all read/write operations of the rate switching request so as to realize the rate switching of the processor core;

the slave control module is used for carrying out single read/write operation on the rate switching request and indicating the completion and failure of the single read/write operation so as to enter the next read/write operation or carry out the read/write operation again;

the read cycle control module is used for generating a read address required by the slave control module when the slave control module carries out single read operation and an attribute read value required by the write cycle control module, and generating a read cycle completion mark after the slave control module completes all read operations;

the write cycle control module is used for generating write addresses and write data required by the slave control module during single write operation, and generating a write cycle completion mark after the slave control module completes all write operations;

the standardized AXI-Lite interface receives a rate switching instruction from a processor core and transmits the rate switching instruction to a synchronization module, and the synchronization module is used for synchronizing a rate switching instruction signal in the system clock domain; if the synchronous module detects that the rate switching instruction changes, a rate switching request signal is generated; the rate switching request signal and an initialization completion flag signal from the Xilinx GTX transceiver jointly form a start flag signal of the main control module; the synchronization module also outputs a rate mode signal to the configuration module for subsequent writing into the Xilinx GTX transceiver;

the configuration module is used for waiting for writing data written into the Xilinx GTX transceiver according to the corresponding relation between the rate mode and the attribute to be modified according to the rate mode signal;

the rate switching module is used for generating a current line rate according to the rate switching flag signal and the rate mode signal and reporting the current line rate to the processor core through a standardized AXI-Lite interface;

the Xilinx GTX transceiver is used for modifying attributes by adopting a read-modify-write-back mode and generating a drprdy signal so that the slave control module, the read cycle control module or the write cycle control module respectively sends a single-operation completion mark, a read cycle completion mark or a write cycle completion mark to the master control module.

As one of the improvements of the above technical solution, the main state machine of the main control module includes an idle state, a check state, a read wait state, a NEXTR state, a write wait state, a NEXTW state, a rate switch state, a reset state, and a retry state, and is used to control read-write operation, state update, and state recording of the entire system;

when the main control module starts to operate, the main state machine enters a check state from an idle state; the main state machine can enter a reading state unconditionally when in a checking state; in a reading state, the main state machine enters a reading waiting state unconditionally, and a reading process flag signal is set; if the master state machine receives the set single operation completion signal from the slave state machine, entering a NEXTR state, otherwise, still being in a read waiting state; when the read cycle completion flag is detected to be set, the read cycle completion flag indicates that all read operations of the current rate switching are completed, and the main state machine enters a write-in state in a NEXTR state; if the main state machine does not detect that the reading cycle completion flag is set in the NEXTR state, the main state machine enters the reading state again and carries out the next single reading operation; entering a writing waiting state unconditionally in a writing state; if the main state machine receives the single operation completion signal, the main state machine enters a NEXTW state from a write-in waiting state, otherwise, the main state machine is still in the write-in waiting state; when the main state machine receives a valid (valid means high level, binary 1) write cycle completion mark, the main state machine enters a rate switching state, otherwise, the main state machine enters a write-once state again, and a new round of single write operation is started; the main state machine directly enters a reset state from a rate switching state, and the reset state enters an idle state unconditionally; although some states are unconditionally entered into the next state, the output of each state is different; the unconditional entry to the next state is set primarily to complete a series of operations in sequence at different steps to ensure that each operation is completed.

If the master state machine receives a single operation failure signal from the slave state machine in a read waiting state or a write waiting state, the master state machine enters a retry state; in a retry state, if the retry times exceed the limit, the main state machine enters an idle state; and if the retry times do not exceed the limit and the reading process mark is valid, the main state machine enters a reading state from a retry state, otherwise, the main state machine enters a writing state.

As one improvement of the above technical solution, the slave state machine of the slave control module includes a START (DRP _ START) state, a DRP _ READ state, a DRP _ WAIT state, a DRP _ WRITE state, a DONE (DRP _ DONE) state, and an error handling (DRP _ ERR) state; when receiving a slave state machine READ enable signal from a master state machine, the slave state machine enters a DRP _ READ state; when a slave state machine WRITE enable signal from a master state machine is received, the state machine enters a DRP _ WRITE state; entering a DRP _ WAIT state unconditionally in a DRP _ READ state and a DRP _ WRITE state; in the DRP _ WAIT state, if receiving a drprdy signal from the state machine, entering a completion state, if receiving a waiting overtime signal from the state machine, entering an error processing state, otherwise, the slave state machine is still in the DRP _ WAIT state; the slave state machine unconditionally enters the start state in the completion state.

As an improvement of the above technical solution, the system further includes: the device comprises an address selection module, a state recording module, a timer and a retry number counter;

the address selection module is used for generating an address signal transmitted to the Xilinx GTX transceiver; when the reading process mark is effective, the address selection module selects a reading address as a drpaddr signal; otherwise, the module selects the write address as an output signal;

the timer is used for timing the DRP _ WAIT state; when receiving an effective slave control clearing signal or a master control clearing signal, clearing the timer; when no valid clear signal is detected, the timer is incremented to a single operation wait upper limit; the single operation wait upper limit is configured by a processor core through a standardized AXI-Lite interface; after the upper limit is reached, the timer sets a waiting overtime signal and transmits the signal to the slave control module;

the retry number counter is used for counting the retry number of the main state machine; when receiving the signal of clearing retry times, the counter is cleared; when receiving the retry number increasing signal, the counter is incremented; when the upper limit of the retry times is counted, the retry times counter sets a retry times over-limit mark and transmits the retry times over-limit mark to the main state machine; the master state machine receives the retry number overrun mark and transfers the retry state to an idle state; the retry number upper limit is configured by the processor core through a standardized AXI-Lite interface;

the state recording module is used for indicating the state of rate switching, and setting a busy signal when the system is in the process of rate switching; when receiving the effective busy clearing signal, the state recording module clears the busy state; when receiving the effective busy state setting signal, the state recording module raises the busy state; when the system is in a busy state, data in the transceiver is invalid through Xilinx GTX; when receiving an operation failure signal from the master state machine, the state recording module outputs an effective switching failure mark and reports the effective switching failure mark to the processor core through the standardized AXI-Lite interface.

As one improvement of the above technical solution, when the main state machine is in an idle state, the write cycle clear signal is set and used to clear the number of write cycles of the write cycle control module; the reading period clearing signal is set and is used for clearing the number of reading periods of the reading period control module; a clear retry number signal is set and transmitted to a retry number counter; generating a master control clearing signal for clearing the timer;

when the main state machine is in an idle state and the next state is still in the idle state, the busy state clearing signal is set and transmitted to the state recording module for canceling the busy state; when the main state machine is in an idle state and the next state is a check state, the busy state signal is set and transmitted to the state recording module to mark the start of the busy state; meanwhile, setting a maximum reading period signal and a maximum writing period signal according to a rate mode; the maximum write cycle number and the maximum read cycle number are respectively used for the total write cycle number required by the write cycle control module and the total read cycle number required by the read cycle control module;

when the main state machine is in a reading state, the slave state machine reading enabling signal is set and is used for transferring the slave state machine from a starting state to a DRP _ READ state; in the read state of the master state machine, the read process flag signal is set.

When the main state machine is in a reading waiting state, the main state machine still sets a reading process mark;

when the main state machine is in a NEXTR state, setting a reading period increasing signal to be used for increasing the number of reading periods in the reading period control module so as to control reading addresses and reading data; in this state, the master state machine also sets the read process flag signal;

when the main state machine is in a writing state, the main state machine sets a reading cycle clearing signal to clear the number of reading cycles; meanwhile, setting a WRITE enable signal of the slave state machine transfers the working state of the slave state machine from the starting state to the DRP _ WRITE state;

when the main state machine is in a NEXTW state, the main state machine sets a write cycle increasing signal for controlling the increment of the number of write cycles and further controlling the write address and write data;

when the main state machine is in a rate switching state, a rate switching flag signal is set, and the rate switching flag signal is transmitted to a rate switching module to update a current line rate value;

when the main state is in a reset state, the main state machine sets a reset signal of the converter and transmits the reset signal to the GTX transceiver;

when the main state machine is in a retry state and the retry times exceed the upper limit, setting an operation failure mark and transmitting the operation failure mark to a state recording module; at the same time, the master state machine sends a master clear signal for clearing the timer value and a set retry number increment signal for accumulation of retry numbers.

As one improvement of the above technical solution, when the slave state machine enters a DRP _ READ state or a DRP _ WRITE state from an idle state, the slave control clear signal is set and transmitted to the timing module; in the DRP _ READ state, the slave state machine pulls up the drpen signal and the low drpwe signal according to the READ sequence to perform a single DRP READ operation; in the DRP _ WRITE state, the slave state machine sets a drpen signal and sets a drpecewe signal according to the WRITE time sequence; the writing address is a 9-bit drpaddr signal, the writing data is a 16-bit drpdh signal, and the two signals are respectively generated by an address selection module and a writing period control module; when the slave state machine is in a completion state, setting a single-operation completion signal and transmitting the signal to the master control module; when receiving the single operation completion signal and setting, the main state machine enters a NEXTR state from a reading waiting state or enters a NEXTW state from a writing waiting state; in an error processing state, the slave state machine sets a single operation failure mark and transmits the single operation failure mark to the master state machine; the master state machine enters a retry state if it is in a read wait state or a write wait state.

As one improvement of the above technical solution, when a read cycle clear signal from a master state machine is received, the read cycle control module clears a read cycle count; when receiving a valid read cycle increasing signal of the main state machine, the read cycle control module starts to count the read cycles; when the reading period counts to the maximum reading period signal, the reading period control module sets a reading period completion mark for the main state machine to use, indicates that all reading operations of the current rate switching are completed, and the main state machine enters a writing state from a NEXTR state; at each read cycle, when the read process flag is active and the drprdy signal is active, the read cycle control module reads the drpdo value from the Xilinx GTX transceiver and records the corresponding attribute value.

As one improvement of the above technical solution, according to attribute write data input by a configuration module, a write control module outputs a drpdi signal to a Xilinx GTX transceiver according to a write cycle to modify its corresponding attribute; when an effective write cycle clearing signal is received, the write cycle control module clears the write cycle count; when receiving an effective write cycle increasing signal, the write cycle control module starts to count the write cycle; when the write cycle counts to the maximum write cycle signal, the write cycle control module sets a write cycle completion flag for the main state machine to use, and indicates that all write operations of the rate switching are completed; the main state machine receives the signal and then enters a rate switching state from a NEXTW state, otherwise, the main state machine continues to enter a write-in state to carry out read operation again.

As an improvement of the above technical solution, the Xilinx GTX transceiver first needs to read attribute data of a corresponding configuration space of the transceiver, then transmits the read attribute data to the read cycle control module, and writes back the configuration space of a corresponding address after the write cycle control module is modified.

The invention also provides a standardized configurable multi-rate switching method facing the SpaceFibre protocol based on the system, which receives a rate switching instruction sent by a processor core through the standardized AXI-Lite interface and transmits the rate switching instruction to a synchronization module; the synchronization module synchronizes the rate switching instruction signal in the system clock domain to keep the integrity of the signal and generate a rate switching request signal; the speed switching request signal and an initialization completion flag signal from the Xilinx GTX transceiver jointly form a start flag signal of the main control module;

after receiving the start mark signal, the master control module sends a read enable signal to the slave control module and sequentially sends a read cycle clearing signal, a read cycle increasing signal and a maximum read cycle signal to the read cycle control module respectively; after receiving the read enable signal from the control module, sequentially performing read operation; the read cycle control module generates a read address required by the slave control module when the slave control module carries out single read operation; the Xilinx GTX transceiver firstly reads attribute data of a corresponding configuration space of the Xilinx GTX transceiver and then transmits the read attribute data to the read cycle control module; writing back the configuration space of the corresponding address after the write cycle control module is modified; when a reading period clearing signal from the main state machine is received, the reading period control module clears the reading period count; when receiving a valid read cycle increasing signal of the main state machine, the read cycle control module starts to count the read cycles; when the reading period counts to the maximum reading period signal, the reading period control module sets a reading period completion mark for the main state machine to use;

after receiving the read cycle completion mark, the master control module sends a write enable signal to the slave control module and sequentially sends a write cycle clearing signal, a write cycle increasing signal and a maximum write cycle signal to the write cycle control module respectively;

the write cycle control module generates write addresses and write data required by the slave control module during single write operation; when a valid write cycle clear signal is received, the module clears the write cycle count; when a valid write cycle increment signal is received, the module starts counting write cycles; when the write cycle counts to the maximum write cycle signal, the module sets a write cycle completion flag for the use of the master state machine;

and after receiving the write cycle completion mark, the main control module generates a rate switching mark signal and transmits the rate switching mark signal to the rate switching module to update the current line rate value, so that rate switching is realized.

The invention provides a hardware architecture of a rate switching system, and realizes the function of dynamically adjusting the rate of a SpaceFibre transmission system; the invention adopts a standardized interface to configure the operation speed; the configuration module of the invention automatically matches the attribute parameters of the GTX transceiver according to the target rate and the current rate; the invention adopts a master-slave cooperative control strategy to complete rate switching.

The invention can realize that the AXI-Lite standard interface dynamically configures the GTX transceiver to different rates, has simpler implementation steps, reduces the development complexity and the design difficulty, and improves the rate switching efficiency.

Drawings

FIG. 1 is a block diagram of the architecture of the system of the present invention;

FIG. 2 is a block diagram of the main control module structure of the present invention;

FIG. 3 is a block diagram of the slave control module structure according to the present invention.

Detailed Description

The technical scheme provided by the invention is further illustrated by combining the following embodiments.

As shown in fig. 1, the system is composed of a standardized AXI-Lite interface, a synchronization module, a rate switching module, a configuration module, a master control module, a slave control module, a write cycle control module, a read cycle control module, a state recording module, a timer, a retry number counter, an address selection module, and a Xilinx GTX transceiver module.

Standardized AXI-Lite interface

The standardized AXI-Lite interface is responsible for the communication of the processor core and the rate switching system. The interface receives the speed switching command and transmits the speed switching command to the synchronous module, receives the single operation waiting upper limit signal and transmits the single operation waiting upper limit signal to the timer, and receives the retry number upper limit signal and transmits the retry number upper limit signal to the retry number counter. The interface also transmits a current line rate and a handoff failure signal to the processor core.

Synchronization module

The synchronization module synchronizes the rate switch command signal in the clock domain of the system to maintain the integrity of the signal. If the module detects that the rate mode changes, a rate switching request signal is generated. This signal, together with the initialization completion flag signal from the GTX transceiver, constitutes the start flag signal for the master control module. In addition, the synchronization module outputs a rate mode signal to the configuration module for subsequent writing to the Xilinx GTX transceiver.

Rate switching module

And the rate switching module generates the current line rate according to the rate switching mark signal and the rate mode signal and reports the current line rate to the processor core through the standardized AXI-Lite interface. The corresponding relationship between the rate mode signals with different numbers and the rate switching process is shown in table 1. The SpaceFibre protocol supports seven transmission rates, 1Gbps, 1.25Gbps, 2Gbps, 2.5Gbps, 3.125Gbps, 5Gbps and 6.25 Gbps.

TABLE 1

Configuration module

The configuration module generates an attribute write-in value to be written in the Xilinx GTX transceiver according to the corresponding relationship between the rate mode signal and the attribute to be modified shown in the table 2, wherein the table comprises the corresponding relationship between the rate mode and the attribute to be modified. Table 2 details three aspects of the attribute name of the attribute to be modified, before modification of the attribute value, and after modification of the attribute value. And the configuration module transmits the generated attribute write value signal to the write cycle control module, and the write cycle control module writes the attribute write value signal into the GTX transceiver.

TABLE 2

Master control module

The main control module is mainly composed of a main state machine, and the state machine is used for controlling read-write operation, state updating and state recording of the whole system. Referring to fig. 2, the state transition diagram of the state machine is mainly divided into 11 states, i.e., idle state, check state, read wait state, NEXTR state, write wait state, NEXTW state, rate switch state, reset state, and retry state. And when the starting mark is detected to be set, the main state machine enters a checking state from an idle state. The master state machine unconditionally enters the read state when verifying the state. In the read state, the main state machine unconditionally enters a read wait state. The NEXTR state is entered if the master state machine receives a single operation complete signal from the slave state machine that has been set, otherwise it is still in the read wait state. When the read cycle completion flag is detected to be set, it indicates that all read operations of the current rate switching have been completed, and the main state machine enters a write state in the NEXTR state. And if the main control state machine does not detect that the read cycle completion flag is set in the NEXTR state, the main control state machine enters the read state again and carries out the next single read operation. The write state unconditionally enters a write wait state. If the master state machine receives a single operation done signal that is set from the slave state machine, it indicates that the slave state machine has completed a single DRP write operation. At this time, the main state machine enters the NEXTW state from the write wait state, otherwise the state of the main state machine does not change. When the main state machine receives the effective writing cycle completion mark, all writing cycles of the rate switching are completely completed. And the main state machine enters a rate switching state, otherwise, enters a write-once state, and starts a new round of write-once operation. The main state machine directly enters a reset state from a rate switching state, and the reset state unconditionally enters an idle state. To maintain the stability of the system, an over time mechanism is added to the master slave state machine. If the master state machine receives a single operation failure signal from the slave state machine in either the read wait state or the write wait state, the master state machine enters a retry state. In the retry state, if the retry number exceeds the limit, the master state machine enters an idle state. If the retry times do not exceed the limit and the read process flag is valid, the master state machine enters the read state from the retry state, otherwise the master state machine enters the write state.

When the main state machine is in an idle state: the write cycle clear signal is set and is used for clearing the number of write cycles of the write cycle control module; the reading period clearing signal is set and is used for clearing the number of reading periods of the reading period control module; a clear retry number signal is set and transmitted to a retry number counter; generating a master clear signal for timer clearing.

When the main state machine is in an idle state and the next state is still in the idle state, the busy state clearing signal is set and transmitted to the state recording module for canceling the busy state. When the master state machine is in an idle state and the next state is a check state, the busy state signal is set and transmitted to the state recording module for marking the start of the busy state. At this time, it is also necessary to set the maximum read cycle signal and the maximum write cycle signal according to the rate mode. The maximum number of write cycles and the maximum number of read cycles are respectively used for the total number of write cycles required by the write cycle control module and the total number of read cycles required by the read cycle control module.

When the master state machine is in the READ state, the slave state machine READ enable signal is set for transferring the slave state machine from the start state to the DRP _ READ state. In the read state of the master state machine, the read process flag signal is set. In the read wait state, the master state machine still sets the read process flag.

The main state machine sets a read cycle increase signal in the NEXTR state for incrementing the number of read cycles in the read cycle control module to control the read address and read data. In this state, the master state machine also sets the read process flag signal.

In the write state, the main state machine sets the read cycle clear signal for clearing the number of read cycles. Meanwhile, setting the slave state machine WRITE enable signal transfers the working state of the slave state machine from the starting state to the DRP _ WRITE state. In the NEXTW state, the main state machine asserts a write cycle increase signal for controlling the incrementing of the number of write cycles, and thus the write address and write data.

In the rate switch state, a rate switch flag signal is set, which is transmitted to the rate switch module to update the current line rate value. In the reset state, the master state machine sets a transition piece reset signal and transmits to the GTX transceiver.

If the main state machine exceeds the retry time upper limit in the retry state, setting an operation failure mark and transmitting the operation failure mark to the state recording module. At this point, the master state machine issues a master clear signal for clearing the timer value and a bit retry number increment signal for accumulation of the retry number.

Read cycle control module

The read cycle control module generates a read address required when the control module performs a single read operation and an attribute read value required by the write cycle control module. The GTX transceiver uses a read-modify-write-back mode to modify the attribute, so that after the attribute to be modified is clear, the attribute data of the corresponding configuration space of the GTX transceiver needs to be read first, and then the read attribute data is transmitted to the write cycle control module. And after the write cycle control module is modified, writing back the configuration space of the corresponding address. And when a read cycle clearing signal from the main state machine is received, the read cycle control module clears the read cycle count. When receiving the effective reading period increasing signal of the main state machine, the reading period control module starts to count the reading period. When the reading period counts to the maximum reading period signal, the module sets a reading period completion flag for the main state machine to use, indicates that all reading operations of the current rate switching are completed, and the main state machine enters a writing state in a NEXTR state. Different read cycles represent reading different attributes as shown in table 3. In each read cycle, when the read process flag is valid and the drprdy signal is valid, the read cycle control module reads the drpdo value from the GTX transceiver and records the corresponding attribute value. The attribute read value recorded by the module is output to the write cycle control module. The reading process mark can effectively avoid the error reading operation caused by the response of the writing operation.

TABLE 3

Write cycle control module

The write cycle control block generates a write address and write data drpdi required for a single write operation from the control block. The module clears the write cycle count when a valid write cycle clear signal is received. When a valid write cycle increment signal is received, the module begins counting write cycles. When the write cycle counts to the maximum write cycle signal, the module sets a write cycle completion flag for the master control state machine to use, and indicates that all write operations of the current rate switching are completed. The main state machine receives the signal and then enters a rate switching state from a NEXTW state, otherwise, the main state machine continues to enter a write state to carry out read operation again. As shown in table 4, different write cycles represent different modification properties. Correspondingly, the write data drpdi of different write cycles is also different, and the write data is composed of the attribute write value generated by the configuration module and the attribute read value generated by the read cycle control module.

TABLE 4

Write cycle	Write back attribute names	Write back attribute address
			0	CPLL_FBDIV_45/CPLL_FBDIV	0x5E
1	TXOUT_DIV/RXOUT_DIV	0x88
			2	RXCDR_CFG_DRPADDR	0xA8
3	RXCDR_CFG_DRPADDR	0xA9
			4	RXCDR_CFG_DRPADDR	0xAA
5	RXCDR_CFG_DRPADDR	0xAB
			6	RXCDR_CFG_DRPADDR	0xAC

Address selection module

The address selection module is used for generating an address signal transmitted to the GTX transceiver. When the read process flag is valid, the address selection module selects the read address as the drpaddr signal. Otherwise, the module selects the write address as the output signal.

Slave control module

The slave control module is mainly composed of a slave control state machine. As shown in fig. 3, the state transition diagram of the state machine is mainly divided into six states, i.e., a start state, a DRP _ READ state, a DRP _ WAIT state, a DRP _ WRITE state, a complete state, and an error handling state. The state is started. When receiving a slave state machine READ enable signal from a master state machine, the state machine enters a DRP _ READ state; when a slave state machine WRITE enable signal is received from the master state machine, the state machine enters the DRP _ WRITE state. The DRP _ READ state and DRP _ WRITE state unconditionally enter the DRP _ WAIT state. In the DRP _ WAIT state, the slave state machine enters a completion state if receiving a drprdy signal, enters an error handling state if receiving a WAIT timeout signal, and remains in the DRP _ WAIT state otherwise. The slave state machine may unconditionally enter the start state in the done state.

When the slave state machine enters a DRP _ READ state or a DRP _ WRITE state from an idle state, the slave control clearing signal is set and transmitted to the timing module. In the DRP _ READ state, the slave state machine pulls up the drpen signal and the drpwe signal according to the READ timing to perform a single DRP READ operation. In the DRP _ WRITE state, the slave state machine sets the drpen signal and sets the drpewe signal according to the WRITE timing. The write address is a 9-bit drpaddr signal, the write data is a 16-bit drpdh signal, and the two signals are respectively generated by the address selection module and the write cycle control module. When the slave state machine is in the completion state, a single operation completion signal is set and transmitted to the master control module for indicating the completion of a single DRP operation (the single DRP operation refers to a single read operation or a single write operation). When the signal is received and set, the master state machine enters the NEXTR state from the read wait state or the NEXTW state from the write wait state. In the error handling state, the slave state machine sets the single operation failure flag and transmits it to the master state machine. If the master state machine is in the read waiting state or the write waiting state at this time, the master state machine enters a retry state.

State recording module

The state recording module is used for indicating the state of rate switching, and the system sets a busy signal in the process of rate switching. When receiving the effective busy clearing signal, the state recording module clears the busy state; when receiving the effective busy state setting signal, the state recording module pulls up the busy state. When the system is busy, data is not available through the GTX transceiver. When receiving an operation failure signal from the master state machine, the module outputs a valid switch failure flag and reports it to the processor core via the standardized AXI-Lite interface.

Time-meter

The timer is used for timing the DRP _ WAIT state. The timer is cleared when a valid slave clear or master clear signal is received. When no valid clear signal is detected, the timer is incremented to a single operation wait upper limit. The single operation latency upper bound is configured by the processor core through the standardized AXI-Lite interface. After reaching the upper limit, the timer sets a wait timeout signal and transmits it to the slave module. After receiving the signal, the slave control module enters an error processing state from the DRP _ WAIT state.

Retry number counter

The retry number counter is used for counting the retry number of the master control state machine, and when the counter receives a signal of clearing the retry number, the counter is cleared. The counter is incremented when a retry number increase signal is received. When the retry count reaches the upper limit of the retry count, the retry count counter sets the retry count overrun flag and transmits to the master state machine. And the master control state machine receives the retry number overrun mark and transfers the retry state to the idle state. Wherein, the upper limit of the retry times is obtained by the processor core through the standardized AXI-Lite interface configuration.

It can be seen from the above detailed description of the present invention that the present invention can implement multi-rate switching by dynamically configuring different rates of the GTX transceiver through the AXI-Lite standard interface, and at the same time, the present invention implements step simplification, reduces development complexity and design difficulty, and improves rate switching efficiency.

Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A standardized configurable multi-rate switching system oriented to the spacefiber protocol, the system being associated with a processor core through a standardized AXI-Lite interface, the system comprising: the device comprises a master control module, a slave control module, a write cycle control module, a read cycle control module, a configuration module, a synchronization module, a rate switching module and a Xilinx GTX transceiver;

the configuration module is used for waiting for writing data written into the Xilinx GTX transceiver according to the corresponding relation between the rate switching instruction and the attribute to be modified according to the rate mode signal;

the Xilinx GTX transceiver is used for modifying attributes by adopting a read-modify-write-back mode and generating a drprdy signal, so that the slave control module, the read cycle control module or the write cycle control module respectively sends a single-operation completion mark, a read cycle completion mark or a write cycle completion mark to the master control module.

2. The spacefiber protocol oriented standardized configurable multi-rate switching system of claim 1 wherein the master control module master state machine comprises an idle state, a check state, a read wait state, a NEXTR state, a write wait state, a NEXTW state, a rate switch state, a reset state and a retry state for controlling read and write operations, state updates and state records of the whole system;

when the main control module starts to operate, the main state machine enters a check state from an idle state; the main state machine can enter a reading state unconditionally when in a verification state; in a reading state, the main state machine enters a reading waiting state unconditionally, and a reading process flag signal is set; if the master state machine receives the set single operation completion signal from the slave state machine, the master state machine enters a NEXTR state, otherwise, the master state machine is still in a read waiting state; when the read cycle completion flag is detected to be set, the read cycle completion flag indicates that all read operations of the current rate switching are completed, and the main state machine enters a write-in state in a NEXTR state; if the main state machine does not detect that the reading cycle completion flag is set in the NEXTR state, the main state machine enters the reading state again and carries out the next single reading operation; entering a writing waiting state unconditionally in a writing state; if the main state machine receives the single operation completion signal, the main state machine enters a NEXTW state from a write-in waiting state, otherwise, the main state machine is still in the write-in waiting state; when the main state machine receives an effective write cycle completion mark, the main state machine enters a rate switching state, otherwise, the main state machine enters a write-once state again, and a new round of single write operation is started; the main state machine directly enters a reset state from a rate switching state, and the reset state unconditionally enters an idle state;

3. The spacefiber protocol-oriented standardized configurable multi-rate switching system of claim 2, wherein the slave state machine of the slave control module comprises a start state, a DRP _ READ state, a DRP _ WAIT state, a DRP _ WRITE state, a done state and an error handling state; when receiving a slave state machine READ enable signal from a master state machine, the slave state machine enters a DRP _ READ state; when a slave state machine WRITE enabling signal from a master state machine is received, the state machine enters a DRP _ WRITE state; entering a DRP _ WAIT state unconditionally in a DRP _ READ state and a DRP _ WRITE state; in the DRP _ WAIT state, if receiving a drprdy signal from the state machine, entering a completion state, if receiving a waiting overtime signal from the state machine, entering an error processing state, otherwise, the slave state machine is still in the DRP _ WAIT state; the slave state machine unconditionally enters the start state in the done state.

4. The spacefiber protocol oriented standardized configurable multi-rate handover system of claim 3, further comprising: the device comprises an address selection module, a state recording module, a timer and a retry number counter;

the timer is used for timing the DRP _ WAIT state; when an effective slave control clearing signal or a master control clearing signal is received, resetting the timer; when no valid clear signal is detected, the timer is incremented to a single operation wait upper limit; the single operation wait upper limit is configured by a processor core through a standardized AXI-Lite interface; after the upper limit is reached, the timer sets a waiting overtime signal and transmits the signal to the slave control module;

the retry number counter is used for counting the retry number of the main state machine; when receiving the signal of clearing retry times, the counter is cleared; when receiving the retry number increasing signal, the counter is incremented; when the upper limit of the retry times is counted, the retry time counter sets a retry time overrun mark and transmits the retry time overrun mark to the master state machine; the master state machine receives the retry number overrun mark and transfers the retry state to an idle state; the retry number upper limit is configured by the processor core through a standardized AXI-Lite interface;

the state recording module is used for indicating the state of rate switching, and setting a busy signal when the system is in the process of rate switching; when receiving the effective busy clearing signal, the state recording module clears the busy state; when receiving an effective busy state setting signal, the state recording module raises the busy state; when the system is in the busy state, the data in the transceiver is invalid through the GTX; when receiving the operation failure signal from the main state machine, the state recording module outputs a valid switching failure mark and reports the switching failure mark to the processor core through the standardized AXI-Lite interface.

5. The spacefiber protocol oriented standardized configurable multi-rate switching system of claim 4 wherein when the master state machine is in an idle state, a write cycle clear signal is set and used to clear the number of write cycles of the write cycle control module; the reading period clearing signal is set and is used for clearing the number of reading periods of the reading period control module; a clear retry number signal is set and transmitted to a retry number counter; generating a master control clearing signal for clearing the timer;

when the main state machine is in an idle state and the next state is still in the idle state, the busy state clearing signal is set and transmitted to the state recording module to cancel the busy state; when the main state machine is in an idle state and the next state is a check state, the busy state signal is set and transmitted to the state recording module to mark the start of the busy state; meanwhile, setting a maximum reading period signal and a maximum writing period signal according to a rate mode; the maximum writing cycle number and the maximum reading cycle number are respectively used for the total writing cycle number required by the writing cycle control module and the total reading cycle number required by the reading cycle control module;

when the master state machine is in a reading state, the slave state machine reading enabling signal is set and is used for transferring the slave state machine from a starting state to a DRP _ READ state; in the reading state of the main state machine, a reading process flag signal is set;

when the main state machine is in a writing-in state, the main state machine sets a reading period clearing signal for clearing the number of reading periods; meanwhile, setting a WRITE enable signal of the slave state machine to transfer the working state of the slave state machine from a starting state to a DRP _ WRITE state;

when the main state machine is in a NEXTW state, the main state machine sets a write cycle increasing signal for controlling the increment of the number of write cycles and further controlling the write address and the write data;

when the main state is in a reset state, the main state machine sets a reset signal of a converter and transmits the reset signal to the Xilinx GTX transceiver;

when the main state machine is in a retry state and the retry times exceed the upper limit, setting an operation failure mark and transmitting the operation failure mark to a state recording module; at the same time, the master state machine issues a master clear signal for clearing the timer value and a bit retry number increment signal for accumulation of retry numbers.

6. The spacefiber protocol oriented standardized configurable multi-rate switching system of claim 5, wherein when the slave state machine enters a DRP _ READ state or a DRP _ WRITE state from an idle state, a slave control clear signal is set and transmitted to the timing module; in the DRP _ READ state, the slave state machine pulls up the drpen signal and the low drpwe signal according to the READ sequence to perform a single DRP READ operation; in the DRP _ WRITE state, the slave state machine sets a drpen signal and sets a drpecewe signal according to the WRITE time sequence; the writing address is a 9-bit drpaddr signal, the writing data is a 16-bit drpdh signal, and the two signals are respectively generated by an address selection module and a writing period control module; when the slave state machine is in a completion state, setting a single-operation completion signal and transmitting the signal to the master control module; when receiving the single operation completion signal and setting, the main state machine enters a NEXTR state from a reading waiting state or enters a NEXTW state from a writing waiting state; in an error processing state, the slave state machine sets a single operation failure mark and transmits the single operation failure mark to the master state machine; if the main state machine is in the read waiting state or the write waiting state at the moment, the main state machine enters a retry state.

7. The spacefiber protocol oriented standardized configurable multi-rate switching system of claim 3 wherein the read cycle control module clears the read cycle count when receiving a read cycle clear signal from a master state machine; when receiving a valid read cycle increasing signal of the main state machine, the read cycle control module starts to count the read cycles; when the reading period counts to the maximum reading period signal, the reading period control module sets a reading period completion mark for the main state machine to use, all the reading operations of the current speed switching are indicated to be completed, and the main state machine enters a writing state from a NEXTR state; at each read cycle, when the read process flag is active and the drprdy signal is active, the read cycle control module reads the drpdo value from the Xilinx GTX transceiver and records the corresponding attribute value.

8. The spacefiber protocol-oriented standardized configurable multi-rate switching system of claim 3 wherein the write control module outputs a drpdi signal to the Xilinx GTX transceiver to modify its corresponding attribute according to a write cycle according to attribute write data inputted by the configuration module; when an effective write cycle clearing signal is received, the write cycle control module clears the write cycle count; when receiving an effective write cycle increasing signal, the write cycle control module starts to count the write cycle; when the write cycle counts to the maximum write cycle signal, the write cycle control module sets a write cycle completion flag for the main state machine to use, and indicates that all write operations of the rate switching are completed; the main state machine receives the signal and then enters a rate switching state from a NEXTW state, otherwise, the main state machine continues to enter a write-in state to carry out read operation again.

9. The spacefiber protocol-oriented standardized configurable multi-rate switching system as claimed in claim 1, wherein the Xilinx GTX transceiver first needs to read attribute data of a corresponding configuration space of the transceiver, then transmits the read attribute data to the read cycle control module, and writes back the configuration space of a corresponding address after the write cycle control module is modified.

10. A standardized configurable multi-rate switching method facing the spacefiber protocol based on the system of one of claims 1 to 9, the method receives a rate switching instruction sent by a processor core through the standardized AXI-Lite interface and transmits the rate switching instruction to a synchronization module; the synchronization module synchronizes the rate switching instruction signal in the system clock domain to keep the integrity of the signal and generate a rate switching request signal; the rate switching request signal and an initialization completion flag signal from the Xilinx GTX transceiver jointly form a start flag signal of the main control module;

after receiving the start mark signal, the master control module sends a read enable signal to the slave control module and sequentially sends a read cycle clearing signal, a read cycle increasing signal and a maximum read cycle signal to the read cycle control module respectively; after receiving the read enable signal, the slave control module sequentially performs read operation; the read cycle control module generates a read address required by the slave control module when the slave control module carries out single read operation; the Xilinx GTX transceiver firstly reads attribute data of a corresponding configuration space of the Xilinx GTX transceiver and then transmits the read attribute data to the read cycle control module; writing back the configuration space of the corresponding address after the write cycle control module is modified; when a reading period clearing signal from the main state machine is received, the reading period control module clears the reading period count; when receiving a valid read cycle increasing signal of the main state machine, the read cycle control module starts to count the read cycles; when the reading period counts to the maximum reading period signal, the reading period control module sets a reading period completion mark for the main state machine to use;