CN110825684A - Serial port interface integrated output system - Google Patents
Serial port interface integrated output system Download PDFInfo
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- CN110825684A CN110825684A CN201911121315.0A CN201911121315A CN110825684A CN 110825684 A CN110825684 A CN 110825684A CN 201911121315 A CN201911121315 A CN 201911121315A CN 110825684 A CN110825684 A CN 110825684A
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- module
- data
- serial port
- port interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
The invention discloses a serial port interface integration output system, which comprises: register module, serial port interface module, processing module, conversion output module and digital-to-analog conversion module, user's optional 3 line formula or 4 line formula serial port interface module allows to carry out programming and readback to many internal parameters, and possess advanced low spurious and distortion design technique, high-quality synthesis can be realized to the broadband signal of high intermediate frequency from the baseband, and support many master controls, wherein any equipment that can send and receive all can become the main bus, transmission and clock frequency that a master control can control signal, let system's design more nimble.
Description
Technical Field
The invention relates to the field of protocol standards of converters, in particular to a serial port interface integration output system.
Background
In the past, the connection method of data transmission is mainly divided into a parallel port and a serial port, wherein the parallel port transmits data for each data bit simultaneously, and when the machine executes a sequence program, the data can be operated simultaneously corresponding to all or part of the data stored in the internal processing unit, so that the parallel means that the data is divided into a plurality of blocks and the blocks are respectively mapped to different processors, each processor runs the same processing program to process the assigned data, but the defect is that the number of bits of the memory is large, the number of data lines are required, and therefore, the cost is relatively high.
And serial and parallel ports are an opposing pair of concepts. The Serial port is data that is transmitted by data bits in sequence in a transmission process, that is, the data is sequentially transmitted by one bit by using one data line, each bit of data occupies a fixed time length, and information can be exchanged between systems only by a few lines, so that cost is greatly reduced.
Although both the above-mentioned serial interfaces are synchronous transmission interfaces and are mainly applied to processors and peripheral chips, since SPI is a high-speed, full-duplex, synchronous communication bus, and a standard SPI also uses only 4 pins, and is often used for communication of devices such as a single chip microcomputer, a real-time clock, a digital signal processor, and the like, the SPI communication principle IIC is simple, and it is mainly a master-slave communication mode, and this mode generally has only one master and one or more slaves, and in time sequence, SPI does not start, stop, and respond, and when SPI is in communication, it is only responsible for communication regardless of whether communication is successful, and IIC acquires information of successful and failed communication through response information, so the transmission speed is relatively slow.
Disclosure of Invention
The present invention provides a serial port interface integrated output system with simple hardware structure and high transmission speed, which is directed to the above-mentioned defects of the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: constructing a serial port interface consolidation output system, comprising: the register module is used for accessing the initialization data and the first data; the serial port interface module is electrically connected with the register module and reads the initialization data; the processing module receives and operates the first data to generate second data; the conversion output module is electrically connected with the processing module, generates and configures an internet protocol address, and generates a packet according to the second data and the internet protocol address; and the digital-to-analog conversion module is respectively and electrically connected with the serial port interface module and the conversion output module, reads the initialization data through the serial port interface module to carry out initialization operation, receives the packet and converts the packet into analog quantity, and transmits the analog quantity to the Internet protocol address.
In the system of the invention, the processing module is a JESD 204B IP core.
In the system of the present invention, the second data and the packet are accessed at the same internet protocol address.
In the system of the invention, the digital-to-analog conversion module is an AD9144 digital-to-analog converter.
In the system of the present invention, the packet includes an instruction field and a data field, and the instruction field is used as a starting point.
In the system of the present invention, the conversion output module generates the packet according to the timing sequence of the instruction field and the data field.
In the system of the present invention, the serial port interface module transmits a command to the digital-to-analog conversion module according to the command field.
In the system of the present invention, the instruction field further includes a most significant bit first mode or a least significant bit first mode.
In the system of the present invention, further comprising: and the data control module is respectively electrically connected with the registering module and the processing module and transmits the first data to the processing module through the registering module.
The serial port interface integrated output system has the following beneficial effects: the user-selectable 3-wire or 4-wire serial port interface module allows programming and readback of a plurality of internal parameters, and has advanced low stray and distortion design technology, high-quality synthesis can be realized from a baseband to a broadband signal of high and intermediate frequency, and multiple main controls are supported, wherein any device capable of sending and receiving can become a main bus, and one main control can control the transmission and clock frequency of the signal, so that the system design is more flexible.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a serial port interface integrated output system according to the present invention;
FIG. 2 is a timing diagram of a serial port interface MSB-preferred mode packet data according to the present invention;
FIG. 3 is a timing diagram of the LSB-first mode packet data of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the embodiment of the present invention, a schematic structural diagram of the serial port interface integrated output system is shown in fig. 1. In the figure, the serial port interface integrates an output system, and the system comprises a register module 1, a serial port interface module 2, a processing module 3, a conversion output module 4, a digital-to-analog conversion module 5 and a data control module 6.
In this embodiment, the register module 1 accesses the initialization data D0 and the first data D1; the serial port interface module 2 is electrically connected with the register module 1 and reads the initialization data D0; the processing module 3 is a JESD 204B IP core and receives and operates the first data D1 to generate second data D2; the conversion output module 4 is electrically connected to the processing module 3, generates and configures an internet protocol address, and generates a packet according to the second data D2 and the internet protocol address; the digital-to-analog conversion module 5 is an AD9144 digital-to-analog converter, is respectively and electrically connected with the serial port interface module 2 and the conversion output module 4, and receives packets and converts the packets into analog quantity after the initialization operation is performed by reading the initialization data D0 through the serial port interface module 2, and transmits the analog quantity to an internet protocol address; the data control module 6 is electrically connected to the register module 1 and the processing module 3, and transmits the first data D1 to the processing module 3 through the register module 1.
The packets generated by the second data D2 generated by the processing module 3 and the conversion output module 4 access the same internet protocol address, and the packets include an instruction field and a data field, and the instruction field is used as a starting point, so the conversion output module 4 generates the packets according to the timing of the instruction field and the data field, the serial port interface module 2 can transmit a command to the digital-to-analog conversion module 5 according to the instruction field, and the instruction field further includes a most significant bit priority mode or a least significant bit priority mode.
In this embodiment, the serial port interface module 2 receives the initialization data D0 through the register module 1 and transmits the initialization data D0 to the digital-to-analog conversion module 5 for initialization setting, which is defined as the following table 1, the data control module 6 transmits the first data D1 to the processing module 3 through the register module 1 for processing, and then generates the second data D2, the conversion output module 4 generates and configures an internet protocol address, and generates a packet according to the second data D2 and the internet protocol address, and finally the serial port interface module 2 transmits a command to the digital-to-analog conversion module 5 according to the command field and configures the command into a four-wire main interface protocol to control three independent serial port interfaces, wherein a timing diagram of the packet in the serial port interface most significant bit priority mode is shown in fig. 2. In the figure, the width of the receiving register is configured in sixteen bits, wherein the first eight bits are the instruction field and the last eight bits are the data field, and the data transmitted in the most significant bit-first mode (MSB-first) conforms to the default power-on mode of the switching device.
In another embodiment, a timing diagram of a serial port interface least significant bit first mode packet is shown in FIG. 3. In the figure, data transmitted in the least significant bit-first mode (LSB-first) corresponds to a default power-up mode of the switching device.
Table 1 is as follows:
the invention provides a serial port interface integrated output system with simple hardware structure and high transmission speed, a user can select a 3-wire or 4-wire serial port interface module to allow programming and readback of a plurality of internal parameters, and the system has advanced low stray and distortion design technology, high-quality synthesis can be realized from a baseband to a broadband signal of high and intermediate frequency, and multiple main controls are supported, wherein any device capable of sending and receiving can be used as a main bus, and one main control can control the transmission and clock frequency of the signal, so that the system design is more flexible.
The above description is only exemplary of the present invention and should not be taken as limiting the invention, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A serial port interface consolidation output system, comprising:
the register module is used for accessing the initialization data and the first data;
the serial port interface module is electrically connected with the register module and reads the initialization data;
the processing module receives and operates the first data to generate second data;
the conversion output module is electrically connected with the processing module, generates and configures an internet protocol address, and generates a packet according to the second data and the internet protocol address; and
and the digital-to-analog conversion module is respectively and electrically connected with the serial port interface module and the conversion output module, reads the initialization data through the serial port interface module to perform initialization operation, receives the packet and converts the packet into analog quantity, and transmits the analog quantity to the Internet protocol address.
2. The system of claim 1, wherein the processing module is a JESD 204B IP core.
3. The system of claim 1 wherein said second data and said packet access are at the same internet protocol address.
4. The system of claim 1, wherein the digital-to-analog conversion module is an AD9144 digital-to-analog converter.
5. The system of claim 1, wherein the packet includes an instruction field and a data field, and the instruction field is used as a starting point.
6. The system of claim 5, wherein the translation output module generates the packet according to the timing of the command field and the data field.
7. The system of claim 5, wherein the serial port interface module transmits a command to the digital-to-analog conversion module according to the command field.
8. The system of claim 5, wherein the instruction field further comprises a most significant bit first mode or a least significant bit first mode.
9. The system of claim 1, further comprising:
and the data control module is respectively electrically connected with the registering module and the processing module and transmits the first data to the processing module through the data control module.
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| CN201911121315.0A CN110825684A (en) | 2019-11-15 | 2019-11-15 | Serial port interface integrated output system |
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| CN201911121315.0A CN110825684A (en) | 2019-11-15 | 2019-11-15 | Serial port interface integrated output system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113326215A (en) * | 2021-07-04 | 2021-08-31 | 芯河半导体科技(无锡)有限公司 | SPI NOR and NAND flash memory transmission mode identification method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113326215A (en) * | 2021-07-04 | 2021-08-31 | 芯河半导体科技(无锡)有限公司 | SPI NOR and NAND flash memory transmission mode identification method |
| CN113326215B (en) * | 2021-07-04 | 2024-01-19 | 芯河半导体科技(无锡)有限公司 | SPI NOR and NAND flash memory transmission mode identification method |
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