KR20050011822A - Apparatus for connecting plurality of device with same address to one bus controller and operation method thereof - Google Patents

Abstract

PURPOSE: An apparatus for connecting plural devices having the same address to one bus connection and its operating method are provided to reduce the volume of hardware and allows a host processor to simply control a 12C bus controller. CONSTITUTION: Each transceiver module(200_1-200_4) includes a serial EEPROM having the same device address and handles interfacing with a giga bit Ethernet link. A 12C bus controller(202) writes data received from a host processor(204) in the serial EEPROM of a corresponding transceiver module through a path establishing unit(201) and reads data stored in the serial EEPROM of a corresponding transceiver module through the path establishing unit(201). The path establishing unit(201) provides a 12C bus path between one of the transceiver modules(200_1-200_4) and the 12C bus controller(202). A buffer control logic unit(203) inputs a signal received from the host processor(204), a signal exchanged between the 12C bus controller(202) and the transceiver modules(200_1-200_4) and a synchronization signal, and generates control signals for controlling a plurality of three-state buffers based on the inputted signals. The host processor(204) controls a general operation of a network unit.

Description

Apparatus for connecting a plurality of devices having the same address to one bus controller and its operation method {APPARATUS FOR CONNECTING PLURALITY OF DEVICE WITH SAME ADDRESS TO ONE BUS CONTROLLER AND OPERATION METHOD THEREOF}

The present invention relates to an Ethernet line card of a network device, and more particularly, to an apparatus and a method of operating the same for connecting a plurality of devices having the same address to a single bus controller.

In general, as a physical media dependent (PMD) for connecting external Gigabit Ethernet links to a line card that includes a gigabit Ethernet physical layer (PHY layer) in a network device, Hot pluggable optical transceiver modules such as Small From factor Pluggable (SFP), or optical transceiver modules fixed to a PCB are mounted. Most of the optical transceivers and copper transmission transceiver modules used in Gigabit Ethernet applications are the "Serial mode definition protocol (I2C bus)" of the "Gigabit Interface Converter (GBIC) Rev 5.5" proposed in the "SFF_8053" specification of "SFF Commitee". Built-in "Serial-EEPROM" is supported. As the packet processing capacity of the system becomes larger, more PMDs, or transceiver modules, are mounted on one line card.

In the transceiver module, information representing the characteristics of the transceiver is stored in a serial EEPROM, and most of these serial EEPROMs use an I2C bus method. The serial EEPROM has “A2 to A0” as an address pin, which is an address for distinguishing each device when multiple serial EEPROMs are connected to one I2C bus. The I2C bus controller loads the value of the device to select in "A2-A0 (A0 = LSB)" of the serial data. The serial EEPROM responds only when it receives the same address as itself.

Meanwhile, the network device may connect a plurality of serial EEPROMs in parallel on one I2C bus by the address pins of the serial Y pyroms. However, the condition is that a serial EEPROM having the same address among the addresses that can be composed of three bits A0 to A2 cannot be configured. If configured, one I2C controller must be used for each transceiver module with a serial EEPROM.

However, according to the related art, the serial EEPROM address pins in the transceiver module mounted in the network device are not external to the transceiver module, but are fixed to "000" inside, and these transceiver modules are mostly GBIC Rev5. .5 "AT24C01A" from "Atmel" is used. In other words, when mounting a plurality of transceiver modules in a network device, there is a problem that the I2C bus controller must be provided with the same number of transistor modules because the addresses of the transceiver modules are all the same as "000". For example, if four GBICs (transceiver modules) are used on a gigabit Ethernet line card, four I2C controllers should be used.

1 is a view schematically showing an Ethernet line card according to the prior art. As shown, it can be seen that the transceiver module and the I2C controller are configured in one-to-one correspondence.

In summary, GBICs, SFPs, and the like used as physical media dependent (PMD) have a serial EEPROM, which is set to the same address. That is, since the address pin of the built-in serial EEPROM cannot be modified, there is a problem in that several I2C dedicated controllers such as PCF8584 of Philips Semiconductor Inc. must be used. In addition, since most host processors provide one I2C dedicated port (I2C controller), a separate I2C controller must be implemented in order to use a transceiver module with a serial EEPROM having the same address as described above. There is a problem.

Accordingly, an object of the present invention is to provide an apparatus and a method of operating the same for connecting a plurality of devices having the same address on one bus.

According to a first aspect of the present invention for achieving the above object, a device for connecting a plurality of devices having the same address to one bus controller, a plurality of three-state buffer consisting of two buffers in opposite directions And the three-state buffers and the plurality of devices are connected one-to-one, the bus controller exchanging serial data in a predetermined format with the plurality of devices according to a predetermined protocol, and identification of a device to be accessed from a host processor. Receives information, receives the serial data from the bus controller, and analyzes the serial data to enable serial data from the bus controller by enabling a buffer in the write direction in a three-state buffer connected to the device when data recording is required. Is transmitted to the device, and data read is required. To enable the read out of the buffer in the direction of tri-state buffers associated with the device and the serial data from the device, it characterized in that it comprises a buffer control logic to transfer to the bus controller.

According to a second aspect of the present invention, in a line card in which three state buffers composed of two buffers in opposite directions are connected to each of a plurality of transceiver modules using an I2C bus interface, the three state buffers are controlled. A method for accessing a specific transceiver module may include: outputting, by a host processor, a signal specifying a transceiver module to be accessed; and receiving a signal specifying the transceiver module; (start) and outputting serial data (SDA) of a predetermined format to the bus, generating a clock signal (SCL) for synchronization between devices, and when the start condition signal is detected, a buffer control logic unit to the transceiver module Enables the write direction buffer in the connected three-state buffer to transfer serial data from the bus controller to the transceiver module. (B) outputting, by the transceiver module, a response signal (RX_ACK) for the serial data to the buffer in the read direction from the three-state buffer; and the buffer control logic unit is configured to perform a ninth clock from the time of transmission of the serial data. And enabling the buffer in the read direction to transfer the response signal to the bus controller.

1 is a block diagram of an Ethernet line card according to the prior art.

2 is a block diagram illustrating an Ethernet line card (or PMD) according to an exemplary embodiment of the present invention.

3 is a view showing in more detail the configuration of FIG.

FIG. 4 is a diagram illustrating a procedure for reading data from a serial EPIROM of a specific transceiver module in an Ethernet line card according to an embodiment of the present invention. FIG.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, an apparatus for connecting a plurality of transceiver modules to one I2C bus controller and a method of operating the same will be described when configuring a plurality of transceiver modules having the same address in a line card in a network device. Meanwhile, the present invention can be applied to a system using a transceiver module that does not have the same address.

2 illustrates a configuration of an Ethernet line card (or PMD) having a plurality of transceiver modules according to an embodiment of the present invention. 3 illustrates the configuration of FIG. 2 in more detail. The figure only shows four transceiver modules for convenience.

As shown, the Ethernet line card according to the present invention includes a plurality of transceiver modules 200-1 to 200 -N, a routing unit 201, an I 2 C bus controller 202, and a buffer control logic unit ( 203 and a host processor 204.

Meanwhile, the route setting unit 201 includes a plurality of three state buffers. The three-state buffer is composed of two buffers having different directions, and operates in three states. The first state is a disable state, the second state is a write state (state of writing data to EPIROM), and the third state is a read state (state of reading data from EPIROM). Here, in the second state, the buffer in the recording direction (lower buffer) is enabled, and in the third state, the buffer in the read direction (upper buffer) is operated. The plurality of tri-state buffers and the plurality of transceiver modules 200 are also connected one to one.

Referring to Figures 2 and 3, the transceiver modules 200 have serial Ypyroms with the same device address and are responsible for interfacing with gigabit Ethernet links. Here, the serial Y pyrom stores information indicating the characteristics of the transceiver module.

The I2C bus controller 202 writes the data from the host processor 204 to the serial Y pyrom of the transceiver module through the routing unit 201 and writes the data stored in the serial Y pyrom in the transceiver modules. Read through the routing unit 201. In particular, the I2C bus controller 202 transmits and receives signals according to a serial mode definition protocol. In this case, signals (SDA: serial data) transmitted and received with the I2C bus controller 202 and the transceiver module 200 are simultaneously transmitted to the buffer control logic unit 203.

The routing unit 201 provides an I2C bus path between one of the plurality of transceiver modules 200 and the I2C bus controller 202 by a control signal from the buffer control logic unit 203. Perform. As mentioned above, in the case of writing data in the EPIROM of the transceiver module, the buffer in the write direction (lower buffer) is enabled, and in the case of reading data from the EPIROM, the buffer in the read direction (upper buffer) is enabled. do.

The buffer control logic unit 203 inputs a control signal from the host processor 204, a signal SDA and a synchronization clock SCL signal exchanged between the I2C bus controller 202 and the transceiver module 200. And control signals (read signal, write signal and enable signal) for controlling the plurality of three-state buffers based on the signals. The enable signal is a control signal for enabling the three-state buffer, the read signal is a control signal for enabling the buffer in the read direction (upper buffer), and the write signal is a buffer in the write direction (bottom). Buffer) to enable the control signal.

The host processor 204 controls the overall operation of the network device. In particular, according to the present invention, the host processor 204 outputs data of a format defined to communicate with the transceiver module 200 supporting the serial mode definition protocol to the I2C controller 202. At this time, the data of the predetermined format is simultaneously transferred to the buffer control logic unit 203.

The operation of the above-described Ethernet line card is as follows.

In general, the first time a network device boots up or during system operation, the host processor 204 reads data from the serial EEPROM, which stores various information of the transceiver module over the I2C bus.

When data readout is required, the host processor 204 first outputs a control signal (control data) designating a transceiver module to read data to the I2C bus controller 202 and the buffer control logic unit 203. Then, the I2C bus controller 202 generates signals SDA and SCL according to a predetermined protocol protocol in response to the control signal from the host processor 204. Meanwhile, the buffer control logic unit 203 sets a corresponding buffer enable register in response to a control signal from the host processor 204. The buffer control logic unit 203 extracts a start condition signal start from the serial data SDA from the I2C bus controller 202, and connects to the specified transceiver module when the start condition signal is detected. An enable signal and a write signal are output to the status buffer. At this time, the buffer in the write direction is enabled among the two buffers constituting the three-state buffer, and serial data from the I2C bus controller 202 is transferred to the designated transceiver module. This serial data consists of 8 bits (1010 0000). Here, "1010" represents a device type identifier (EEPROM), "000" represents device addresses A0 to A2, and "0" represents write.

Meanwhile, the I2C slave (transceiver module) transmits a response signal (RX_ACK) for the serial data to the I2C bus controller 202 according to the protocol. That is, the buffer control logic unit 203 enables the response signal by enabling the read-out buffer of the two buffers constituting the three-state buffer at the ninth clock from the generation of the synchronization clock SCL according to the protocol agreement. (RX_ACK) passes to the I2C bus controller 202.

After exchanging protocol signals for data reading as described above, when receiving real data from the transceiver module through the I2C bus, the transceiver module occupies the I2C bus and transmits serial data to the I2C bus controller 202 so that the read direction buffer Is enabled. At this time, the buffer control logic unit 203 enables the buffer in the recording direction at the ninth clock from the start of the synchronous clock (SCL) output from the I2C bus controller 202, and the I2C bus controller 202 is the recording. The response signal TX_ACK is transmitted to the corresponding transceiver module through the buffer in the direction. If the data is no longer read out, the response signal is not transmitted. An I 2 C bus controller 202 transfers the data received from the transceiver module to the host processor 204. In this manner, the host processor 204 reads data of a specific transceiver module.

In general, at system boot-up, the host processor 204 sequentially accesses serial EEPROMs of the transceiver modules to obtain internal information of the transceiver modules. On the other hand, when the transceiver module is mounted by the operator during system operation, the host processor 204 outputs a control signal for designating the mounted transceiver module to the I2C controller 202 and the buffer control logic unit 203 and the Acquire internal information of transceiver module. In addition, even during normal operation, the host processor 204 outputs a control signal specifying a transceiver module from which data is to be read to obtain internal information of the transceiver module.

The buffer control logic unit 203 sets a corresponding enable register in response to a transceiver module designation signal from the host processor 204 to generate a buffer enable signal to a three-state buffer connected to the corresponding transceiver module. do. Thereafter, when a control signal for designating another transceiver module is input, the enable register is cleared and the enable register of the other transceiver module is set to output an enable signal to a tri-state buffer connected to the other transceiver module.

FIG. 4 illustrates a procedure for reading data from the YPIROM of a specific transceiver module in an Ethernet line card according to an exemplary embodiment of the present invention.

Referring to FIG. 4, in initialization, the host processor 204 outputs a control signal to the buffer control logic unit 203 in step 401 to disable all three state buffers. In operation 403, the host processor 204 determines a transceiver module to read information, and outputs a control signal for designating the transceiver module to the buffer control logic unit 203 and the I2C bus controller 202. In step 405, the I2C bus controller 202 outputs the start condition signal and the serial data SDA specifying the transceiver module to the bus and generates a synchronous clock SCL. The sync clock SCL is provided to the plurality of transceiver modules 200 and the buffer control logic unit 203. On the other hand, the buffer control logic unit 203 detects the start condition signal from the signal from the I2C bus control unit 202 in step 407, and configures a three-state buffer connected to the transceiver module when the start condition signal is detected. Among the two buffers, the buffer in the recording direction is enabled to transmit serial data SDA from the I2C bus controller 202 to the transceiver module.

In operation 409, the buffer control logic unit 203 enables a buffer in a read direction of two buffers constituting the three-state buffer at the ninth clock from the start of the synchronization clock SCL, thereby enabling the transceiver module. Transmits a response signal from the I2C bus controller 202. In operation 411, the I2C bus controller 202 checks whether a response signal RX_ACK is received from the transceiver module. If the response signal is not received, the process proceeds to step 439 to perform the corresponding error processing. If the response signal is received, the I2C bus controller 202 outputs serial data specifying an actual read address to the bus in step 413. In operation 415, the buffer control logic unit 203 enables the buffer in the recording direction to transfer the serial data to the transceiver module.

In operation 417, the buffer control logic unit 203 enables a buffer in the read direction at the ninth clock from the start of the transmission of the serial data, and transmits a response signal from the transceiver module to the I2C bus controller 202. do. In operation 419, the I2C bus controller 202 checks whether a response signal RX_ACK is received from the transceiver module. If the response signal is not received, the process proceeds to step 441 to perform the corresponding error processing. If the response signal is received, the I2C bus controller 202 outputs serial data for commanding data transmission to the I2C bus in step 421. In operation 423, the buffer control logic unit 203 enables the buffer in the recording direction to transfer the serial data to the transceiver module.

In operation 425, the buffer control logic unit 203 enables a buffer in the read direction at the ninth clock from the start of transmission of the serial data and transmits a response signal from the transceiver module to the I2C bus controller 202. do. In operation 427, the I2C bus controller 202 checks whether a response signal RX_ACK is received from the transceiver module. If the response signal is not received, the process proceeds to step 443 to perform the corresponding error processing. If the response signal is received, the I2C bus controller 202 receives 1 byte data from the transceiver module in step 429.

In operation 431, the host processor 202 determines whether to continue to receive data. If no data is continuously received, the host processor 202 returns to step 401 to disable all three state buffers. If the data is continuously received, the I2C bus controller 202 outputs a response signal TX_ACK to the bus in step 433. On the other hand, the buffer control logic unit 203 enables the buffer in the recording direction in step 435 to transfer the response signal from the I2C bus controller 202 to the transceiver module, and in step 437 in the read direction. After enabling the buffer, the process returns to step 429.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

As described above, the present invention has the advantage of connecting several devices having the same address on one I2C bus. In other words, the hardware volume can be reduced, and the host processor has the effect of controlling the I2C bus controller in a simple manner.

Claims (2)

An apparatus for connecting a plurality of devices having the same address to one bus controller, A plurality of tri-state buffers composed of two buffers in opposite directions, the tri-state buffers and the plurality of devices are connected one-to-one, The bus controller for exchanging serial data of a predetermined format with the plurality of devices according to a predetermined protocol; Receive identification information of a device to be accessed from a host processor, receive the serial data from the bus controller, analyze the serial data, and enable a write direction buffer in a three-state buffer connected to the device when data recording is required. Transfers serial data from the bus controller to the device and, when data reading is required, enables a buffer in a read direction in a tri-state buffer connected to the device to transfer serial data from the device to the bus controller. And a control logic portion. A method for accessing a specific transceiver module by controlling the three-state buffer in a line card to which a three-state buffer consisting of two buffers in opposite directions is connected to each of a plurality of transceiver modules using an I2C bus interface. To Outputting, by the host processor, a signal specifying a transceiver module to be accessed; Upon receiving the signal designating the transceiver module, the bus controller outputs a start condition signal (start) and serial data (SDA) of a predetermined format to a bus according to a predetermined protocol, and outputs a clock signal (SCL) for synchronization between devices. What happens, When the start condition signal is detected, a buffer control logic unit, enabling a buffer in a write direction in a three-state buffer connected to the transceiver module to transfer serial data from the bus controller to the transceiver module; Outputting, by the transceiver module, a response signal (RX_ACK) for the serial data from the three-state buffer to a buffer in a read direction; And the buffer control logic enables the buffer in the read direction to transmit the response signal to the bus controller at a ninth clock from the time of transmission of the serial data.