CN113326215B - SPI NOR and NAND flash memory transmission mode identification method - Google Patents

Abstract

The invention discloses a SPI NOR and NAND Flash memory transmission mode identification method, which utilizes 2-line/4-line transmission commands commonly used among manufacturers, and identifies the transmission mode supported by a chip through specific code judgment logic, thereby achieving the purpose of automatically adapting the Flash chip transmission mode; the method comprises a method for automatically identifying SPI NAND Flash read mode, a method for automatically identifying SPI NAND Flash write mode, a method for automatically identifying SPI NOR Flash read mode and a method for automatically identifying SPIOR Flash write mode; the invention can automatically identify the transmission modes supported by all SPI NOR/NAND Flash; the unknown new Flash can be supported without changing the software version, and the performance of the Flash can be exerted to the maximum extent.

Description

SPI NOR and NAND flash memory transmission mode identification method

Technical Field

The invention relates to the technical field of flash memory transmission, in particular to an SPI NOR and NAND flash memory transmission mode identification method.

Background

SPI NOR and SPI NAND Flash chips only have 8 pins, so the occupied CPU pins are few, the occupied PCB area is also few, and the SPI NOR and SPI NAND Flash chips are widely used as memory chips in the embedded system at present. The manufacturers are numerous and the specifications are also various. Because SPI transmission is adopted, the input and output of the standard SPI mode is provided with one pin, so that the transmission rate is not high, and the speed of the parallel NOR/NAND Flash which does not use multi-pin transmission is high. To overcome the slow rate limitation of the standard SPI transmission mode, manufacturers have newly added two-wire transmission and four-wire transmission modes by multiplexing SI, SO, WP and HOLD pins on an original basis. Thus, the transmission rate can be increased by a factor of 2/4. Pin diagram of SPI NOR/NAND Flash as shown in fig. 1.

Wherein VCC and GND are used for power supply. Cs# is the chip select pin. SCLK is the SPI clock signal. SI is an input signal in the standard SPI single-wire mode, SO is an output signal in the standard SPI single-wire mode. SIO0 and SIO1 are input/output signals in two-wire mode, SIO0-SIO3 are input/output signals in four-wire mode, WP# and HOLD# are write protect and suspend function pins in single-wire and two-wire modes.

If a new Flash is required to be supported by the embedded system code, the code is written according to a device manual provided by a manufacturer, the manufacturer and the device identifier are read first, and the transmission mode supported by the chip is judged according to the identifier. This new Flash is eventually supported by way of updating the firmware version. This approach is not conducive to the management and control of the product software version, and the version is reissued every time a new Flash is added. To reduce release of versions, it is more common practice to build in a default set of parameters to support unknown Flash in standard SPI transmission mode. However, in the standard SPI mode, the maximum transmission speed of Flash cannot be achieved by using the multi-line transmission mode, so that the problems of slow system start, slow response and the like are caused.

Disclosure of Invention

The invention aims to provide an SPI NOR and NAND Flash memory transmission mode identification method, which utilizes 2-line/4-line transmission commands commonly used among manufacturers, and identifies which transmission mode is supported by a chip through specific code judgment logic, so as to achieve automatic adaptation of the Flash chip transmission mode, and solve the problems in the background art.

In order to achieve the above purpose, the present invention provides the following technical solutions:

the SPI NAND flash memory transmission mode identification method specifically comprises the following steps:

step 1: a 4-wire mode of SPI NAND flash needs to be started; after the 4-wire mode is started; WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission; currently, each manufacturer adopts the 0 th bit of a function Register (Feature Register) 0xb0 as the four-line start bit;

step 2: generating a random number to a cache 0;

step 3: loading cache 0 data into a Flash internal write cache by using a standard SPI single-line mode loading command (0 x 02); no write operation is used to prevent corruption of Flash content;

step 4: reading page 0 data to cache 1 using a general 4-line read command (0 x6 b);

step 5: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 4-line read operation; if the two types are different, jumping to the step 8 to continue execution;

step 6: reading page 0 data to cache 1 using a general 2-line read command (0 x3 b);

step 7: compare whether cache 0 and 1 are identical, if so, it is representative that Flash supports a 2-line read operation. Otherwise, flash only supports single-wire read operation;

step 8: generating random data to a cache 0;

step 9: using a general 4-line loading command (0 x 32) to load cache 0 data into the Flash internal cache, and not executing a writing operation; so that the data content in Flash is not destroyed;

step 10: reading page 0 data to cache 1 using a general 4-line read command (0 x6 b) (Flash, which typically supports 4-line write operations, must support 4-line read operations, so this step employs a 4-line read command instead of a standard single-line read command);

step 11: comparing whether the contents of the cache 0 and the cache 1 are the same, and if the contents are the same, supporting 4-line writing operation by Flash; otherwise Flash only supports single-wire write operations.

In addition, flash has no 2-line writing function at present, so that judgment is not performed.

The SPI NOR flash memory transmission mode identifying method includes the following steps:

step 1: a 4-wire mode of SPI NOR Flash needs to be started; after the 4-wire mode is started, WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission; some factories do not need specific commands, and some factories need to send general commands 0xb7;

step 2: reading the content of a flash specific address to the cache 0 by using a standard SPI single-line mode read command (0 x0 b);

step 3: reading page 0 data to cache 1 using a general 4-line read command (0 x6 b);

step 4: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 4-line read operation; if the two types are different, jumping to the step 7 to continue execution;

step 5: reading page 0 data to cache 1 using a general 2-line read command (0 x3 b);

step 6: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 2-line read operation; otherwise, flash only supports single-wire read operation;

step 7: because SPI Nor Flash does not have an internal buffer memory for loading data, whether 4 lines are supported by automatic identification writing or not can be judged by actually writing the data; therefore, a data block which is not used is required to be found for testing, so that whether a spare data block is used for testing is required to be judged, if yes, the testing can be continued, and otherwise, the data block can be identified only according to single-line writing;

step 8: erasing a specific address data block;

step 9: generating random data to a cache 0;

step 10: writing cache 0 data into the Flash internal cache by using a universal 4-line write command (0 x 32);

step 11: reading page 0 data to cache 1 using a general 4-line read command (0 x6 b) (Flash, which typically supports 4-line write operations, must support 4-line read operations, so this step employs a 4-line read command instead of a standard single-line read command);

step 12: comparing whether the contents of the cache 0 and the cache 1 are the same, and if the contents are the same, supporting 4-line writing operation by Flash; otherwise Flash only supports single-wire write operations.

Compared with the prior art, the invention has the advantages that:

1. all SPI NOR/NAND Flash supported transmission modes can be automatically identified.

2. The unknown new Flash can be supported without changing the software version, and the performance of the Flash can be exerted to the maximum extent.

Drawings

FIG. 1 is an SPI NOR/NAND Flash pin diagram.

Fig. 2 is a flowchart of automatic identification of SPI NAND Flash in the present invention.

Fig. 3 is a flowchart of SPI NOR Flash automatic identification in the present invention.

Detailed Description

The technical scheme of the patent is further described in detail below with reference to the specific embodiments.

Referring to fig. 2, an SPI NOR and NAND flash memory transmission mode identification method specifically comprises the following steps:

step 1: a 4-wire mode of SPI NAND flash needs to be started; after the 4-wire mode is started; WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission; currently, each manufacturer uses the 0 th bit of the function Register (Feature Register) 0xb0 as the four-line on bit.

Step 2: generating a random number into cache 0.

Step 3: loading cache 0 data into a Flash internal write cache by using a standard SPI single-line mode loading command (0 x 02); no write operation is used to prevent corruption of Flash content.

Step 4: page 0 data is read to cache 1 using a general 4-line read command (0 x6 b).

Step 5: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 4-line read operation; if not, jumping to the step 8 to continue execution.

Step 6: page 0 data is read to cache 1 using a general 2-line read command (0 x3 b).

Step 7: compare whether cache 0 and 1 are identical, if so, it is representative that Flash supports a 2-line read operation. Otherwise Flash only supports single-wire read operations.

Step 8: random data is generated into cache 0.

Step 9: using a general 4-line loading command (0 x 32) to load cache 0 data into the Flash internal cache, and not executing a writing operation; so that the data content in Flash is not destroyed.

Step 10: page 0 data is read to cache 1 using a general 4-line read command (0 x6 b) (Flash, which typically supports 4-line write operations, must support 4-line read operations, so this step employs a 4-line read command instead of a standard single-line read command).

Step 11: comparing whether the contents of the cache 0 and the cache 1 are the same, and if the contents are the same, supporting 4-line writing operation by Flash; otherwise Flash only supports single-wire write operations.

In addition, flash has no 2-line writing function at present, so that judgment is not performed.

The SPI NOR flash memory transmission mode identifying method includes the following steps:

step 1: a 4-wire mode of SPI NOR Flash needs to be started; after the 4-wire mode is started, WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission; some factories do not need specific commands, and some factories need to send general commands 0xb7;

step 2: reading the content of a flash specific address to the cache 0 by using a standard SPI single-line mode read command (0 x0 b);

step 3: reading page 0 data to cache 1 using a general 4-line read command (0 x6 b);

step 4: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 4-line read operation; if the two types are different, jumping to the step 7 to continue execution;

step 5: reading page 0 data to cache 1 using a general 2-line read command (0 x3 b);

step 6: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 2-line read operation; otherwise, flash only supports single-wire read operation;

step 7: since SPI NOR Flash has no internal cache for loading data. Whether the automatic identification writing supports 4 lines or not can be judged by actually writing data; therefore, a data block which is not used is required to be found for testing, so that whether a spare data block is used for testing is required to be judged, if yes, the testing can be continued, and otherwise, the data block can be identified only according to single-line writing;

step 8: erasing a specific address data block;

step 9: generating random data to a cache 0;

step 10: writing cache 0 data into the Flash internal cache by using a universal 4-line write command (0 x 32);

step 11: reading page 0 data to cache 1 using a general 4-line read command (0 x6 b) (Flash, which typically supports 4-line write operations, must support 4-line read operations, so this step employs a 4-line read command instead of a standard single-line read command);

step 12: comparing whether the contents of the cache 0 and the cache 1 are the same, and if the contents are the same, supporting 4-line writing operation by Flash; otherwise Flash only supports single-wire write operations.

While the preferred embodiments of the present patent have been described in detail, the present patent is not limited to the above embodiments, and various changes may be made without departing from the spirit of the present patent within the knowledge of one of ordinary skill in the art.

Claims (4)

1. The SPI NAND Flash memory transmission mode identification method is characterized by being capable of automatically identifying an SPI NAND Flash reading mode or a writing mode;

the method for automatically identifying SPI NAND Flash read mode comprises the following steps: writing data by using an SPI NAND Flash internal cache space in a standard single-wire writing mode, obtaining cache data by using a 4-wire and 2-wire reading mode, and judging whether the SPI NAND Flash supports a 2-wire and 4-wire reading mode by comparing whether the data contents are the same;

the method for automatically identifying the SPI NAND Flash writing mode comprises the following steps: and using the internal cache space of the SPI NAND Flash, loading data into the cache through 4 lines, reading the cache in a 4-line reading mode, and judging whether the SPI NAND Flash supports a 4-line writing mode by comparing whether the data content is the same.

2. The method for identifying the transmission mode of the SPI NAND flash memory as recited in claim 1, wherein the specific identification steps are as follows:

step 1: a 4-wire mode of SPI NAND flash needs to be started; after the 4-wire mode is started; WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission;

step 2: generating a random number to a cache 0;

step 3: loading the cache 0 data into the Flash internal write cache by using a standard SPI single-wire mode loading command 0x 02; no write operation is used to prevent corruption of Flash content;

step 4: reading page 0 data to cache 1 using a general 4-line read command 0x6 b;

step 5: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 4-line read operation; if the two types are different, jumping to the step 8 to continue execution;

step 6: reading page 0 data to cache 1 using a general 2-line read command 0x3 b;

step 7: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 2-line read operation; otherwise, flash only supports single-wire read operation;

step 8: generating random data to a cache 0;

step 9: using a general 4-line loading command 0x32 to load cache 0 data into the Flash internal cache, and not executing a writing operation; so that the data content in Flash is not destroyed;

step 10: reading page 0 data to cache 1 using a general 4-line read command 0x6 b;

step 11: comparing whether the contents of the cache 0 and the cache 1 are the same, and if the contents are the same, supporting 4-line writing operation by Flash; otherwise Flash only supports single-wire write operations.

3. The SPI NOR Flash memory transmission mode identification method is characterized by being capable of automatically identifying an SPI NOR Flash read mode or a write mode;

the method for automatically identifying SPI NOR Flash read mode comprises the following steps: reading data by a standard single-line reading mode, reading the same position data by a 4-line and 2-line reading mode, and judging whether the SPI NOR Flash supports a 2-line and 4-line reading mode by comparing whether the data content is the same;

the method for automatically identifying SPI NOR Flash writing mode comprises the following steps: and writing a group of random data by using a 4-wire writing mode by using a system free unused data block, reading the data by using a 4-wire reading mode, and judging whether the SPI NOR Flash supports a 4-wire writing mode by comparing whether the data contents are the same or not.

4. A method for identifying an SPI NOR flash memory transfer mode according to claim 3, characterized by the specific identification steps of:

step 1: a 4-wire mode of SPI NOR Flash needs to be started; after the 4-wire mode is started, WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission;

step 2: reading the content of a flash specific address to the cache 0 by using a standard SPI single-line mode read command 0x0 b;

step 3: reading page 0 data to cache 1 using a general 4-line read command 0x6 b;

step 4: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 4-line read operation; if the two types are different, jumping to the step 7 to continue execution;

step 5: reading page 0 data to cache 1 using a general 2-line read command 0x3 b;

step 6: comparing whether the content of the cache 0 and the content of the cache 1 are the same, if so, representing that Flash supports 2-line read operation; otherwise, flash only supports single-wire read operation;

step 7: because SPI NOR Flash does not have internal buffer memory for loading data, whether 4 lines are supported by automatic identification writing is realized, and the data can be judged by actual writing; therefore, a data block which is not used is required to be found for testing, so that whether a spare data block is used for testing is required to be judged, if yes, the testing can be continued, and otherwise, the data block can be identified only according to single-line writing;

step 8: erasing a specific address data block;

step 9: generating random data to a cache 0;

step 10: writing cache 0 data into a Flash internal cache by using a universal 4-line write command 0x 32;

step 11: reading page 0 data to cache 1 using a general 4-line read command 0x6 b;

step 12: comparing whether the contents of the cache 0 and the cache 1 are the same, and if the contents are the same, supporting 4-line writing operation by Flash; otherwise Flash only supports single-wire write operations.