CN113326215A - SPI NOR and NAND flash memory transmission mode identification method - Google Patents
SPI NOR and NAND flash memory transmission mode identification method Download PDFInfo
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- CN113326215A CN113326215A CN202110754025.0A CN202110754025A CN113326215A CN 113326215 A CN113326215 A CN 113326215A CN 202110754025 A CN202110754025 A CN 202110754025A CN 113326215 A CN113326215 A CN 113326215A
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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Abstract
The invention discloses a method for identifying SPI NOR and NAND Flash memory transmission modes, which utilizes a 2-line/4-line transmission command which is universal among manufacturers and identifies the transmission mode supported by a chip through specific code judgment logic so as to achieve the purpose of automatically adapting to the transmission mode of a Flash chip; the method comprises a method for automatically identifying an SPI NAND Flash read mode, a method for automatically identifying an SPI NAND Flash write mode, a method for automatically identifying an SPI NOR Flash read mode and a method for automatically identifying an SPINOR Flash write mode; the invention can automatically identify all transmission modes supported by SPI NOR/NAND Flash; unknown new Flash can be supported without changing software version, and the performance of Flash can be maximized.
Description
Technical Field
The invention relates to the technical field of flash memory transmission, in particular to a method for identifying transmission modes of an SPI NOR flash memory and an NAND flash memory.
Background
The SPI NOR and SPI NAND Flash chips only have 8 pins, so the occupied CPU pins are less, the occupied PCB area is less, and the SPI NOR and SPI NAND Flash chips are memory chips widely adopted by the current embedded system. The manufacturers are many and the specifications are various. Because the SPI transmission is adopted, the standard SPI mode input and output only has one pin, the transmission rate is not high, and the parallel NOR/NAND Flash without multi-pin transmission has high speed. In order to overcome the limitation of slow speed of a standard SPI transmission mode, manufacturers add a two-wire transmission mode and a four-wire transmission mode through multiplexing SI, SO, WP and HOLD pins on the original basis. The transmission rate can be increased by a factor of 2/4. Such as the pin diagram of SPI NOR/NAND Flash shown in fig. 1.
Where VCC and GND are used for power. CS # is the chip select pin. SCLK is the SPI clock signal. SI is an input signal in the standard SPI single line mode, and SO is an output signal in the standard SPI single line mode. SIO0 and SIO1 are input and output signals in a two-wire mode, SIO0-SIO3 are input and output signals in a four-wire mode, and WP # and HOLD # are write protect and suspend function pins in a single-wire and two-wire mode.
Generally, if an embedded system code needs to support a new Flash, the code needs to be written according to a device manual provided by a manufacturer, and the manufacturer and a device identifier are read first, and the transmission mode supported by the chip is judged according to the identifier. And finally, the new Flash is supported by updating the firmware version. The method is not beneficial to the management and control of the product software version, and the version is required to be released again every time a new Flash is added. In order to reduce release of the version, a set of default parameters is built in to support the unknown Flash in a standard SPI transmission mode. However, in the standard SPI mode, the maximum transmission speed of Flash cannot be achieved by using the multi-line transmission mode, which results in slow system start, slow response, and the like
Disclosure of Invention
The invention aims to provide an SPI NOR and NAND Flash memory transmission mode identification method, which utilizes a 2-line/4-line transmission command commonly used among manufacturers to identify the transmission mode supported by a chip through specific code judgment logic so as to achieve the purpose of automatically adapting to the Flash chip transmission mode and solve the problems provided in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme:
an SPI NAND flash memory transmission mode identification method comprises the following specific identification steps:
step 1: a 4-line mode of the SPI NAND flash needs to be started; after the 4-line mode is started; WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission; at present, each manufacturer adopts the 0 th bit of a function Register (Feature Register)0xb0 as the start bit of a four-wire;
step 2: generating a random number to a buffer 0;
and step 3: loading cache 0 data to a Flash internal write cache using a standard SPI single line mode load command (0x 02); write operations are not used to prevent Flash content from being destroyed;
and 4, step 4: read page 0 data to cache 1 using a general 4-line read command (0x6 b);
and 5: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 4-line reading operation; jumping to the step 8 to continue execution;
step 6: read page 0 data to cache 1 using a general 2-line read command (0x3 b);
and 7: and comparing whether the contents of the cache 0 and the cache 1 are the same, and if so, representing that the Flash supports 2-line reading operation. Otherwise, the Flash only supports single-line reading operation;
and 8: generating random data to a buffer 0;
and step 9: loading cache 0 data to a Flash internal cache by using a general 4-line loading command (0x32), and not executing a writing operation; therefore, the data content in the Flash cannot be damaged;
step 10: read page 0 data to cache 1 using a general 4-line read command (0x6b) (Flash that normally supports 4-line write operations necessarily supports 4-line read operations, so this step employs a 4-line read command rather than a standard single-line read command);
step 11: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if the contents of the cache 0 and the cache 1 are the same, representing that Flash supports 4-line write-in operation; otherwise Flash only supports single line write operations.
In addition, Flash does not have a 2-line writing function at present, so that Flash is not judged any more.
An SPI NOR flash memory transmission mode identification method comprises the following specific identification steps:
step 1: a 4-wire mode of the SPI NOR Flash needs to be started; after the 4-line mode is started, WP and HOLD pins of the Flash are used for IO2 and IO3 in 4-line transmission; some manufacturers do not need specific commands, and some need to send a universal command 0xb 7;
step 2: reading the flash specific address content to cache 0 using a standard SPI single line mode read command (0x0 b);
and step 3: read page 0 data to cache 1 using a general 4-line read command (0x6 b);
and 4, step 4: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 4-line reading operation; jumping to step 7 to continue execution;
and 5: read page 0 data to cache 1 using a general 2-line read command (0x3 b);
step 6: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 2-line reading operation; otherwise, the Flash only supports single-line reading operation;
and 7: because SPI Nor Flash does not have internal cache to be used for loading data, whether the automatic identification write-in supports 4 lines can be judged only by actually writing data; therefore, an unused data block needs to be found for testing, so that whether a spare data block is used for testing or not needs to be judged, if yes, the testing can be continued, otherwise, the data block can be identified only according to single-line writing;
and 8: erasing the specific address data block;
and step 9: generating random data to a buffer 0;
step 10: write cache 0 data to Flash internal cache using a general 4-line write command (0x 32);
step 11: read page 0 data to cache 1 using a general 4-line read command (0x6b) (Flash that normally supports 4-line write operations necessarily supports 4-line read operations, so this step employs a 4-line read command rather than a standard single-line read command);
step 12: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if the contents of the cache 0 and the cache 1 are the same, representing that Flash supports 4-line write-in operation; otherwise Flash only supports single line write operations.
Compared with the prior art, the invention has the advantages that:
1. all SPI NOR/NAND Flash supported transmission modes can be automatically identified.
2. The unknown new Flash can be supported without changing the software version, and the performance of the Flash can be maximized.
Drawings
FIG. 1 is a pin diagram of SPI NOR/NAND Flash.
FIG. 2 is a flow chart of the SPI NAND Flash automatic identification in the present invention.
FIG. 3 is a flow chart of SPI NOR Flash automatic identification in the present invention.
Detailed Description
The technical solution of the present patent will be described in further detail with reference to the following embodiments.
Referring to fig. 2, a method for identifying SPI NOR and NAND flash transmission modes includes the following specific steps:
step 1: a 4-line mode of the SPI NAND flash needs to be started; after the 4-line mode is started; WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission; currently, each manufacturer uses the 0 th bit of the function Register (Feature Register)0xb0 as the start bit of the four-line.
Step 2: a random number is generated to buffer 0.
And step 3: loading cache 0 data to a Flash internal write cache using a standard SPI single line mode load command (0x 02); write operations are not used to prevent Flash content from being corrupted.
And 4, step 4: page 0 data is read into cache 1 using the general 4-line read command (0x6 b).
And 5: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 4-line reading operation; and jumping to the step 8 to continue the execution.
Step 6: page 0 data is read into cache 1 using the general 2-line read command (0x3 b).
And 7: and comparing whether the contents of the cache 0 and the cache 1 are the same, and if so, representing that the Flash supports 2-line reading operation. Otherwise, the Flash only supports single-line reading operation.
And 8: generating random data into cache 0
And step 9: loading cache 0 data to a Flash internal cache by using a general 4-line loading command (0x32), and not executing a writing operation; thus, the data content in Flash cannot be damaged.
Step 10: page 0 data is read to cache 1 using a general purpose 4-line read command (0x6b) (Flash that normally supports 4-line write operations necessarily supports 4-line read operations, so this step employs a 4-line read command rather than a standard single-line read command).
Step 11: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if the contents of the cache 0 and the cache 1 are the same, representing that Flash supports 4-line write-in operation; otherwise Flash only supports single line write operations.
In addition, Flash does not have a 2-line writing function at present, so that Flash is not judged any more.
An SPI NOR flash memory transmission mode identification method comprises the following specific identification steps:
step 1: a 4-wire mode of the SPI NOR Flash needs to be started; after the 4-line mode is started, WP and HOLD pins of the Flash are used for IO2 and IO3 in 4-line transmission; some manufacturers do not need specific commands, and some need to send a universal command 0xb 7;
step 2: reading the flash specific address content to cache 0 using a standard SPI single line mode read command (0x0 b);
and step 3: read page 0 data to cache 1 using a general 4-line read command (0x6 b);
and 4, step 4: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 4-line reading operation; jumping to step 7 to continue execution;
and 5: read page 0 data to cache 1 using a general 2-line read command (0x3 b);
step 6: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 2-line reading operation; otherwise, the Flash only supports single-line reading operation;
and 7: since SPI NOR Flash has no internal cache for loading data. Whether 4 lines of data are supported to be automatically identified and written can be judged only by actually writing data; therefore, an unused data block needs to be found for testing, so that whether a spare data block is used for testing or not needs to be judged, if yes, the testing can be continued, otherwise, the data block can be identified only according to single-line writing;
and 8: erasing the specific address data block;
and step 9: generating random data to a buffer 0;
step 10: write cache 0 data to Flash internal cache using a general 4-line write command (0x 32).
Step 11: read page 0 data to cache 1 using a general 4-line read command (0x6b) (Flash that normally supports 4-line write operations necessarily supports 4-line read operations, so this step employs a 4-line read command rather than a standard single-line read command);
step 12: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if the contents of the cache 0 and the cache 1 are the same, representing that Flash supports 4-line write-in operation; otherwise Flash only supports single line write operations.
Although the preferred embodiments of the present patent have been described in detail, the present patent is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present patent within the knowledge of those skilled in the art.
Claims (4)
1. A SPI NAND Flash memory transmission mode identification method is characterized in that an SPI NAND Flash read mode or write mode can be automatically identified;
the method for automatically identifying the SPI NAND Flash read mode comprises the following steps: writing data in by using an internal cache space of the SPI NAND Flash in a standard single-line writing mode, acquiring cache data by using a 4-line and 2-line reading mode, and judging whether the SPI NAND Flash supports a 2-line and 4-line reading mode by comparing whether the data contents are the same or not;
the method for automatically identifying the SPI NAND Flash write mode comprises the following steps: and (3) loading data to a cache by 4 lines by using the internal cache space of the SPI NAND Flash, reading the cache by a 4-line reading mode, and judging whether the SPI NAND Flash supports a 4-line writing mode by comparing whether the data contents are the same or not.
2. A SPI NOR Flash memory transmission mode identification method is characterized in that an SPI NOR Flash memory reading mode or writing mode can be automatically identified;
the method for automatically identifying the SPI NOR Flash read mode comprises the following steps: reading data in a standard single-wire reading mode, reading data at the same position in a 4-wire and 2-wire reading mode, and judging whether the SPI NOR Flash supports a 2-wire and 4-wire reading mode by comparing whether the data contents are the same;
the method for automatically identifying the SPI NOR Flash write mode comprises the following steps: a group of random data is written in by a 4-line writing mode by utilizing the spare and unnecessary data blocks of the system, the data is read by a 4-line reading mode, and whether the SPI NOR Flash supports a 4-line writing mode is judged by comparing whether the data contents are the same or not.
3. The SPI NAND flash transmission mode identification method of claim 1, characterized in that the specific identification steps are as follows:
step 1: a 4-line mode of the SPI NAND flash needs to be started; after the 4-line mode is started; WP and HOLD pins of Flash are used for IO2 and IO3 in 4-wire transmission;
step 2: generating a random number to a buffer 0;
and step 3: loading cache 0 data to a Flash internal write cache by using a standard SPI single line mode loading command 0x 02; write operations are not used to prevent Flash content from being destroyed;
and 4, step 4: read page 0 data to cache 1 using the general 4-line read command 0x6 b;
and 5: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 4-line reading operation; jumping to the step 8 to continue execution;
step 6: read page 0 data to cache 1 using the general 2-line read command 0x3 b;
and 7: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 2-line reading operation; otherwise, the Flash only supports single-line reading operation;
and 8: generating random data to a buffer 0;
and step 9: loading cache 0 data to a Flash internal cache by using a general 4-line loading command 0x32, and not executing a writing operation; therefore, the data content in the Flash cannot be damaged;
step 10: read page 0 data to cache 1 using the general 4-line read command 0x6 b;
step 11: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if the contents of the cache 0 and the cache 1 are the same, representing that Flash supports 4-line write-in operation; otherwise Flash only supports single line write operations.
4. The SPI NOR flash transmission mode identification method of claim 2, characterized in that the specific identification steps are as follows:
step 1: a 4-wire mode of the SPI NOR Flash needs to be started; after the 4-line mode is started, WP and HOLD pins of the Flash are used for IO2 and IO3 in 4-line transmission;
step 2: reading the content of the flash specific address to a cache 0 by using a standard SPI single-line mode read command 0x0 b;
and step 3: read page 0 data to cache 1 using the general 4-line read command 0x6 b;
and 4, step 4: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 4-line reading operation; jumping to step 7 to continue execution;
and 5: read page 0 data to cache 1 using the general 2-line read command 0x3 b;
step 6: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if so, representing that the Flash supports 2-line reading operation; otherwise, the Flash only supports single-line reading operation;
and 7: since the SPI NOR Flash does not have an internal cache for loading data, the actual data writing can be judged only if the automatic identification of whether the writing supports 4 lines is realized; therefore, an unused data block needs to be found for testing, so that whether a spare data block is used for testing or not needs to be judged, if yes, the testing can be continued, otherwise, the data block can be identified only according to single-line writing;
and 8: erasing the specific address data block;
and step 9: generating random data to a buffer 0;
step 10: writing the cache 0 data to the Flash internal cache by using a general 4-line write command 0x 32;
step 11: read page 0 data to cache 1 using the general 4-line read command 0x6 b;
step 12: comparing whether the contents of the cache 0 and the cache 1 are the same or not, and if the contents of the cache 0 and the cache 1 are the same, representing that Flash supports 4-line write-in operation;
otherwise Flash only supports single line write operations.
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2021
- 2021-07-04 CN CN202110754025.0A patent/CN113326215B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20140269065A1 (en) * | 2013-03-13 | 2014-09-18 | Winbond Electronics Corporation | NAND Flash Memory |
| CN105630405A (en) * | 2015-04-29 | 2016-06-01 | 上海磁宇信息科技有限公司 | Storage system and reading/writing method adopting storage system |
| CN106874224A (en) * | 2017-02-17 | 2017-06-20 | 杭州朔天科技有限公司 | The multi-thread SPI Flash controllers of automatic transporting and adaptation device |
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