JP2001290764A - Data transfer system device and its data transferring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a data transfer system device and its data transferring method capable of avoiding the conflict of a bus connecting a master unit and a slave unit. SOLUTION: When the slave unit 3 transfers data to the master unit 2 through a data line 4, a data transfer end deciding part 13 counts the number of bytes of transferred data, judges whether or not the data transfer has been finished by comparing the number of counted bytes with the number of transfer bytes stored in a register 31 from the master unit 2 and also releases the data line 4 when it is judged that the data transfer has been finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a method data transfer system apparatus and the data transfer serial data is transferred between the master and slave devices, data using the I ² C bus, especially between LSI The present invention relates to a data transfer system device for performing serial transfer and a data transfer method thereof.

[0002]

2. Description of the Related Art Conventionally, there has been a serial transfer system device 100 for serially transferring data between a master device 101 and a slave device 102 as shown in FIG.
The master device 101 and the slave device 102 are connected by a so-called I ² C bus including a data line 103 for performing data transfer and a clock line 104 for performing clock transfer.

FIG. 5 shows a data transfer format when data is transferred from the slave device 102 to the master device 101, and shows a case where the master device 101 reads data from the slave device 102 immediately after the first byte. I have. In FIG. 5, the hatched portion indicates a data transfer portion from the master device 101 to the slave device 102, and the other portions indicate a data transfer portion from the slave device 102 to the master device 101. .

A master device 101 is a slave device 102
Start condition S for starting communication with the slave device 1
02 and outputs the address of the slave device 102, and then outputs data R / W # indicating the data transfer direction. The address is composed of 7 bits, and 1-bit data R / W # follows 8th bit of 1-byte data. Also,
When the data R / W # is "0", data transfer is performed from the master device to the slave device, and the data R / W #
Is "1", data is transferred from the slave device to the master device.

[0005] Further, after each byte data, an acknowledgment indicated by "A" or "A #" follows, and the acknowledgment indicated by "A #" is a signal level of the acknowledgment indicated by "A". Is the inverted signal level. For example,
If the acknowledgment indicated by “A” is at a low level, “A”
The confirmation response indicated by “#” is at the High level. When the reading of the desired data from the slave device 102 is completed, the master device 101 outputs a data transfer completion response indicated by “A #” to the slave device 102, and then stops the communication with the slave device 102. The condition P is output to the slave device 102, and the communication is completed.

[0006]

However, there has been a master device that does not output a response indicating that data transfer to the slave device has been completed to the slave device. Also, originally, a response indicating that the data transfer to the slave device 102 has been completed should be output from the master device 101.
In some cases, the response was not output due to the influence of noise or the like, or the response was not transmitted to the slave device 102 normally. In such a case, the slave device 102 cannot recognize the end of the data transfer from the master device 101, and the slave device 102 holds the data line 103 in order to perform the data transfer continuously to the master device 101. It remains as it is.

For example, when the slave device 102 holds the data line 103 at the Low level in order to continue data transfer to the master device 101, the master device 101 sends a stop condition P to the slave device 102 due to a bus conflict. Cannot be controlled, and the data line 103 cannot be controlled.
There is a problem that a problem occurs in communication with the C.02.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and enables the slave device to determine the end of data transfer without receiving a response from the master device to end the data transfer. Accordingly, an object of the present invention is to provide a data transfer system device for performing serial data transfer and a data transfer method thereof, which can avoid a conflict of a bus connecting a master device and a slave device.

[0009]

According to the present invention, there is provided a data transfer system device comprising: a serial device for connecting a master device and a slave device connected by a data line for performing data transfer and a clock line for performing clock transfer; In a data transfer system device that performs data transfer, a slave device includes a transfer byte number storage unit that stores the number of transfer data bytes during data transfer input from the master device, and a transfer byte number storage unit that stores data transferred between the master device. A data transfer end determining unit that counts the number of bytes and compares the counted number of bytes with the number of transfer bytes stored in the transfer byte number storage unit to determine whether to end the data transfer; and When it is determined that the data transfer is completed, the data line is released by setting the data line to a predetermined binary level. And a release unit, the data transfer termination determination unit, when the number of transfer bytes stored number of bytes counted and the transfer byte number storage unit match, is to determine the data transfer is completed.

More specifically, the data transfer end determining unit counts the number of bytes of the transferred data by counting the clock input from the master device via the clock line. .

In a data transfer method in a data transfer system device for performing serial data transfer between a master device and a slave device connected by a data line for performing data transfer and a clock line for performing clock transfer, The number of transfer data bytes output from the master device during data transfer is stored in the slave device, the number of bytes of data transferred between the master device and the slave device is counted by the slave device, and stored in the slave device. The slave device compares the number of transferred data bytes and the counted number of bytes with the slave device, and when the counted byte number matches the stored number of transferred bytes from the master device, the slave device determines that the data transfer is completed, The data line is set to a predetermined binary level by the slave device and released.

More specifically, the number of bytes of transferred data is counted by counting the clock input from the master device via the clock line by the slave device.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a schematic configuration diagram showing an example of a data transfer system device according to an embodiment of the present invention. In FIG. 1, a data transfer system device 1 performs serial data transfer between a master device 2 and a slave device 3, and a master device 2 and a slave device 3 are connected to a data line 4 for performing data transfer. are connected by a so-called I ² C bus is composed of a clock line 5 for clock transfer with. The data line 4 is pulled up to a power supply line Vdd by a pull-up resistor R1, and the clock line 5 is pulled up to a power supply line Vdd by a pull-up resistor R2.

The slave device 3 includes an interface unit 11 for interfacing with the master device 2 via the data line 4 and the clock line 5, and an interface unit 1
1 and a control signal generation unit 12 for performing the operation control of the first control signal. Further, the slave device 3 counts the number of bytes of data transferred to the master device 2 via the data line and determines whether or not the data transfer has ended, and a data transfer end determining unit 13; The data processing unit 14 controls the operation of the interface unit 11, the control signal generation unit 12, and the data transfer end determination unit 13 based on data transferred from the master device 2. In FIG. 1, a data storage unit for storing data in the slave device 3 is omitted.

The interface unit 11 includes a data line 4
For interfacing with master device 2 via
Via the interface circuit 16 and the clock line 5
Clock interface for interfacing with master device 2
And a data interface.
The circuit 16 and the clock interface circuit 17 ^Two
It has a C interface circuit. Data interface
The source circuit 16 includes a buffer 21 and an N-channel MOS transistor.
Transistor (hereinafter referred to as NMOS transistor) 22
And the clock interface circuit 17
Consists of a buffer 23 and an NMOS transistor 24
Have been.

The data line 4 is connected to the data transfer end determination unit 13 and the data processing unit 14 via a buffer 21 of the data interface circuit 16, and the clock line 5 is controlled via a buffer 23 of the clock interface circuit 17. The signal generation unit 12, the data transfer end determination unit 13, and the data processing unit 14 are connected to each other. The NMOS transistor 22 of the data interface circuit 16 has a drain and a source connected between the data line 4 and the ground, and a gate connected to the control signal generator 1.
2 and the operation is controlled by the control signal generator 12. The NMO of the clock interface circuit 17
The drain and source of the S transistor 24 are connected between the clock line 5 and the ground, and the gate is connected to the data processing unit 14. The operation of the S transistor 24 is controlled by the data processing unit 14.

Further, the data processing unit 14 controls the operation of the control signal generation unit 12 and the data transfer end determination unit 13 based on the data input from the data line 4 and the clock input from the clock line 5. Further, the data transfer end determination unit 13 outputs a result of the determination as to whether the data transfer has been completed to the control signal generation unit 12.

The clock transferred via the clock line 5 is normally transferred from the master device 2 to the slave device 3 and is not transferred from the slave device 3 to the master device 2. Therefore, a low-level signal is input from the data processing unit 14 to the gate of the NMOS transistor 24 in the clock interface circuit 17, and the NMOS transistor 24 is off. However, the data processing unit 14 may turn on the NMOS transistor 24 to adjust the clock signal input from the master device 2. The clock signal output from the master device 2 to the clock line 5 is input to the control signal generation unit 12, the data transfer end determination unit 13, and the data processing unit 14 via the buffer 23.

When data is transferred from the master device 2 to the slave device 3, the data processing unit 14
2, the NMOS transistor 22 of the data interface circuit 16 is turned off, and the data output from the master device 2 to the data line 4 is input to the data processing unit 14 via the buffer 21. When data is transferred from the slave device 3 to the master device 2, the data processing unit 1
4 outputs read data to the control signal generator 12, and the control signal generator 12 switches the NMOS transistor 22 according to the input read data to change the potential level of the data line 4. Thus, data transfer is performed from the slave device 3 to the master device 2.

FIG. 2 is a waveform diagram showing an example of data transfer performed between the master device 2 and the slave device 3.
The data transfer performed between the master device 2 and the slave device 3 will be described with reference to FIG. In FIG. 2,
The data signal transferred via the data line 4 is SD
A, a clock signal SCL transferred via the clock line 5.

When data is transferred between the master device 2 and the slave device 3, first, the master device 2
Outputs a “start” condition (hereinafter referred to as a start condition) indicating that the clock signal SCL is set to the high level and the data signal SDA is started to start data transfer. When the data transfer is completed, master device 2 transmits clock signal SCL.
To a high level, and also raises the data signal SDA to output an “end” condition (hereinafter referred to as a stop condition) indicating that the data transfer is ended to the slave device 3.

As described above, when the master device 2 indicates the start condition and the stop condition to the slave device 3, the master device 2 always sets the clock signal SCL to the high level. Accordingly, the master device 2 and the slave device 3 perform data transfer by changing the signal level of the data signal SDA when the clock signal SCL is at the low level.

After the master device 2 outputs the stop condition to the slave device 3, the master device 2 stores a 7-bit data indicating a location where data to be read from the slave device 3 is stored or a location where data is to be stored in the slave device 3. Output address data. Subsequently, the master device 2
1-bit data R / W #, which indicates whether data is to be written to or read from the slave device 3, that is, indicates the data transfer direction, is output to the data line 4. In this way, a total of one byte of data is output to the slave device 3 via the data line 4. When writing data to the slave device 3, the master device 2 outputs data R / W # of low level, that is, “0”, and when reading data from the slave device 3, high level, that is, data R / W # of “1”. / W #
Is output.

The data processing unit 14 receives the
When the byte data is input, the control signal generating unit 12 outputs High to the gate of the NMOS transistor 22.
Outputs a low-level signal and sends a low-level acknowledgment ACK
Is output to the master device 2. When the input data R / W # is at the High level, the data processing unit 14 outputs the data stored at the specified address to the control signal generation unit 12, and the control signal generation unit 12 sends the data to the NMOS transistor 22. Is output to the data line 4 via.

On the other hand, when the input data R / W # is at the low level, the data processing unit 14 turns off the NMOS transistor 22 to the control signal generation unit 12 and transmits the data input from the master device 2. Store at the specified address. When reading data from the slave device 3, the master device 2 sends a low-level acknowledgment ACK every time 1-byte data is input to the data line 4.
To the slave device 3 via the. When writing data to the slave device 3, the slave device 3 turns on the NMOS transistor 22 for the control signal generation unit 12 every time 1-byte data is input, and sends a low-level acknowledgment ACK to the data. Output to master device 2 via line 4.

When reading data from the slave device 3, the master device 2 transmits the requested data to the slave device 3.
When all the data is transferred from the slave device, a high-level response ACK indicating that the data transfer has been completed is output to the slave device 3, and the data processing unit 14 recognizes the end of the data transfer by receiving the response ACK. It is possible,
An NMOS transistor 22 for the control signal generation unit 12
Off. Conversely, when writing data to the slave device 3, a response indicating that the data transfer has been completed is output from the slave device 3 to the master device 2. Finally, the master device 2 outputs a stop condition to the slave device 3 and the communication with the slave device 3 ends.

In such a configuration, the master device 2
Causes the data indicating the number of bytes of the transfer data to be written into a predetermined register 31 of the slave device 3 when performing data transfer with the slave device 3. Next, the data processing unit 14
When 1-byte data for reading data is input from the master device 2, the data transfer end determination unit 13
, The number of bytes of data transferred to the master device 2 via the data line 4 is counted. The data transfer end determination unit 13 counts the number of transfer data based on a clock signal input via the clock line 5.

The data transfer end determining unit 13 compares the counted number of transfer data with the number of transfer bytes stored in the register 31, and sets a predetermined transfer byte match flag F to the control signal generator 12 when they match. I do. When the transfer byte match flag F is set, the control signal generator 12 turns off the NMOS transistor 22 and releases the data line 4. On the other hand, when the transfer byte match flag F is not set from the data transfer end determination unit 13, the control signal generation unit 12 generates a control signal for the NMOS transistor according to the read data input from the data processing unit 14. Output.

FIG. 3 shows that the slave device 3 and the master device 2
FIG. 4 is a flowchart showing an operation example when data is transferred to the master device 2 with reference to FIG. 3, and a flow of operations of each unit when data is transferred from the slave device 3 to the master device 2 will be described. In FIG. 3, the master device 2 writes a device ID in the data processing unit 14 of the slave device 3 (step S1), and the data processing unit 14 checks whether the written device ID matches a preset ID. It is checked (step S2) whether or not they match (NO), and the process returns to step S1.

In step S2, if they match (Y
ES), the master device 2 causes the slave device 3 to write the number of transfer bytes to the register 31 of the data processing unit 14 (step S3). Next, the data processing unit 14 transfers the designated data to the master device 2 via the data line 4 and causes the data transfer end determination unit 13 to count the number of transfer bytes (Step S).
4). The data transfer end determination unit 13 compares the counted number of bytes with the number of transfer bytes stored in the register 31 to check whether they match (step S5). If they do not match (NO), Returning to step S4, if they match (YES), the transfer byte match flag F is set in the control signal generator 12 (step S6).

When the transfer byte match flag F is set, the control signal generator 12 turns off the NMOS transistor 22 to release the data line 4 (step S).
7) After that, the master device 2 outputs a stop condition to the slave device 3 (step S8), and the data transfer performed between the master device 2 and the slave device 3 ends.

As described above, when data is transferred from the slave device 3 to the master device 2 via the data line 4 in the data transfer system device according to the present embodiment, the data transfer end determination unit 13 determines the number of bytes of the transfer data. To determine whether the data transfer has been completed,
If it is determined that the data transfer has been completed,
Was released. Thus, even when a response to the end of the data transfer cannot be obtained from the master device, the end of the data transfer can be determined on the slave device side, and a conflict of a bus connecting the master device and the slave device can be avoided.

In the above embodiment, the case where data is transferred from the slave device to the master device has mainly been described as an example. However, the present invention is not limited to this, and data transfer from the master device to the slave device is performed. Needless to say, the present invention can be applied to such a case.

[0034]

As is apparent from the above description, according to the data transfer system of the present invention, when data transfer is performed between the master device and the slave device via the data line, the data transfer end determination unit is provided. The number of bytes of the transfer data is counted to determine whether or not the data transfer is completed. If the data transfer end determination unit determines that the data transfer is completed, the data line release unit releases the data line. I did it. From this, even when a response of the data transfer end is not obtained from the master device, the slave device side can determine the end of the data transfer and release the data line, and the bus connecting the master device and the slave device can be used. Conflicts can be avoided.

Specifically, the data transfer end determination unit counts the number of bytes of the transferred data by counting the clock input from the master device via the clock line. From
The number of bytes of data transferred to and from the master device can be easily counted.

Further, according to the data transfer method in the data transfer system device of the present invention, when data is transferred between the master device and the slave device via the data line, the number of bytes of the transfer data is determined by the slave device. It is determined whether or not the data transfer is completed by counting, and when it is determined that the data transfer is completed, the data line is released. From this, even when a response of the data transfer end is not obtained from the master device, the slave device side can determine the end of the data transfer and release the data line, and the bus connecting the master device and the slave device can be used. Conflicts can be avoided.

More specifically, since the number of bytes of transferred data is counted by counting the clock input from the master device via the clock line, the number of bytes of the transferred data is counted. The number of bytes of transferred data can be easily counted.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating an example of a data transfer system device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an example of data transfer performed between a master device 2 and a slave device 3 in FIG.

FIG. 3 is a flowchart showing an operation example when data is transferred from a slave device 3 to a master device 2 in FIG.

FIG. 4 is a schematic configuration diagram showing an example of a conventional data transfer system device.

FIG. 5 is a diagram showing a slave device 102 to a master device 1 shown in FIG. 4;
FIG. 11 is a diagram showing an example of a data transfer format when data is transferred to 01.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data transfer system device 2 master device 3 slave device 4 data line 5 clock line 11 interface unit 12 control signal generation unit 13 data transfer end determination unit 14 data processing unit 16 data interface circuit 17 clock interface circuit 31 register

Claims (4)

[Claims] 1. A data transfer system device for performing serial data transfer between a master device and a slave device connected by a data line for performing data transfer and a clock line for performing clock transfer, wherein the slave device is A transfer byte number storage unit for storing the number of transfer data bytes at the time of data transfer input from the master device; and counting the number of bytes of data transferred between the master device and the counted byte number. And a data transfer end determining unit that determines the end of data transfer by comparing the transfer byte number stored in the transfer byte number storage unit with the transfer byte number. A data line release unit for releasing the data line to a predetermined binary level, and ending the data transfer. Tough, when the number of transfer bytes stored number of bytes counted and the transfer byte number storage unit match, the data transfer system apparatus and determines that the data transfer is completed. 2. The data transfer end determination unit counts the number of bytes of transferred data by counting clocks input from a master device via a clock line. Item 2. The data transfer system device according to item 1. 3. A data transfer method in a data transfer system device for performing serial data transfer between a master device and a slave device connected by a data line for performing data transfer and a clock line for performing clock transfer, The number of transferred data bytes at the time of data transfer output from the master device is stored in the slave device, and the number of bytes of data transferred between the master device and the slave device is counted by the slave device. The number of transfer data bytes stored in
The slave device compares the counted number of bytes with the slave device. If the counted number of bytes matches the stored number of bytes transferred from the master device, the slave device determines that data transfer has been completed. A data transfer method characterized in that the data is released after being set to a binary level. 4. The data according to claim 3, wherein the number of bytes of the transferred data is counted by counting the clock input from the master device via the clock line by the slave device. Transfer method.