WO2022126893A1

WO2022126893A1 - Bridging module for serdes interface

Info

Publication number: WO2022126893A1
Application number: PCT/CN2021/082547
Authority: WO
Inventors: 袁磊; 宣学雷; 李宁
Original assignee: 深圳市紫光同创电子有限公司
Priority date: 2020-12-16
Filing date: 2021-03-24
Publication date: 2022-06-23
Also published as: KR20230086788A; CN112765066A; CN112765066B

Abstract

Provided is a bridging module for a SerDes interface. The bridging module comprises write-in control, read-out control, and a Be_FIFO sub-module, wherein the write-in control comprises a channel control sub-module, a first selector, a compensation frequency difference deletion sub-module and a second selector which are cascaded; and the read-out control comprises a channel read control sub-module, a third selector, a fourth selector, a compensation frequency difference coverage sub-module, a fifth selector and a sixth selector. By means of the bridging module for a SerDes interface in the present application, the processing delay of data is reduced, and the transmission performance of the whole SerDes port is improved.

Description

Bridge module for serdes interface

【Technical field】

The present application relates to the technical field of integrated circuit chips, and in particular, to a bridge module for a serdes interface.

【Background technique】

As a mainstream time-division multiplexing, point-to-point serial communication technology, the serdes interface on an FPGA (Field Programmable Gate Array, programmable gate array) can achieve a higher data rate through fewer pins, satisfying the Data throughput requirements in multiple protocol scenarios such as PCIE and SATA.

As an important part of serdes, the PCS rx part is responsible for receiving serial-to-parallel converted data, decoding the aligned data, and supporting multi-channel data alignment and frequency error compensation. Therefore, the quality of the data processing delay of the PCS rx part has a great impact on the data transmission performance of the entire serdes.

In the PCS rx part of the prior art, functions such as multi-channel data alignment are implemented in each individual module, and whether to support related functions is selected through multiple mux. In order to complete the temporary storage of data and clock domain conversion, each module instantiates the afifo module. Since each module starts the data writing operation from the address of half the afifo depth, and starts the data reading from the '0' address, when multiple functions are enabled, the sequential processing of the data causes the delay to accumulate gradually, and the overall processing delay is over large, which is not conducive to the improvement of the overall serdes data processing performance.

【Contents of application】

The purpose of this application is to provide a bridge module for serdes interface.

In order to achieve the above object, the application provides a bridge module for serdes interface, including write control, read control and Be_fifo submodule;

The write control includes a cascaded channel control sub-module, a first selector, a compensation frequency difference deletion sub-module and a second selector;

The channel control sub-module is used to receive decoded data and afifo write enable, and output the processed write data and afifo write enable; the first selector is used to receive the output of the channel control sub-module. Write data and afifo write enable and receive decoded data and afifo write enable, and select output; the compensation frequency difference deletion sub-module is used to receive the signal output by the first selector, and output the processed write input data and afifo write enable; the second selector is used to receive the signal output by the compensation frequency difference deletion sub-module and the signal output by the first selector, and select and output to afifo;

The readout control includes a channel readout control submodule, a third selector, a fourth selector, a frequency difference compensation submodule, a fifth selector and a sixth selector;

The channel read control submodule is used to receive the afifo read enable, the data water level status information in the current channel afifo, and the status information of the slave channel, and output the processed read enable signals of all channels; the third selector, Used to receive all channel read enable signals and received signals output by the channel read control sub-module, and select the output; the fourth selector is used to receive the afifo read enable and receive the output of the third selector. signal, and select the output; the compensation frequency difference complement sub-module is used to receive the signal output by the fourth selector, and output the processed signal, and receive the read data of afifo, and output the processed complement signal; the fifth selector is used to receive the signal output by the compensation frequency difference compensation sub-module and the signal output by the fourth selector, and select and output to afifo; the sixth selector is used for Receive the read data of the afifo and the complement signal output by the compensation frequency difference complement sub-module, and select the output.

Preferably, the control end of the first selector and the control end of the second selector receive the first mode configuration signal.

Preferably, the control end of the fourth selector, the control end of the fifth selector and the control end of the sixth selector receive the first mode configuration signal; the control end of the third selector, A second mode configuration signal is received.

Preferably, the bridge module further includes a bypass control sub-module and a seventh selector;

The bypass control submodule is used to receive the decoded data and output the processed data;

The seventh selector is configured to receive the data output by the bypass control sub-module and the signal output by the sixth selector, and select and output the configuration output data and the data indication signal.

Preferably, the control end of the seventh selector receives a mode configuration signal.

Preferably, the bridge module further includes a state generating sub-module; the state generating sub-module is configured to receive the signal output by the sixth selector, and after processing, output the function control signal to the channel control sub-module.

Preferably, the state generation submodule is used to generate data alignment state information.

The beneficial effects of the present application are as follows: a bridge module for a serdes interface is provided, which reduces the data processing delay and improves the transmission performance of the entire serdes port.

【Description of drawings】

FIG. 1 is a structural diagram of a bridge module according to an embodiment of the present application.

【Detailed ways】

In order to make the purpose, technical solutions and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present specification, but not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification. It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict.

The terms "first", "second" and "third" in the description and claims of the present application and the above drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

As shown in FIG. 1 , an embodiment of the present application provides a bridge module rx_bridge_unit for a Serdes (SERializer/DESerializer, serializer/deserializer) interface. The bridge module rx_bridge_unit includes a write control wr_ctrl, a read control rd_ctrl and a Be_fifo (afifo) submodule.

Among them, the Be_fifo (first in first out, first-in, first-out queue) sub-module includes afifo (memory module), and the Be_fifo sub-module is used to output the data water level status information fifo_state of afifo according to the data water level in the afifo.

The write control wr_ctrl includes a cascaded channel control submodule cb_ctrl, a first selector X1, a compensation frequency difference deletion submodule ctc_del_ctrl and a second selector X2;

The channel control sub-module cb_ctrl is used to receive the decoded data data_after_decoder and afifo write enable rxfifo_wr_en, and output the processed write data cb_wr_start, afifo write enable mcb_dout;

The first selector X1 is used to receive the write data cb_wr_start and afifo write enable mcb_dout and receive decoded data data_after_decoder and aFIFO write enable rxfifo_wr_en output by the channel control submodule cb_ctrl, and select the output;

Since the judgment conditions of the first selector X1 are the same, the decoded data data_after_decoder and the afifo write enable rxfifo_wr_en received by the first selector X1 in the figure are represented by a line; The input and output data and enable signal lines are represented by one line, and the data and enable signals on the same line are distinguished by ",".

The compensation frequency difference deletion sub-module ctc_del_ctrl is used to receive the write data ctc_din and afifo write enable ctc_wr_en output by the first selector X1, and output the processed write data ctc_dout and afifo write enable ctc_fifo_wr_start;

The second selector X2 is used to receive the signal output by the compensation frequency difference deletion sub-module ctc_del_ctrl and receive the signal write data ctc_din (Mcb-dout) and afifo write enable ctc_wr_en (Mcb fifo_wr_start) output by the first selector X1, and Select output write data wr_ctrl_dout and afifo write enable fifo_wr_start to afifo.

The readout control rd_ctrl includes a channel read control submodule cb_rden_ctrl, a third selector X3, a fourth selector X4, a frequency difference compensation submodule ctc_add_ctrl, a fifth selector X5 and a sixth selector X6.

The channel read control sub-module cb_rden_ctrl is used to receive the afifo read enable rx_fifo_rden, the data water level status information fifo_state in the current channel (main channel) afifo, the state information fifo_state_cin of the slave channel, and output the processed read enable signal master_cb_rden for all channels;

The third selector X3 is used to receive all channel read enable signals master_cb_rden output by the channel read control sub-module cb_rden_ctrl and receive the cascaded signal cb_rden_cin, and select the output; wherein, the cascaded signal cb_rden_cin is used to transmit the afifo output by the main channel Read enable signal to ensure that all channel data are read at the same time;

The fourth selector X4 is used to receive the afifo read enable rx_fifo_rden and receive the signal cb_rden output by the third selector X3, and select the output;

Compensation frequency difference compensation submodule ctc_add_ctrl, for receiving the signal ctc_fifo_rden_in output by the fourth selector X4, and outputting the processed signal ctc_fifo_rden, and receiving the readout data of afifo, and outputting the processed complement signal ctc_add_dout;

The fifth selector X5 is used to receive the signal ctc_fifo_rden output by the compensation frequency difference compensation sub-module ctc_add_ctrl and receive the signal output by the fourth selector X4, and select and output the read enable signal fifo_rd_en to afifo; read enable signal fifo_rd_en;

The sixth selector X6 is used to receive the read data of afifo and the complement signal ctc_add_dout output by the compensation frequency difference complement sub-module ctc_add_ctrl, and select the output.

Among them, the third selector X3, according to the configuration of the master and slave channels, the master channel selects the afifo read enable signal master_cb_rden generated by this channel; the slave channel selects the cascaded signal cb_rden_cin. cb_rden is the afifo read enable signal finally generated by the data alignment function to ensure that all channels start reading data from afifo at the same time.

Among them, the compensation frequency difference compensation sub-module ctc_add_ctrl inserts the special character skip pattern into the data read by afifo, and the signal ctc_fifo_rden is to pull down a cycle after a certain number of special character insertion operations to complete the frequency difference compensation of the data; The difference complement sub-module ctc_add_ctrl inserts the special character skip pattern into the data read by afifo, and the complement signal ctc_add_dout is the data adjusted by the frequency difference compensation sub-module ctc_add_ctrl.

Among them, the channel read control sub-module cb_rden_ctrl of the main channel judges the received data water level status information fifo_state in the channel afifo and the data water level status information fifo_state_cin in the slave channel afifo. When the data water level status information of all channels displays the data in the channel When the water level reaches the specified state, the main channel channel read control sub-module cb_rden_ctrl transmits the externally received read enable rx_fifo_rden to the afifo of this channel, and starts the data read operation; at the same time, the cascade signal cb_rden_cout is transmitted to all slave channels, all slave channels The afifo read enable uses the cascaded transmission signal of the master channel to ensure that the master channel and the slave channel start reading afifo data at the same time to ensure data alignment.

Four channel lanes (0-3) are planned in the Serdes interface, and each channel lane uses its own bridge module rx_bridge_unit module; among them, the channel Lane 0 is set as the master channel, and the other channels are set as slave channels.

Further, the control terminal of the first selector X1 and the control terminal of the second selector X2 receive the first mode configuration signal cfg_rebridge_mode.

Further, the control terminal of the fourth selector X4, the control terminal of the fifth selector X5 and the control terminal of the sixth selector X6 receive the first mode configuration signal cfg_rebridge_mode. Further, the control end of the third selector X3 receives the second mode configuration signal cfg_rxbu_slave. The second mode configuration signal cfg_rxbu_slave is used to configure the state of the master and slave channels.

In one embodiment, as shown in FIG. 1 , the bridge module (rx_bridge_unit) further includes a bypass control submodule by_pass_ctrl and a seventh selector X7.

The bypass control sub-module by_pass_ctrl is used to receive the decoded data data_after_decoder and output the processed data by_pass_dout;

The seventh selector X7 is configured to receive the data by_pass_dout output by the bypass control sub-module by_pass_ctrl and receive the frequency difference adjusted output data ctc_dout output by the sixth selector X6, and select and output the configuration output data data_after_rxbu and the data indication signal data_vld_after_rxbu. Further, the control terminal of the seventh selector X7 receives the first mode configuration signal cfg_rebridge_mode.

The bridge module (rx_bridge_unit) also supports by_pass (bypass) selection, that is, by setting the bypass control submodule by_pass_ctrl, so that the internal Be_fifo submodule is not enabled, and the data is output only after the bypass control submodule by_pass_ctrl is sampled.

In one embodiment, as shown in FIG. 1 , the bridge module (rx_bridge_unit) further includes a status generation submodule mcb_status_gen.

The status generation sub-module mcb_status_gen is used to receive the signal output by the sixth selector X6, and after processing, output the function control signal channel bonding to the channel control sub-module cb_ctrl; to enable all channel data adjustment and special character apattern detection.

The status generation submodule mcb_status_gen is used to generate data alignment status information bonding_status; specifically, the status generation submodule mcb_status_gen obtains the data alignment status information bonding_status and data alignment status information through the built-in state machine according to the results of the special character apattern detection in all channel data. bonding_status is pulled high to indicate that all channel data alignment is complete.

In one embodiment, the first mode configuration signal cfg_rebridge_mode is used to configure the working mode of the bridge module rx_bridge_unit, and a plurality of sub-modules are enabled to complete the selected function.

When the bridging module rx_bridge_unit is configured to bridge fifo mode through the first mode configuration signal cfg_rebridge_mode, the bridging module rx_bridge_unit only enables the Be_fifo sub-module after receiving the decoded data data_after_decoder to complete the data bridging and compensate the phase difference. The read and write start addresses of the Be_fifo submodule can be configured as 3 and 1, respectively, so as to reduce the overall processing delay.

If the serdes interface needs the bridge module rx_bridge_unit to perform the alignment function between multi-channel data, the channel control sub-module cb_ctrl in each channel completes the data adjustment through the special character apattern in the data, and writes it to the Be_fifo sub-module for clock domain conversion. The main channel channel read control sub-module cb_rden_ctrl outputs fifo read enable to all channels according to the data water level status in the Be_fifo sub-modules of all channels to ensure data alignment. The alignment of multi-channel data is controlled by the state machine in the status generation sub-module mcb_status_gen of the main channel. Clock domain conversion often consumes most of the delay in the implementation of multi-channel alignment functions. The optimal configuration of fifo read and write start addresses can greatly improve this problem. Under different configurations of the first mode configuration signal cfg_rxbridge_mode, the read and write start addresses are different. For example, after the ctc function is enabled and nominal empty mode is configured, the read and write start addresses are both configured as 0.

When the bridging module rx_bridge_unit is configured to the clock compensation frequency difference mode ctc mode through the first mode configuration signal cfg_rebridge_mode, in order to minimize the delay caused by the data processing of the Be_fifo sub-module, the bridging module rx_bridge_unit supports the nominal empty mode configuration. In this mode, the compensation frequency difference deletion sub-module ctc_del_ctrl directly deletes the special characters skip pattern in the data, and writes the processed data into the Be_fifo sub-module for temporary storage and clock domain conversion. The ctc_add_ctrl submodule ctc_add_ctrl for the compensation frequency difference compensation of the read clock domain directly pulls down the read enable after the be_fifo submodule reads "empty", and indicates invalid data through the data indication signal data_vld_after_rxbu. In order to minimize the delay caused by the data clock domain conversion, the read and write start addresses of the Be_fifo sub-module are both configured as 0.

If you need to support multi-channel data alignment and frequency difference compensation functions at the same time, the bridge module rx_bridge_unit configures the required sub-modules through the first mode configuration signal cfg_rebridge_mode, and supports the normal empty mode selection under the clock compensation frequency difference ctc processing.

The embodiment of the present application also provides a PCS rx architecture comprising the above-mentioned bridge module rx_bridge_unit, the bridge module rx_bridge_unit is located before the transmission module gear unit, and the eighth selector X8 is also included between the bridge module rx_bridge_unit and the transmission module gear unit.

The bridge module rx_bridge_unit integrates the functions implemented by all Be_fifo submodules, and only one afifo is instantiated in the bridge module rx_bridge_unit. Due to the reduction in the use of afifo, when multiple functions are enabled, the processing delay caused by data temporary storage and clock domain conversion is greatly reduced.

The read and write start addresses of afifo in the bridge module rx_bridge_unit can be configured; in the case of ensuring normal data processing, the time delay caused by clock domain conversion can be minimized by changing the read and write start addresses. For the frequency difference compensation function, the bridge module rx_bridge_unit supports the nominal empty mode, that is, the afifo write and read data operations start from the '0' address, so as to ensure the lowest processing delay in the process.

Taking the valid data as 20bit as an example, and under the same data characteristics, the processing delay required by the PCS rx architecture of the prior art and the PCS rx architecture of the bridge module rx_bridge_unit used in the present application is 18rclks (read clock unit cycle); frequency difference compensation Under the function, the processing delay of the PCS rx architecture of the bridge module rx_bridge_unit in this application is 10rclks, which is lower than 22.5rclks in the prior art PCS rx architecture; under the functions of multi-channel data alignment and frequency difference compensation, the application uses the bridge module rx_bridge_unit. The processing latency of the PCS rx architecture is 24rclks, which is lower than 39.5rclks in the prior art PCS rx architecture.

The PCS rx architecture of the bridge module rx_bridge_unit used in this application requires lower processing delay and better transmission performance of serdes.

The above are only the embodiments of the present application. It should be pointed out that for those of ordinary skill in the art, improvements can be made without departing from the creative concept of the present application, but these belong to the present application. scope of protection.

Claims

A bridge module for serdes interface, characterized in that it comprises write control, read control and Be_fifo submodule;

The write control includes a cascaded channel control sub-module, a first selector, a compensation frequency difference deletion sub-module and a second selector;

The channel control sub-module is used to receive decoded data and afifo write enable, and output the processed write data and afifo write enable; the first selector is used to receive the output of the channel control sub-module. Write data and afifo write enable and receive decoded data and afifo write enable, and select output; the compensation frequency difference deletion sub-module is used to receive the signal output by the first selector, and output the processed write input data and afifo write enable; the second selector is used to receive the signal output by the compensation frequency difference deletion sub-module and the signal output by the first selector, and select and output to afifo;

The readout control includes a channel readout control submodule, a third selector, a fourth selector, a frequency difference compensation submodule, a fifth selector and a sixth selector;

The channel read control submodule is used to receive the afifo read enable, the data water level status information in the current channel afifo, and the status information of the slave channel, and output the processed read enable signals of all channels; the third selector, Used to receive all channel read enable signals and received signals output by the channel read control sub-module, and select the output; the fourth selector is used to receive the afifo read enable and receive the output of the third selector. signal, and select the output; the compensation frequency difference complement sub-module is used to receive the signal output by the fourth selector, and output the processed signal, and receive the read data of afifo, and output the processed complement signal; the fifth selector is used to receive the signal output by the compensation frequency difference compensation sub-module and the signal output by the fourth selector, and select and output to afifo; the sixth selector is used for Receive the read data of the afifo and the complement signal output by the compensation frequency difference complement sub-module, and select the output.
The bridge module according to claim 1, wherein the control terminal of the first selector and the control terminal of the second selector receive a first mode configuration signal.
The bridge module according to claim 1, wherein the control end of the fourth selector, the control end of the fifth selector and the control end of the sixth selector receive a first mode configuration signal ; The control end of the third selector receives the second mode configuration signal.
The bridge module according to claim 1, wherein the bridge module further comprises a bypass control sub-module and a seventh selector;

The bypass control submodule is used to receive the decoded data and output the processed data;

The seventh selector is configured to receive the data output by the bypass control sub-module and the signal output by the sixth selector, and select and output the configuration output data and the data indication signal.
The bridge module according to claim 4, wherein the control terminal of the seventh selector receives a mode configuration signal.
The bridging module according to claim 1, wherein the bridging module further comprises a state generating sub-module; the state generating sub-module is configured to receive the signal output by the sixth selector, and output the function control signal after processing to the channel control submodule.
The bridge module according to claim 6, wherein the state generation sub-module is configured to generate data alignment state information.