CN112765066A - Bridge module for serdes interface - Google Patents
Bridge module for serdes interface Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a bridge module for a serdes interface, which comprises a write-in control module, a read-out control module and a Be _ fifo submodule; the write-in control comprises a cascaded channel control submodule, a first selector, a compensation frequency difference deleting submodule and a second selector; the reading control module comprises a channel reading control submodule, a third selector, a fourth selector, a compensation frequency difference complement submodule, a fifth selector and a sixth selector. The bridging module for the serdes interface reduces the processing time delay of data and improves the transmission performance of the whole serdes interface.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of integrated circuit chips, in particular to a bridge module for serdes interfaces.
[ background of the invention ]
As a mainstream time division multiplexing and point-to-point serial communication technology, a serdes interface on an FPGA (Programmable Gate Array) can realize a higher data rate through fewer pins, and the requirements of data throughput under multiple protocol scenes such as PCIE and SATA are met.
As an important component of serdes, the PCS rx part is responsible for receiving the data after serial-parallel conversion, decoding the aligned data, and supporting the functions of multi-channel data alignment and frequency difference compensation. Therefore, the quality of the PCS rx part data processing delay has great influence on the whole serdes data transmission performance.
In the prior art, a PCS rx part realizes functions of multi-channel data alignment and the like in each single module, and selects whether related functions are supported or not through a plurality of muxes. In order to complete temporary storage of data and clock domain conversion, each module instantiates an afifo module. Because each module starts data writing operation from an address half the depth of the afifo and starts data reading from the '0' address, when a plurality of functions are enabled, the time delay caused by the sequential processing of the data is gradually accumulated, and the overall processing time delay is too large, which is not beneficial to the improvement of the overall serdes data processing performance.
[ summary of the invention ]
The invention aims to provide a bridging module for serdes interfaces.
In order to achieve the above object, the present invention provides a bridge module for serdes interface, which includes a write control module, a read control module, and a Be _ fifo submodule;
the write-in control comprises a cascaded channel control submodule, a first selector, a compensation frequency difference deleting submodule and a second selector;
the channel control submodule is used for receiving the decoding data and the afifo write enable and outputting the processed write data and the afifo write enable; the first selector is used for receiving the write data and the afifo write enable output by the channel control submodule, receiving the decoding data and the afifo write enable, and selecting to output; the compensation frequency difference deleting submodule is used for receiving the signal output by the first selector and outputting the processed write data and the afifo write enable; the second selector is used for receiving the signal output by the compensation frequency difference deleting submodule and the signal output by the first selector, and selecting and outputting the signal to the afifo;
the reading control module comprises a channel reading control submodule, a third selector, a fourth selector, a compensation frequency difference complement submodule, a fifth selector and a sixth selector;
the channel reading control submodule is used for receiving the af ifo reading enable, the water level state information of the data in the current channel af ifo and the state information of the slave channel, and outputting all the processed channel reading enable signals; the third selector is used for receiving all the channel read enabling signals and receiving signals output by the channel read control submodule and selectively outputting the signals; the fourth selector is used for receiving the afifo read enable and receiving the signal output by the third selector, and selecting and outputting the signal; the compensation frequency offset and bit complementing submodule is used for receiving the signal output by the fourth selector, outputting a processed signal, receiving read data of the afifo and outputting a processed bit complementing signal; the fifth selector is configured to receive a signal output by the compensation frequency offset compensation sub-module and a signal output by the fourth selector, and selectively output the signal to the afifo; and the sixth selector is used for receiving the read data of the afifo, receiving the complementary bit signal output by the compensation frequency difference complementary bit submodule and selectively outputting the complementary bit signal.
Preferably, the control terminal of the first selector and the control terminal of the second selector receive a first mode configuration signal.
Preferably, the control terminal of the fourth selector, the control terminal of the fifth selector, and the control terminal of the sixth selector receive a first mode configuration signal; and the control end of the third selector receives a second mode configuration signal.
Preferably, the bridge module further comprises a bypass control sub-module and a seventh selector;
the bypass control submodule is used for receiving the decoded data and outputting the processed data;
and the seventh selector is used for receiving the data output by the bypass control sub-module, receiving the signal output by the sixth selector, and selectively outputting configuration output data and a data indication signal.
Preferably, the control terminal of the seventh selector receives a mode configuration signal.
Preferably, the bridge module further comprises a state generation submodule; and the state generation submodule is used for receiving the signal output by the sixth selector and outputting a function control signal to the channel control submodule after processing.
Preferably, the state generating submodule is configured to generate data alignment state information.
The invention has the beneficial effects that: the bridge module for the serdes interface is provided, so that the processing time delay of data is reduced, and the transmission performance of the whole serdes interface is improved.
[ description of the drawings ]
Fig. 1 is a structural diagram of a bridge module according to an embodiment of the invention.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below with reference to the specific embodiments of the present disclosure and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present specification without any creative effort belong to the protection scope of the present specification. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The terms "first," "second," and "third," etc. in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
As shown in fig. 1, an embodiment of the present invention provides a bridge module rx _ bridge _ unit for Serdes (SERializer/DESerializer) interface, where the bridge module rx _ bridge _ unit includes sub-modules of write control wr _ ctrl, read control rd _ ctrl, and Be _ fifo (afifo).
The Be _ fifo (first in first out ) submodule includes an afifo (memory module), and the Be _ fifo submodule is used for outputting data water level state information fifo _ state of the afifo according to the data water level condition in the afifo.
The write control wr _ ctrl comprises a cascaded channel control submodule cb _ ctrl, a first selector X1, a compensated frequency difference deleting submodule ctc _ del _ ctrl and a second selector X2;
the channel control submodule cb _ ctrl is used for receiving the decoded data _ after _ decoder and the afifo write enable rxfifo _ wr _ en, and outputting the processed write data cb _ wr _ start and the afifo write enable mcb _ dout;
a first selector X1 for receiving the write data cb _ wr _ start and the aFIFO write enable mcb _ dout output by the channel control submodule cb _ ctrl and receiving the decoded data _ after _ decoder and the affifo write enable rxfifo _ wr _ en, and selecting an output;
since the determination conditions of the first selector X1 are consistent, the decoded data _ after _ decoder and the afifo write enable rxfifo _ wr _ en received by the first selector X1 in the drawing are represented by one line; similarly, the judgment conditions based on the selector are the same, the data and enable signal lines input and output by the selector are represented by one line, and the data and enable signals on the same line are distinguished by 'two'.
The compensation frequency difference deleting submodule ctc _ del _ ctrl is configured to receive the write data ctc _ din and the afifo write enable ctc _ wr _ en output by the first selector X1, and output the processed write data ctc _ dout and the afifo write enable ctc _ fifo _ wr _ start;
a second selector X2, for receiving the signal output by the compensated frequency difference deleting submodule ctc _ del _ ctrl and the signal write data ctc _ din (Mcb-dout) and the afifo write enable ctc _ wr _ en (Mcb fifo _ wr _ start) output by the first selector X1, and selecting to output the write data wr _ ctrl _ dout and the afifo write enable fifo _ wr _ start to the afifo.
The readout control rd _ ctrl includes a channel read control sub-module cb _ rden _ ctrl, a third selector X3, a fourth selector X4, a compensation frequency difference complement sub-module ctc _ add _ ctrl, a fifth selector X5, and a sixth selector X6.
The channel read control submodule cb _ rden _ ctrl is configured to receive the afifo read enable rx _ fifo _ rden, the state information fifo _ state of the data level in the current channel (main channel), and the state information fifo _ state _ cin of the slave channel, and output a processed all-channel read enable signal master _ cb _ rden;
a third selector X3 for receiving all the channel read enable signals master _ cb _ rden and receiving the cascade signal cb _ rden _ cin output by the channel read control sub-module cb _ rden _ ctrl and selecting an output; the cascade signal cb _ rden _ cin is used for transmitting an afifo read enable signal output by the main channel and ensuring that all channel data are read simultaneously;
a fourth selector X4 for receiving afifo read enable rx _ fifo _ rden and receiving the signal cb _ rden output from the third selector X3, and selecting an output;
a compensation frequency offset complementary sub-module ctc _ add _ ctrl for receiving the signal ctc _ fifo _ rden _ in output by the fourth selector X4, outputting a processed signal ctc _ fifo _ rden, receiving read data of afifo, and outputting a processed complementary signal ctc _ add _ dout;
a fifth selector X5, configured to receive the signal ctc _ fifo _ rden output by the compensated frequency offset compensation submodule ctc _ add _ ctrl and receive the signal output by the fourth selector X4, and select to output the read enable signals fifo _ rd _ en to afifo; namely, the read enable signal fifo _ rd _ en which is finally output to the Be _ fifo submodule;
a sixth selector X6, configured to receive the read data of the afifo and receive the complementary bit signal ctc _ add _ dout output by the compensated frequency offset complementary bit submodule ctc _ add _ ctrl, and select an output.
The third selector X3 selects, according to the configuration of the master and slave channels, the afifo read enable signal master _ cb _ rden generated by the channel; the cascaded signal cb _ rden _ cin is selected from the channel. cb _ rden is the af ifo read enable signal that the data alignment function finally generates to ensure that all channels start reading data from the af ifo at the same time.
The compensation frequency offset compensation sub-module ctc _ add _ ctrl inserts a special character skip pattern into data read out from the afifo, and the signal ctc _ fifo _ rden is pulled down by one cycle after a certain number of special character insertion operations to complete frequency offset compensation of the data; the compensation frequency offset compensation sub-module ctc _ add _ ctrl inserts a special character skip pattern into data read out from the afifo, and the compensation signal ctc _ add _ dout is data adjusted by the compensation frequency offset compensation sub-module ctc _ add _ ctrl.
The channel reading control submodule cb _ rden _ ctrl of the main channel judges received data water level state information fifo _ state in the af ifo of the main channel and data water level state information fifo _ state _ cin in the slave channel, and when the data water level state information of all the channels shows that the data water level in the channels reaches a specified state, the main channel reading control submodule cb _ rden _ ctrl transmits externally received reading enable rx _ fifo _ rden to the af ifo of the main channel, and starts data reading operation; meanwhile, the cascade signal cb _ rden _ cout is transmitted to all the slave channels, and the afifo read enable of all the slave channels uses the signal transmitted by the master channel in a cascade mode, so that the master channel and the slave channels can start reading of the afifo data at the same time, and data alignment is guaranteed.
Planning four channel lanes (0-3) in the Serdes interface, wherein each channel lane uses a respective bridge module rx _ bridge _ unit; wherein, the Lane 0 is set as a master channel, and the other channels are set as slave channels.
Further, the control terminal of the first selector X1 and the control terminal of the second selector X2 receive the first mode configuration signal cfg _ rebidge _ mode.
Further, the control terminal of the fourth selector X4, the control terminal of the fifth selector X5, and the control terminal of the sixth selector X6 receive the first mode configuration signal cfg _ rebrid _ mode. Further, the control terminal of the third selector X3 receives the second mode configuration signal cfg _ rxbu _ slave. The second mode configuration signal cfg _ rxbu _ slave is used for configuring the states of the master channel and the slave channel.
In one embodiment, as shown in fig. 1, the bridge module (rx _ bridge _ unit) further includes a bypass control sub-module by _ pass _ ctrl and a seventh selector X7.
The bypass control sub-module by _ pass _ ctrl is used for receiving the decoded data _ after _ decoder and outputting the processed data by _ pass _ dout;
and the seventh selector X7 is configured to receive the data by _ pass _ dout output by the bypass control sub-module by _ pass _ ctrl and the frequency difference-adjusted output data ctc _ dout output by the sixth selector X6, and select and output the configuration output data _ after _ rxbu and the data indication signal data _ vld _ after _ rxbu. Further, the control terminal of the seventh selector X7 receives the first mode configuration signal cfg _ rebidge _ mode.
The bridge module (rx _ bridge _ unit) also supports by _ pass selection, namely, the bypass control sub-module by _ pass _ ctrl is set, so that the internal Be _ fifo sub-module is controlled not to Be enabled, and data is output only after the bypass control sub-module by _ pass _ ctrl is sampled.
In one embodiment, as shown in fig. 1, the bridge module (rx _ bridge _ unit) further includes a state generation submodule mcb _ status _ gen.
The state generating sub-module mcb _ status _ gen is configured to receive the signal output by the sixth selector X6, and output the function control signal channel bonding to the channel control sub-module cb _ ctrl after processing; to enable all channel data adjustment and special character aptattern detection.
A state generating sub-module mcb _ status _ gen for generating data alignment state information binding _ status; specifically, the state generating sub-module mcb _ status _ gen determines, by using a built-in state machine, according to a result of detection of a special character aptattern in all channel data, to obtain data alignment state information binding _ status, where the data alignment state information binding _ status is raised to indicate that all channel data alignment is completed.
In one embodiment, the first mode configuration signal cfg _ bridge _ mode is used to configure the operating mode of the bridge module rx _ bridge _ unit, and the plurality of sub-modules are enabled to perform the selected function.
When the bridge module rx _ bridge _ unit is configured to the bridge mode by the first mode configuration signal cfg _ rebridge _ mode, the bridge module rx _ bridge _ unit only enables the Be _ fifo sub-module after receiving the decoded data _ after _ decoder, thereby completing data bridging and compensating for phase difference. The read and write start addresses of the Be _ fifo submodule can Be respectively configured to Be 3 and 1, so that the overall processing delay is reduced.
If the serdes interface needs the bridge module rx _ bridge _ unit to perform the alignment function between the multi-channel data, the channel control sub-module cb _ ctrl in each channel completes the adjustment of the data through the special character apattern in the data, and writes the data into the Be _ fifo sub-module to perform the conversion of the clock domain. And the main channel reading control submodule cb _ rden _ ctrl outputs fifo read enable to all the channels according to the data water level states in all the channel Be _ fifo submodule so as to ensure the alignment of data. Multi-channel data alignment is controlled by the state machine within the main channel's state generation submodule mcb _ status _ gen. Clock domain conversion usually consumes most time delay in the realization of a multi-channel alignment function, and the optimal configuration of fifo read and write start addresses can greatly improve the problem. In different first mode configuration signal cfg _ rxbridge _ mode configurations, the read and write start addresses are different, for example, after the ctc function is enabled, and after the nominal empty mode is configured, the read and write start addresses are both configured to be 0.
When the bridge module rx _ bridge _ unit is configured as the clock compensation frequency difference mode ctc mode through the first mode configuration signal cfg _ rebridge _ mode, in order to maximally reduce the delay caused by the processing of the Be _ fifo sub-module data, the bridge module rx _ bridge _ unit supports the normal null mode nominal mode configuration. In this mode, the compensation frequency difference deleting submodule ctc _ del _ ctrl directly deletes the special character skip pattern in the data, and writes the processed data into the Be _ fifo submodule for temporary storage and clock domain conversion. The compensation frequency offset compensation sub-module ctc _ add _ ctrl of the read clock domain directly pulls down the read enable after the be _ fifo sub-module reads "empty", and indicates invalid data through the data indication signal data _ vld _ after _ rxbu. To minimize the latency caused by data clock domain switching, the read and write start addresses of the Be _ fifo submodule are both configured to Be 0.
If the multi-channel data alignment and frequency difference compensation functions need to be simultaneously supported, the bridge module rx _ bridge _ unit configures required sub-modules through a first mode configuration signal cfg _ rebridge _ mode, and simultaneously supports normal null mode nominal mode selection under the clock compensation frequency difference ctc processing.
An embodiment of the present invention further provides a PCS rx architecture including the bridge module rx _ bridge _ unit, where the bridge module rx _ bridge _ unit is located before the transfer module gear unit, and an eighth selector X8 is further included between the bridge module rx _ bridge _ unit and the transfer module gear unit.
The bridge module rx _ bridge _ unit integrates the functions realized by all Be _ fifo sub-modules, and only one afifo is instantiated in the bridge module rx _ bridge _ unit. Due to the reduction of the use of the afifo, when a plurality of functions are enabled, the processing time delay caused by data temporary storage and clock domain conversion is greatly reduced.
The read and write start addresses of the afifo in the bridge module rx _ bridge _ unit can be configured; under the condition of ensuring normal data processing, the time delay caused by clock domain conversion can be maximally reduced by changing the read and write initial addresses. For the frequency offset compensation function, the bridge module rx _ bridge _ unit supports a normal null mode, i.e. the afifo write and read data operations start from '0' addresses, so as to ensure the lowest processing delay in the process.
Taking effective data as 20 bits as an example, and under the same data characteristics, the processing time delay required by the PCS rx architecture in the prior art and the PCS rx architecture adopting the bridge module rx _ bridge _ unit in the present invention are both 18rclks (read clock unit period); under the frequency difference compensation function, the processing time delay of a PCS rx framework of a bridge module rx _ bridge _ unit is 10rclks which is lower than 22.5rclks in the PCS rx framework in the prior art; under the functions of multi-channel data alignment and frequency difference compensation, the processing time delay of the PCS rx framework adopting the bridge module rx _ bridge _ unit is 24rclks which is lower than 39.5rclks in the PCS rx framework in the prior art.
The PCS rx framework adopting the bridge module rx _ bridge _ unit has lower processing time delay and better transmission performance of the serdes.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (7)
1. A bridge module for serdes interface is characterized in that it includes write control, read control and Be _ fifo submodule;
the write-in control comprises a cascaded channel control submodule, a first selector, a compensation frequency difference deleting submodule and a second selector;
the channel control submodule is used for receiving the decoding data and the afifo write enable and outputting the processed write data and the afifo write enable; the first selector is used for receiving the write data and the afifo write enable output by the channel control submodule, receiving the decoding data and the afifo write enable, and selecting to output; the compensation frequency difference deleting submodule is used for receiving the signal output by the first selector and outputting the processed write data and the afifo write enable; the second selector is used for receiving the signal output by the compensation frequency difference deleting submodule and the signal output by the first selector, and selecting and outputting the signal to the afifo;
the reading control module comprises a channel reading control submodule, a third selector, a fourth selector, a compensation frequency difference complement submodule, a fifth selector and a sixth selector;
the channel reading control submodule is used for receiving the af ifo reading enable, the water level state information of the data in the current channel af ifo and the state information of the slave channel, and outputting all the processed channel reading enable signals; the third selector is used for receiving all the channel read enabling signals and receiving signals output by the channel read control submodule and selectively outputting the signals; the fourth selector is used for receiving the afifo read enable and receiving the signal output by the third selector, and selecting and outputting the signal; the compensation frequency offset and bit complementing submodule is used for receiving the signal output by the fourth selector, outputting a processed signal, receiving read data of the afifo and outputting a processed bit complementing signal; the fifth selector is configured to receive a signal output by the compensation frequency offset compensation sub-module and a signal output by the fourth selector, and selectively output the signal to the afifo; and the sixth selector is used for receiving the read data of the afifo, receiving the complementary bit signal output by the compensation frequency difference complementary bit submodule and selectively outputting the complementary bit signal.
2. The bridge module of claim 1, wherein the control terminal of the first selector and the control terminal of the second selector receive a first mode configuration signal.
3. The bridge module of claim 1, wherein the control terminal of the fourth selector, the control terminal of the fifth selector, and the control terminal of the sixth selector receive a first mode configuration signal; and the control end of the third selector receives a second mode configuration signal.
4. The bridge module of claim 1, further comprising a bypass control sub-module and a seventh selector;
the bypass control submodule is used for receiving the decoded data and outputting the processed data;
and the seventh selector is used for receiving the data output by the bypass control sub-module, receiving the signal output by the sixth selector, and selectively outputting configuration output data and a data indication signal.
5. The bridge module of claim 4, wherein the control terminal of the seventh selector receives a mode configuration signal.
6. The bridge module of claim 1, further comprising a state generation submodule; and the state generation submodule is used for receiving the signal output by the sixth selector and outputting a function control signal to the channel control submodule after processing.
7. The bridge module of claim 6, wherein the status generation submodule is configured to generate data alignment status information.
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| CN202011491396.6A CN112765066B (en) | 2020-12-16 | 2020-12-16 | Bridge module for serdes interface |
| PCT/CN2021/082547 WO2022126893A1 (en) | 2020-12-16 | 2021-03-24 | Bridging module for serdes interface |
| KR1020237016819A KR20230086788A (en) | 2020-12-16 | 2021-03-24 | Bridge unit for serdes interface |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003081785A1 (en) * | 2002-03-21 | 2003-10-02 | Broadcom Corporation | Physcial layer device having an analog serdes pass through mode |
| US20070073943A1 (en) * | 2005-07-28 | 2007-03-29 | Nec Electronics Corporation | Serial-to-parallel conversion/parallel-to-serial conversion/ FIFO unified circuit |
| US20080316320A1 (en) * | 2007-06-21 | 2008-12-25 | Ronald Norman Prusia | Clock serizlizer/deserializer transmission method and appartus |
| US20090125652A1 (en) * | 2002-07-26 | 2009-05-14 | Broadcom Corporation | Physical layer device having a serdes pass through mode |
| US20140029331A1 (en) * | 2012-07-27 | 2014-01-30 | Rambus Inc. | Memory device with multi-mode deserializer |
| JP2014138362A (en) * | 2013-01-18 | 2014-07-28 | Nippon Telegr & Teleph Corp <Ntt> | Signal receiving circuit |
| CN105516288A (en) * | 2015-12-01 | 2016-04-20 | 盛科网络（苏州）有限公司 | Architecture for extending physical ports with single Serdes, control method and control system thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007033305A2 (en) * | 2005-09-12 | 2007-03-22 | Multigig Inc. | Serializer and deserializer |
| CN108388532A (en) * | 2018-03-13 | 2018-08-10 | 算丰科技（北京）有限公司 | The AI operations that configurable hardware calculates power accelerate board and its processing method, server |
| CN108345555B (en) * | 2018-03-13 | 2021-10-08 | 算丰科技（北京）有限公司 | Interface bridge circuit based on high-speed serial communication and method thereof |
| CN210515149U (en) * | 2019-10-28 | 2020-05-12 | 成都爱斯顿科技有限公司 | CPCI computer main controller based on Shenwei processor and ICH2 bridge chip |
| CN211087065U (en) * | 2019-12-24 | 2020-07-24 | 龙芯中科(西安)科技有限公司 | Mainboard and computer equipment |
-
2020
- 2020-12-16 CN CN202011491396.6A patent/CN112765066B/en active Active
-
2021
- 2021-03-24 WO PCT/CN2021/082547 patent/WO2022126893A1/en active Application Filing
- 2021-03-24 KR KR1020237016819A patent/KR20230086788A/en unknown
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003081785A1 (en) * | 2002-03-21 | 2003-10-02 | Broadcom Corporation | Physcial layer device having an analog serdes pass through mode |
| US20090125652A1 (en) * | 2002-07-26 | 2009-05-14 | Broadcom Corporation | Physical layer device having a serdes pass through mode |
| US20070073943A1 (en) * | 2005-07-28 | 2007-03-29 | Nec Electronics Corporation | Serial-to-parallel conversion/parallel-to-serial conversion/ FIFO unified circuit |
| US20080316320A1 (en) * | 2007-06-21 | 2008-12-25 | Ronald Norman Prusia | Clock serizlizer/deserializer transmission method and appartus |
| US20140029331A1 (en) * | 2012-07-27 | 2014-01-30 | Rambus Inc. | Memory device with multi-mode deserializer |
| JP2014138362A (en) * | 2013-01-18 | 2014-07-28 | Nippon Telegr & Teleph Corp <Ntt> | Signal receiving circuit |
| CN105516288A (en) * | 2015-12-01 | 2016-04-20 | 盛科网络（苏州）有限公司 | Architecture for extending physical ports with single Serdes, control method and control system thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112765066B (en) | 2022-07-08 |
| KR20230086788A (en) | 2023-06-15 |
| WO2022126893A1 (en) | 2022-06-23 |
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