JP4646932B2 - Memory element - Google Patents

Description

  The present invention relates to a memory device capable of switching between access using a serial interface and access using a parallel interface.

  A memory element such as a flash memory employs an architecture that allows access through a simple four-wire serial interface. For example, as shown in FIG. 6, a memory element employing a serial interface is usually incorporated in a chip package of 8 pins or 16 pins. Therefore, the device can be made smaller than a memory device that employs a parallel interface, and the cost of the package can be reduced.

  For example, when an 8-pin chip package is used, in addition to the power supply terminals (VDD, VSS), an address / data input terminal (SI), a data output terminal (SO), a chip select terminal (CS #), a system clock A 4-wire serial interface terminal of an input terminal (SCK) is assigned. Other pins are assigned control terminals such as a write protect terminal for determining permission of write / erase access, a reset terminal for stopping processing at the time of interruption, and a hold terminal for temporarily stopping processing and holding the state.

  As shown in FIG. 7, the memory element 100 employing the serial interface includes an address buffer / latch unit 10, a control logic unit 12, a data register 14, an X decoder 16, a Y decoder 18, a memory array 20, and a serial-parallel conversion unit. 22 and a parallel-serial converter 24.

  When data is read from the memory element 100, control is performed as shown in the timing chart of FIG.

  First, the memory element 100 to be accessed is selected by changing the chip select terminal (CS #) to the low level. When the chip select terminal (CS #) is changed to a low level, the control logic unit 12 sets each unit to a command receiving state.

  Next, a command (03h in FIG. 8) indicating data reading is input from the address / data input terminal (SI). The command is composed of, for example, 8 bits, and is serially input to the serial-parallel conversion unit 22 bit by bit in synchronization with the system clock input from the system clock input terminal (SCK). The command is converted from serial data into parallel data corresponding to the bit width (for example, 8 bits) of the internal bus by the serial-parallel conversion unit 22 and sent to the control logic unit 12.

  The control logic unit 12 analyzes the command. For example, in the case of a command (03h) indicating data reading, the control logic unit 12 sets each unit to an address value reception state.

Next, an address value (Add.) Is input from the address / data input terminal (SI). The address value is represented by 24 bits, for example, and is input to the serial-parallel converter 22 serially bit by bit in synchronization with the system clock. The serial-parallel converter 22 sequentially converts the address value from serial data to parallel data having a bit width (for example, 8 bits) of the internal bus. The control logic unit 12 sequentially transfers the address values converted into parallel data from the serial-parallel conversion unit 22 to the address buffer / latch unit 10.

  When the address buffer / latch unit 10 receives the address value, it outputs a control signal to the X decoder 16 and the Y decoder 18 to identify the corresponding memory element in the memory array 20 and is held in that memory element. Read data. The read data is stored in the data register 14 via the Y decoder 18. The parallel-serial converter 24 converts the data stored in the data register 14 into serial data, and outputs it from the data output terminal (SO) in synchronization with the system clock.

  The address buffer / latch unit 10 sequentially increases the address value and performs control so that data is sequentially read from the memory element specified by the next address value.

  However, in a memory device employing a 4-wire serial interface, since the address and data input / output is 1-bit serial communication, the transfer rate is significantly lower than that of a memory device employing a parallel interface. .

  In view of the above-described problems of the prior art, the present invention provides a memory element that enables parallel transfer of data as needed while applying the same package as a memory element that employs a conventional serial interface. Objective.

  In the present invention, the memory device includes a control logic unit connected to the first terminal, the second terminal, the third terminal, and the first terminal, and the first terminal functions as an address / data input terminal, In a state where the second terminal functions as a data output terminal and the third terminal functions as a control terminal, when the control logic unit receives a data read command by a parallel interface by an input from the first terminal, At least two of the first terminal, the second terminal, and the third terminal function as input / output terminals.

  In the present invention, the memory element includes a first terminal, a second terminal, a third terminal, and a control logic unit connected to the first terminal, and the memory element includes the first terminal, the second terminal, and the third terminal. In a state where at least two function as input / output terminals, when the control logic unit receives a data read command by a serial interface by an input from the terminal functioning as the input / output terminal, the first terminal It functions as a data input terminal, the second terminal functions as a data output terminal, and the third terminal functions as a control terminal.

  According to the present invention, it is possible to access by a parallel interface as necessary while applying a package having the same size as a memory element employing a conventional serial interface.

  As shown in FIG. 1, the memory element 200 in the present embodiment includes an address buffer / latch unit 30, a control logic unit 32, a data register 34, an X decoder 36, a Y decoder 38, a memory array 40, and a serial-parallel conversion unit. 42, a parallel-serial converter 44, a parallel-parallel converter 46, and a multiplexer 48.

  The memory device 200 employs a package similar to a memory device employing a conventional serial interface. A multiplexer 48 is provided to switch the connection of the terminals between the serial interface access and the parallel interface access.

  As shown in FIG. 2, the multiplexer 48 includes a plurality of changeover switches 48a. The multiplexer 48 receives the switching control signal from the control logic unit 32, and converts the external terminal of the chip package to any one of the serial-parallel conversion unit 42, the parallel-serial conversion unit 44, and the parallel-parallel conversion unit 46, respectively. Connecting.

  For example, when an 8-pin chip package is employed, when accessing via a serial interface, the changeover switch 48a is connected to the left terminal, and the terminal is assigned in the same manner as in FIG. That is, the data output terminal (SO) is a parallel-serial converter 44, the address / data input terminal (SI) is a serial-parallel converter 42, the first control terminal (C0) and the second control terminal (C1) are control logic. Each is connected to the unit 32.

  On the other hand, when data is read by the parallel interface, the changeover switch 48a is connected to the right terminal, and for example, as shown in FIG. 3, the data output terminal (SO) is connected to the fourth data input / output terminal (SIO3). ), The first control terminal (C0) is the third data input / output terminal (SIO2), the second control terminal (C1) is the second data input / output terminal (SIO1), and the address / data input terminal (SI) is the first. 1 data input / output terminal (SIO0). As a result, access by a parallel interface is made possible. That is, the data output terminal (SO), the address / data input terminal (SI), the first control terminal (C0), and the second control terminal (C1) are all connected to the parallel-parallel converter 46.

Next, data read processing by the serial interface, data read processing by the parallel interface, and return processing to the serial interface will be described.
<Data reading by serial interface>
The memory element 200 is normally set to a state where access is made through a serial interface. At this time, each changeover switch 48a of the multiplexer 48 is connected to the terminal on the left side, and a terminal is assigned in the same manner as in FIG.

Therefore, when reading data from the memory element 200, processing is performed according to the timing chart of FIG. 8 as in the conventional memory element. Since this process is the same as that of a conventional memory element, description thereof is omitted.
<Data reading by parallel interface>
When accessing by a parallel interface, processing is performed as shown in the timing chart of FIG. In the initial state, it is assumed that each changeover switch 48a of the multiplexer 48 is connected to the left terminal, and the terminal is assigned in the same manner as in FIG.

  First, the memory element 200 to be accessed is selected by changing the chip select terminal (CS #) to the low level. When the chip select terminal (CS #) is changed to a low level, the control logic unit 32 sets each unit to a command receiving state.

Next, a command (for example, D4h) indicating data reading through the parallel interface is input from the address / data input terminal (SI). The command is composed of, for example, 8 bits, and is serially input to the serial-parallel conversion unit 42 bit by bit in synchronization with the system clock input from the system clock input terminal (SCK). The command is converted from serial data into parallel data corresponding to the bit width (for example, 8 bits) of the internal bus by the serial-parallel conversion unit 42 and sent to the control logic unit 32.

  The control logic unit 32 analyzes the command. In the case of a command (D4h) indicating data reading by the parallel interface, the control logic unit 32 sets each unit to an address value accepting state and switches the selector switch 48a of the multiplexer 48 to a terminal on the right side. As a result, the data output terminal (SO), the address / data input terminal (SI), the first control terminal (C0), and the second control terminal (C1) are all connected to the parallel-parallel converter 46, and the data output terminal ( SO) is the fourth data input / output terminal (SIO3), the first control terminal (C0) is the third data input / output terminal (SIO2), and the second control terminal (C1) is the second data input / output terminal (SIO1). ), The address / data input terminal (SI) is assigned to the first data input / output terminal (SIO0).

  At this time, it is preferable to switch the multiplexer 48 at a timing at which the chip select terminal (CS #) is returned to the high level and again changed to the low level. Further, the multiplexer 48 may be switched after the control logic 32 counts a predetermined number of system clocks in synchronization with the system clock input to the system clock terminal (SCK).

  Next, the address value (Add.) Is simultaneously input in parallel by four bits from the four data input / output terminals (SIO0 to SIO3). The address value is represented by, for example, 24 bits, and is input to the parallel-parallel converter 46 in parallel by 4 bits in synchronization with the system clock. The parallel-parallel converter 46 sequentially converts the address value into parallel data having a bit width (for example, 8 bits) of the internal bus. The control logic unit 32 sequentially transfers the address value converted into the bit width of the internal bus from the parallel-parallel conversion unit 46 to the address buffer / latch unit 30.

  When the address buffer / latch unit 30 receives the address value, it outputs a control signal to the X decoder 36 and the Y decoder 38 to identify the corresponding memory element in the memory array 40 and is held in that memory element. Read data. The read data is stored in the data register 34 via the Y decoder 38. The parallel-parallel converter 46 converts the data having the bit width of the internal bus stored in the data register 34 into 4-bit parallel data, and synchronizes with the system clock to provide four data input / output terminals (SIO0 to SIO3). ).

  The address buffer / latch unit 30 performs control so that the address value is sequentially increased and data is sequentially read from the memory element specified by the next address value.

In this embodiment, the address value and data are input / output in synchronization with the system clock. However, it is also preferable to apply a high-speed transfer technique such as a double data rate (DDR).
<Return to access via serial interface>
With reference to FIG. 5, processing for returning from access using a parallel interface to access using a serial interface will be described. The chip select terminal (CS #) is once returned to the high level to cancel the selection of the memory element, and the chip select terminal (CS #) is changed to the low level again. This pulse input to the chip select terminal (CS #) is used as a trigger for processing for receiving a new command. That is, the control logic unit 32 puts the memory element 200 into a state of accepting an input as a command. Thereafter, commands are simultaneously input in parallel by four bits from the four data input / output terminals (SIO0 to SIO3).

  The command is represented by, for example, 8 bits, and is input to the parallel-parallel conversion unit 46 in parallel by 4 bits in synchronization with the system clock. The parallel-parallel conversion unit 46 converts the command into the bit width (for example, 8 bits) of the internal bus and transmits the command to the control logic unit 32.

  The control logic unit 32 analyzes the command. When the command is a command for returning to the serial interface, the control logic unit 32 switches the changeover switch 48a of the multiplexer 48 to the left terminal. As a result, the normal serial interface can be accessed again.

  At this time, it is preferable to switch the multiplexer 48 at a timing at which the chip select terminal (CS #) is returned to the high level and again changed to the low level. Alternatively, the multiplexer 48 may be switched after a predetermined standby time has elapsed in synchronization with the system clock input to the system clock terminal (SCK).

  As described above, according to the present embodiment, it is possible to realize a memory element that can be accessed through a parallel interface as needed while applying a package having the same size as a memory element that employs a conventional serial interface. Can do.

It is a block diagram which shows the structure of the memory element in embodiment of this invention. It is a figure which shows the structure of the multiplexer in embodiment of this invention. It is a figure which shows the assignment of the pin at the time of performing access by a parallel interface. It is a figure which shows the timing chart of the data read-out process by the parallel interface in embodiment of this invention. It is a figure which shows the timing chart of the switching process from the parallel interface in embodiment of this invention to a serial interface. It is a figure which shows allocation of the pin of the memory element which performs access by a serial interface. It is a block diagram which shows the structure of the conventional memory element. It is a figure which shows the timing chart of the data read-out process by a serial interface.

Explanation of symbols

  10 address buffer / latch unit, 12 control logic unit, 14 data register, 16 X decoder, 18 Y decoder, 20 memory array, 22 serial-parallel conversion unit, 24 parallel-serial conversion unit, 30 address buffer / latch unit, 32 Control logic unit, 34 data register, 36 X decoder, 38 Y decoder, 40 memory array, 42 serial-parallel conversion unit, 44 parallel-serial conversion unit, 46 parallel-parallel conversion unit, 48 multiplexer, 48a changeover switch, 100, 200 Memory element.

Claims (6)

A memory device that can switch between serial interface access and parallel interface access,
The memory device includes a control logic unit connected to a first terminal, a second terminal, a third terminal, and the first terminal;
The memory element performs access through the parallel interface using only terminals assigned when performing access through the serial interface.
In the access by the serial interface, the first terminal functions as an address / data input terminal, the second terminal functions as a data output terminal, and the third terminal functions as a control terminal.
The input from the first terminal, when the control logic unit receives a data read command by the parallel interface, the first terminal, the second terminal, at least two of the third terminal functions as input and output terminals . The memory device according to claim 1 further includes a chip select terminal.
After the control logic unit accepts a data read command by the parallel interface, the first terminal and the second terminal at a timing when the chip select terminal once enters an inactive state and then enters an active state. At least two of the third terminals function as input / output terminals. The memory device according to claim 1, further comprising a system clock terminal,
After the control logic unit receives a data read command by the parallel interface, and counts a predetermined number of system clocks input to the system clock terminal, the first terminal, the second terminal, and the third terminal At least two function as input / output terminals. A memory device that can switch between serial interface access and parallel interface access,
The memory device includes a control logic unit connected to a first terminal, a second terminal, a third terminal, and the first terminal;
The memory element performs access through the parallel interface using only terminals assigned when performing access through the serial interface.
In the state where at least two of the first terminal, the second terminal, and the third terminal function as input / output terminals in the access by the parallel interface ,
The input from the terminal acting as the output terminal, when the control logic unit receives a data read command by the serial interface, the first terminal functions as an address / data input terminal, said second terminal It functions as a data output terminal, and the third terminal functions as a control terminal. The memory element according to claim 4 further includes a chip select terminal,
After the control logic unit accepts a data read command by the serial interface, the first terminal receives an address / data input at the timing when the chip select terminal once becomes inactive and then becomes active. The second terminal functions as a data output terminal, and the third terminal functions as a control terminal. The memory device according to claim 4, further comprising a system clock terminal,
After the control logic unit receives a data read command by the serial interface and then counts a predetermined number of system clocks input to the system clock terminal, the first terminal functions as an address / data input terminal, The second terminal functions as a data output terminal, and the third terminal functions as a control terminal.

Images