CN113625617A

CN113625617A - GMAC channel multiplexing system based on domestic MCU chip

Info

Publication number: CN113625617A
Application number: CN202110807297.2A
Authority: CN
Inventors: 侍昌江; 金伟; 王凯; 许伟泉; 申海义; 孙启龙
Original assignee: Siyuan Electric Co Ltd
Current assignee: Siyuan Electric Co Ltd
Priority date: 2021-07-16
Filing date: 2021-07-16
Publication date: 2021-11-09

Abstract

The invention relates to the technical field of communication, and discloses a GMAC channel multiplexing system based on a domestic MCU chip, which comprises an MCU chip, the MCU chip is connected with the FPGA chip through an SPI interface and a GMAC interface, the FPGA chip is connected with the expansion equipment through a plurality of expansion interfaces, a plurality of expansion interfaces are configured through the SPI interface, the communication interruption management is controlled by the FPGA chip, a specific bus protocol is adopted, data transmission between a plurality of extension interfaces in the FPGA chip and the MCU chip is carried out through the GMAC interface, a specific data buffer area is arranged in the MCU chip and used for storing data transmitted by a GMAC interface to realize GMAC channel multiplexing, the specific bus protocol comprises a GMAC fixed byte transmission message identification code, a message type identifier, a message serial number identifier, a message byte length and data which needs to be actually received and transmitted.

Description

GMAC channel multiplexing system based on domestic MCU chip

Technical Field

The invention relates to the technical field of communication, in particular to a GMAC channel multiplexing system based on a domestic MCU chip.

Background

In the application and type selection process of the domestic MCU chip, compared with an imported SOC chip (on-chip integrated FPGA), the domestic MCU chip has no FPGA on the chip and no parallel bus outside the chip, and the external interface is limited, so that the application scene is limited, and the external interface (such as an expansion IO port, an expansion Ethernet port, an expansion CAN communication port and an expansion inter-chip high-speed synchronous communication port) needs to be expanded through the off-chip FPGA chip.

The GMAC hardware structure is mainly divided into three layers: core layer, MTL layer, DMA layer: the CORE layer, namely the IP CORE is GMAC-CORE and provides hardware interfaces and some basic functions inside the network card; the MTL layer or GMAC-MTL layer is mainly responsible for the interaction between data and DMA and FIFO cache; the GMAC-DMA layer mainly controls DMA and the interaction with a system memory, the interaction with a CPU and the like. GMAC and a CPU core are integrated in the same chip, internal bus interconnection is adopted, meanwhile, TCP/IP verification and the like are completed by hardware, the complexity and the expense of software are reduced, and the throughput rate of data packets is improved. Because the signal lines used are fewer, the circuit design is simple, and the circuit design is very efficient.

The selected home-made chip can better support a GMAC channel and can realize the communication rate of 1000 Mbps. According to the Linux drive architecture, the GMAC can only support one channel network port, the number of expansion interface devices is limited, and the drive layer needs to be modified to realize GMAC channel multiplexing.

Disclosure of Invention

The invention provides a GMAC channel multiplexing system based on a domestic MCU chip, which solves the problems that the existing domestic MCU chip can only support one GMAC channel network port, the number of expansion interface equipment is limited, and the like.

The invention can be realized by the following technical scheme:

the utility model provides a GMAC passageway multiplexing system based on domestic MCU chip, includes the MCU chip, the MCU chip passes through the SPI interface, the GMAC interface is connected with the FPGA chip, the FPGA chip links to each other with extension equipment through a plurality of extension interfaces, configures a plurality of extension interfaces through the SPI interface, by FPGA chip control communication interrupt management, adopts specific bus stipulation, through the GMAC interface carries out data transfer between a plurality of extension interfaces in the FPGA chip and the MCU chip is inside to be provided with specific data buffer memory district, specific data buffer memory district is used for the data of storage through GMAC interface conveying, realizes GMAC passageway multiplexing, specific bus stipulation contains the data of transmission message identification code, message type sign, message sequence number sign, message byte length and the actual need receiving and dispatching of GMAC fixed byte.

Therefore, a single GMAC channel of a domestic MCU chip is connected with the FPGA to realize the GMAC channel multiplexing of expanding a plurality of networks, CAN and high-speed synchronous channels among chips, and the GMAC channel is used as a data transmission channel of the MCU and the FPGA to realize the high-speed data communication of the MCU and the FPGA expansion equipment. Firstly, FPGA expansion equipment is configured through the SPI, secondly, the FPGA is used for controlling interruption, the MCU and the FPGA expansion equipment are synchronized, and finally, the communication transparency of the MCU and the FPGA expansion equipment is realized through a GMAC internal protocol.

The FPGA is a product of further development of large-scale Programmable logic devices (Field Programmable Gate Array) based on Programmable devices such as PAL, GAL and the like, and is used as a semi-custom circuit in the Field of Application Specific Integrated Circuits (ASIC), thereby not only solving the defects of custom circuits, but also overcoming the defect of limited Gate circuits of the original Programmable devices. FPGA CAN realize IO port expansion, CAN realize a plurality of Ethernet controllers, CAN realize CAN controllers, CAN realize high-speed synchronous communication ports between the customization chip.

Meanwhile, in order to realize that a plurality of devices share a GMAC channel, a Linux-based GMAC interface device driving framework customizes a device for expanding a communication channel, namely a specific data cache region is arranged in an MCU chip, internal buffer of the MCU chip is shared to the expansion device, and all devices synchronously read and write data through FPGA synchronous interruption. Through the internal protocol, the accuracy of data acquisition is realized, and the uniqueness of the communication between the MCU and the FPGA expansion equipment is ensured.

Further, the SPI interface of MCU chip, GMAC interface and the SPI interface of FPGA chip, GMAC interface correspond to be connected, and BUS Conv module, Addr Oper module in the FPGA chip are used for SPI interface, GMAC interface and the passageway mapping that corresponds the extension apparatus of FPGA chip to make things convenient for the MCU chip to pass through the communication of FPGA chip and a plurality of extension apparatuses, realize that the passageway is multiplexing.

Further, the expansion interface comprises an expansion optical interface time synchronization module, a dual Ethernet module, a BO outlet control module, a BI acquisition module, a dual serial port module and a CAN communication module.

In addition, the GMAC channel multiplexing system based on the domestic MCU chip can also be applied to domestic protection and automation equipment, domestic intelligent substation communication equipment and the like.

The beneficial technical effects of the invention are as follows:

the invention utilizes the FPGA and the GMAC channel of the MCU to expand the external interface of the domestic MCU, and realizes the high-speed communication between the MCU and the external expansion equipment, and the MCU and the FPGA are connected only through a GMAC data line. The expansion of an IO port, the expansion of a network port, the expansion of a serial port, the expansion of a CAN communication port and the expansion of a self-defined synchronous bus CAN be realized by utilizing a GMAC channel and an FPGA on a single processor, so that the hardware design is simplified, the system cost is greatly reduced, and the high cost performance is realized. In addition, the method is applied to home-made protection and automation equipment and home-made intelligent substation communication equipment, can realize synchronous processing of multiple platforms by multiple CPUs, and is high in cost performance and flexibility.

Drawings

Fig. 1 is a general circuit connection block diagram of the present invention.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings.

As shown in fig. 1, the GMAC channel multiplexing system based on the domestic MCU chip of the present invention includes a master MCU chip, a slave MCU chip, and an FPGA chip, where the FPGA chip and the master MCU chip are connected by using a GMAC channel, and a "BUS Conv" interface and an "Addr Oper" interface in the FPGA chip implement mapping from the GMAC interface to an expansion device channel, so that the master MCU chip can implement communication with an expansion device inside the FPGA chip through the GMAC interface. Each high-speed bus of the FPGA chip CAN be connected with one MCU chip to realize the expansion of a plurality of devices, wherein the main MCU chip expands the optical interface time synchronization module, the dual Ethernet module, the BO outlet control module, the BI acquisition module, the dual serial port module and the CAN communication module, and the main MCU chip communicates with other intelligent board cards through the expanded CAN communication module and the synchronous data module.

The CPU chips all adopt a CortexA7 quad-core domestic ARM chip, the highest operating frequency of the chip is 1.2GHz, DDR3SDRAM, SD card and NandFlash extension are supported, a 32K instruction cache and a 32K data cache are arranged in the chip, a USB controller and a network controller are provided, and meanwhile, a GMAC interface of T3 needs 14 signal ends, 4 data sending ends, 4 data receiving ends, a sending clock end, a receiving data error correction end, a receiving data control end, a sending data control end and a sending enabling end; the FPGA chip selects and uses a domestic FPGA chip and comprises 27k logic resources and 256pin pins.

The domestic MCU chip usually only has one GMAC channel, and normal communication of only one extended channel can be ensured by using a program of a linux general driver. The invention defines a set of high-speed data exchange bus by user, and the defined specific bus protocol comprises GMAC fixed byte transmission message identification code, message type identification, message sequence number identification, message byte length and data which needs to be received and transmitted actually. And in an FPGA interrupt period, the MCU and the expansion equipment read data from the high-speed data exchange bus and write new data into the high-speed data exchange bus. Through self-defined bus stipulations, guarantee that the expansion equipment analyzes to correct message, through self-defined data bus, the data transmission rate of uplink and downlink all can reach 1000Mbps, has realized the multiplexing of GMAC passageway, has simplified hardware design, has improved efficiency.

Although specific embodiments of the present invention have been described above, it will be appreciated by those skilled in the art that these are merely examples and that many variations or modifications may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is therefore defined by the appended claims.

Claims

1. The utility model provides a GMAC channel multiplexing system based on homemade MCU chip which characterized in that: including the MCU chip, the MCU chip passes through the SPI interface, the GMAC interface is connected with the FPGA chip, the FPGA chip links to each other with the extension equipment through a plurality of expansion interfaces, configures a plurality of expansion interfaces through the SPI interface, by FPGA chip control communication interrupt management, adopts specific bus stipulation, through the GMAC interface carries out a plurality of expansion interfaces in the FPGA chip and the data transfer between the MCU chip is inside to be provided with specific data buffer memory, specific data buffer memory is used for the data of storage through the GMAC interface conveying, realizes GMAC channel multiplexing, specific bus stipulation contains the transmission message identification code of the fixed byte of GMAC, message type sign, message serial number sign, message byte length and the data that actual need received and dispatched.

2. The GMAC channel multiplexing system based on the domestic MCU chip as claimed in claim 1, characterized in that: and the BUS Conv module and the Addr Oper module of the FPGA chip are used for mapping the SPI interface and the GMAC interface of the FPGA chip and the channels of the corresponding expansion equipment.

3. The GMAC channel multiplexing system based on the domestic MCU chip as claimed in claim 2, characterized in that: the expansion interface comprises an expansion optical port time synchronization module, a dual Ethernet module, a BO outlet control module, a BI acquisition module, a dual serial port module and a CAN communication module.