CN103092806A - Data transmission method and data transmission system based on serial peripheral interface (SPI) data transmission timing sequences - Google Patents
Data transmission method and data transmission system based on serial peripheral interface (SPI) data transmission timing sequences Download PDFInfo
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Abstract
The invention discloses a data transmission method and a data transmission system based on serial peripheral interface (SPI) data transmission timing sequences. The data transmission method based on the SPI data transmission timing sequences comprises the following steps: outputting SPI clock in effective status by a main device and sending a read\write mark of 1 byte, a start address (SA) of 2 byte and read\write data length (Len) of the 2 byte, receiving the read\write mark, SA and Len by a secondary device according to the SPI clock output by the main device and the SPI data transmission timing sequences, and sending data with SA and Len byte as a first address to the main device according to the SPI data transmission timing sequences and the read\write mark or storing the data of the Len byte received by the main device to local storage space with SA as the first address. Due to the fact that the Len byte is sent continuously in one frame data, and the data of the Len byte do not need to be sent by being placed on Len frame data like the prior art, transmission effects are improved largely.
Description
Technical field
The present invention relates to the communication technology, relate in particular to a kind of data transmission method and system based on SPI data transmission sequential.
Background technology
SPI(Serial Peripheral Interface, serial peripheral interface) be Motorola(Motorola) at first define on its MC68HCXX series processors.The SPI interface is widely used in carrying out synchronous serial-data transmission between CPU and peripheral low speed devices.The SPI interface is with master-slave mode work, and this pattern has a main device and one or more from device usually, and its interface can comprise following four kinds of signals:
(1) MOSI – master goes out from entering data line, i.e. main device data output, from the data line of device data input;
(2) MISO – master enters from going out data line, i.e. main device data input, from the data line of device data output;
(3) SCLK – clock signal is produced by main device;
(4)/SS – is from the device enable signal, controlled by main device, is used for main device and when communicating by letter by the SPI interface bus from device, selects one of them effective from device with a plurality of.
The form of one frame SPI data is as shown in table 1 below:
Table 1
| W/R?flag | Address | W/R? |
| 1 byte read/write flag | 2 byte read/write address | 2 byte read/write data |
At present, existing general SPI frame traffic process is: main device sends the read/write flag of 1 byte, then sends the read/write address of two bytes; To according to read/write flag, 2 byte datas be read from this address to 2 byte datas that main device sends or the reception main device sends subsequently and write this address from device.
For the SPI interface communication, also can read or clock edge polarity when changing data by clock polarity CPOL being set, arranging.Fig. 1 a and Fig. 1 b show the SPI data transmission sequential schematic diagram under different clocks polarity; Wherein, if CPOL is set to 0, as shown in Figure 1a, the transmit leg of data is changed data at the negative edge of clock sclk, and the take over party of data is at the rising edge reading out data of data; If CPOL is set to 1, as shown in Fig. 1 b, the transmit leg of data is changed data at the rising edge of clock sclk, and the take over party of data is at the negative edge reading out data of data.
Yet the present inventor finds, in actual applications, the communication efficiency of existing communication mode based on SPI is not high, has the demand that improves communication efficiency.
Summary of the invention
Embodiments of the invention provide a kind of data transmission method based on SPI data transmission sequential and logical device and single-chip microcomputer, in order to improve communication efficiency.
According to an aspect of the present invention, provide a kind of data transmission method based on SPI data transmission sequential, having comprised:
The SPI clock of main device output effective status, and send the read/write flag of 1 byte, the start address SA of 2 bytes, and the read/write data length L en of 2 bytes;
From the SPI clock of device according to described main device output, according to SPI data transmission sequential, receive described read/write flag, SA, Len;
Described from device according to SPI data transmission sequential, according to described read/write flag, sending first address to described main device is data SA, the Len byte, or stores into the local storage space that first address is SA from the data that described main device receives the Len byte.
Wherein, described according to described read/write flag, sending first address to described main device is data SA, the Len byte, or stores into the local storage space that first address is SA from the data that described main device receives the Len byte and specifically comprise:
If described is the value of reading to indicate from the definite read/write flag that receives of device, after receiving read/write data length L en, according to SPI data transmission sequential, the first address that this locality is stored is that data SA, the Len byte send to described main device;
If described is to write the value of sign from the definite read/write flag that receives of device, after receiving read/write data length L en, according to SPI data transmission sequential, the data that receive the Len byte of described main device transmission store in the local storage space that first address is SA.
Wherein, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte are all by same data line transmission; Perhaps,
If described read/write flag is the value of reading to indicate, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte enters from going out the transmission of MISO data line by the master; If described read/write flag is to write the value of sign, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte goes out from entering the transmission of MOSI data line by the master.
According to another aspect of the present invention, also provide a kind of data transmission system based on SPI data transmission sequential, having comprised:
Main device is used for the SPI clock of output effective status, and sends the read/write flag of 1 byte, the start address SA of 2 bytes, and the read/write data length L en of 2 bytes;
From device, be used for the SPI clock according to described main device output, according to SPI data transmission sequential, receive described read/write flag, SA, Len; And according to SPI data transmission sequential, according to described read/write flag, sending first address to described main device is data SA, the Len byte, or stores into the local storage space that first address is SA from the data of described main device reception Len byte.
Wherein, describedly specifically comprise from device:
The command reception module is used for the SPI clock according to described main device output, according to SPI data transmission sequential, receives described read/write flag, SA, Len; And if determine that described read/write flag is the value of reading to indicate, sends the data transmitted signal; If determine that described read/write flag is to write the value of sign, send data reception signal; And after the described read/write data length L en of reception is complete, send commencing signal;
Data transmission blocks, if be used for receiving the data transmitted signal that described command reception module sends, after receiving described commencing signal, according to SPI data transmission sequential, the first address that this locality is stored is that data SA, the Len byte send to described main device;
Data reception module, if be used for receiving the data reception signal that described command reception module sends, after receiving described commencing signal, according to SPI data transmission sequential, the data that receive the Len byte of described main device transmission store in the local storage space that first address is SA.
Wherein, described main device and from being connected with clock line and a data lines between device; And
Described SPI clock transmits by described clock line, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte are all by this data line transmission.
Perhaps, described main device and from being connected with clock line between device, main entering from going out the MISO data line, and mainly go out from entering the MOSI data line; And
Described SPI clock is by described clock line transmission;
If described read/write flag is the value of reading to indicate, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte is by described MISO data line transmission;
If described read/write flag is to write the value of sign, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte is by described MOSI data line transmission.
Preferably, by same crystal oscillator as described main device with from the reference clock of device;
Described main device is according to the described SPI clock of described reference clock output; Describedly generate processing clock from device according to described reference clock, and use described processing clock to carry out the transmission of data, receive and processing.
Preferably, described main device is single-chip microcomputer, and described is logical device from device.
Described logical device also is used for by MDIO interface and main-machine communication.
In the technical scheme that the embodiment of the present invention provides, due to existing SPI data frame structure is improved, SPI Frame after improvement can send the Len byte continuously in frame data, transmit in the Len frame data and needn't the data of Len byte be placed on respectively as prior art, greatly improved transfer efficiency, that is improved communication efficiency, improved on the whole the speed of data transmission.
And the present invention also provides a kind of SPI communication mode of single work pattern for single work application scenario, can save the hardware resource of master and slave device, the pin resource of especially master and slave device.
Further, use same crystal oscillator to provide reference clock for master and slave device in the present invention, both can guarantee that the processing clock in main device is consistent with the phase place of processing clock from device, be convenient to synchronously; Can guarantee again to output to from the driving force of the reference clock of device enough, prevent the loss of data phenomenon.
Description of drawings
Fig. 1 a, 1b are the SPI data transmission sequential schematic diagram under the different clocks polarity CPOL of prior art;
Fig. 2 is the schematic diagram that principal and subordinate's device of the embodiment of the present invention communicates by the SPI interface;
Fig. 3 is that the main device of the embodiment of the present invention is from the method flow diagram from the device reading out data;
Fig. 4 is that the main device of the embodiment of the present invention is to the method flow diagram from the device data writing;
Fig. 5 be the embodiment of the present invention realize the schematic diagram of communicating by letter between single-chip microcomputer and main frame by logical device;
Fig. 6 is the SPI interface schematic diagram of single work pattern of the embodiment of the present invention;
Fig. 7 is the inner structure block diagram from device of the embodiment of the present invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to accompanying drawing and enumerate preferred embodiment, the present invention is described in more detail.Yet, need to prove, many details of listing in instructions are only in order to make the reader to one or more aspects of the present invention, a thorough understanding be arranged, even if do not have these specific details also can realize these aspects of the present invention.
The terms such as " module " used in this application, " system " are intended to comprise the entity relevant to computing machine or chip or programmable logic device (PLD), such as but not limited to hardware, firmware, combination thereof, software or executory software.
The present inventor analyzes existing communication mode based on SPI: owing to only transmitting the data of 2 bytes in frame data; If follow-up 2 byte datas that also need to send neighbor address just also need send the next frame data again, still to comprise the read/write flag of 1 byte in the next frame data, and the read/write address of two bytes; Therefore data transmission efficiency is low, and namely communication efficiency is low.Thus, the present inventor considers, adopts the mode of another kind of frame structure to transmit the SPI data, to improve communication efficiency.
The frame structure of the transmission SPI data that the embodiment of the present invention provides is as shown in table 2 below:
Table 2
| W/R?flag | Start?address | Length | W/R? |
| 1 byte read/write flag | 2 byte start addresses | 2 byte read/write data length | Continuous read/write data |
In communication mode based on SPI provided by the invention, still adopt the SPI data transmission sequential identical with the SPI communication mode of prior art, but the frame format of the transmission of data adopts the frame format shown in above-mentioned table 2: in the data of MOSI or MISO data above-the-line promotion, be followed successively by: the 1st read/write flag, the start address SA of 2 bytes, the read/write data length L en of 2 bytes that byte is 1 byte is continuous read/write data afterwards.The byte number of the continuous read/write data after wherein, the read/write data length of 2 bytes is used in reference to and illustrates; The start address of 2 bytes indicates the first address in the memory address of continuous read/write data.The Len maximum of 2 bytes can reach 64M, and this namely means, can transmit continuously at most the data of 64M byte in frame data, thereby has greatly improved transfer efficiency.Certainly, Len can be also minimum value 1.
In the data transmission system based on SPI data transmission sequential as shown in Figure 2, main device and between device, based on SPI data transmission sequential, the method for carrying out the SPI communication transmitting data according to above-mentioned frame format be: after receiving read/write flag that main device sends, SA, Len from device, according to described read/write flag, sending first address to described main device is data SA, the Len byte, or stores into the local storage space that first address is SA from the data of described main device reception Len byte.Concrete method flow is as shown in Fig. 3,4.
Wherein, Fig. 3 mainly illustrates main device based on SPI data transmission sequential from the method from the device reading out data, comprises the steps:
S301: main device begins to export the SPI clock of effective status, and sends the read/write flag of 1 byte.
Particularly, main device is exported effective SPI clock on the SCLK clock line; Effective, the idle condition of the SPI clock of serial synchronous can set in advance: if CPOL=0 is set, the idle condition of SPI clock is low level, it is exported the SPI clock of effective status after the high level by low transition, at this moment, the SPI clock transfers effective status to by idle condition; If CPOL=1, the idle condition of SPI clock is high level, and it is jumped to the SPI clock of exporting effective status after low level by high level, and at this moment, the SPI clock transfers effective status to by idle condition.
The effective SPI clock of main device output, and send the read/write flag of 1 byte on the MISO data line according to SPI data transmission sequential, the value of the read/write flag of this byte is specially the value of reading to indicate.Because SPI data transmission sequential has been introduced in background technology, repeat no more herein.
S302: after receiving read/write flag from device, after the value of determining this read/write flag is the value of reading to indicate, determine this time to be operating as read operation.
Particularly, from the SPI clock of device according to main device output, after receiving according to SPI data transmission sequential the 1st byte that main device sends, after the value of determining this byte is the value of reading to indicate, determine this time to be operating as read operation.
S303: main device continues to send the start address SA of 2 bytes, and the read/write data length L en of 2 bytes.
Particularly, main device after the read/write flag that has sent 1 byte, continues to send the start address SA of 2 bytes according to SPI data transmission sequential, and the read/write data length L en of 2 bytes.
S304: receive the start address SA of 2 bytes of main device transmission from device, and the read/write data length L en of 2 bytes.
Particularly, receive the start address SA of 2 bytes of the follow-up transmission of main device according to SPI data transmission sequential from device, and the read/write data length L en of 2 bytes.
From device according to before the value of reading to indicate that receives, be that SA, data byte length are that the data of Len read and prepare in buffer memory to send with the first address of this locality storage.
S305: be that SA, data byte length are that the data of Len send to main device successively with the first address of this locality storage from device.
Particularly, from device after last Bit data of the read/write data length L en that receives 2 bytes, according to SPI data transmission sequential, after next SPI clock arrives, be that SA, data byte length are that the data of Len send to main device successively with the first address of preparing in buffer memory.Send method and the prior art of data of Len byte from the method for the data of device transmission 2 bytes identically from device, repeat no more herein.
S306: after main device has received the data of Len byte, stop exporting effective SPI clock.
Particularly, main device is according to SPI data transmission sequential, and after having received the data of the Len byte that sends from device, the state of SPI clock is set to idle condition, stops exporting effective SPI clock, completes the transmission of these frame data.
Fig. 4 mainly illustrates main device based on SPI data transmission sequential to the method from the device data writing, comprises the steps:
S401: main device begins to export the SPI clock of effective status, and sends the read/write flag of 1 byte.
Particularly, the effective SPI clock of main device output, and send the read/write flag of 1 byte on the MOSI data line according to SPI data transmission sequential, the value of the read/write flag of this byte is specially the value of writing sign.
S402: after receiving read/write flag from device, after the value of determining this read/write flag is to write the value of sign, determine this time to be operating as write operation.
S403: main device continues to send the start address SA of 2 bytes, and the read/write data length L en of 2 bytes.
S404: receive the start address SA of 2 bytes of main device transmission from device, and the read/write data length L en of 2 bytes.
S405: main device is that the data of Len are successively to sending from device with data byte length.
Particularly, main device according to SPI data transmission sequential, continues to send the data of Len byte on the MOSI data line after having sent the read/write data length L en of 2 bytes.
S406: after receiving from device the data that byte length is Len, be stored in the storage space that local first address is SA.
Particularly, according to the sign of writing that receives, after receiving the read/write data length L en of 2 bytes, begin to receive the data of Len byte from device; In the data that receive Len byte, storing the data that receive into local first address from device is that SA, length are the storage space of Len.
In the occasion that single-chip microcomputer and main frame communicate, the serial line interface commonly used due to main frame is USB or MDIO interface, and single-chip microcomputer serial line interface commonly used is the SPI interface; Therefore, usually pass through logical device between single-chip microcomputer and main frame, such as FPGA(Field Programmable Gata Array, field programmable gate array) or PAL(Programmable Array Logic, programmable logic array), carry out the conversion of interface.
For example, as shown in Figure 5, communicate by letter by the MDIO interface bus between main frame and logical device, communicate by letter by the SPI interface bus between logical device and single-chip microcomputer, thereby realize communicating by letter by logical device between single-chip microcomputer and main frame.Generally speaking, single-chip microcomputer is as above-mentioned main device, logical device as above-mentioned from device; If the SPI interface between logical device and single-chip microcomputer adopts SPI communication mode of the present invention, can greatly improve the efficient of every transmission frame number certificate, thus the whole transmission speed that improves.
Further, be the interface of single work pattern due to the MDIO interface, i.e. communicating by letter between synchronization, main frame and logical device can only be unidirectional data transmission; Because of the restriction of MDIO interface, at synchronization, single-chip microcomputer can only be also unidirectional data transmission through communicating by letter between logical device and main frame; Analyze based on this, the present inventor considers that the dual-mode with existing SPI interface changes single work pattern into, both can satisfy the communication requirement of system, can save again the hardware resource of system, especially the hardware resource of the pin of single-chip microcomputer and logical device.Specifically as shown in Figure 6, the MOSI line in the SPI interface of Fig. 5 and MISO line are merged into SPI data line in Fig. 6.And can be to send on the SPI data line shown in Fig. 6 in the data that send on the MOSI data line in above-mentioned steps S301-306, can be also to send on the SPI data line shown in Fig. 6 in the data that send on the MISO data line in above-mentioned steps S4301-406.
In other words, under single work pattern the SPI interface as shown in Figure 6, main device (single-chip microcomputer) and from being connected with clock line SCLK and a SPI data line between device (logical device); The SPI clock is by described clock line SCLK transmission; The read/write data length L en of the start address SA of the read/write flag of 1 byte, 2 bytes, 2 bytes, and the data of described Len byte are all the transmission of SPI data line by same data line; Like this, single-chip microcomputer and logical device have all reduced by a hardware pin that is used for SPI interface the transmission of data, have saved the hardware resource of single-chip microcomputer and logical device.
Under dual-mode the SPI interface as shown in Figure 3, main device and from being connected with clock line SCLK between device, main entering from going out the MISO data line, and mainly go out from entering the MOSI data line; The SPI clock is by described clock line SCLK transmission; If the read/write flag that main device sends is the value of reading to indicate, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte enters from going out the transmission of MISO data line by the master; If the read/write flag that main device sends is to write the value of sign, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte goes out from entering the transmission of MOSI data line by the master.
For the ease of synchronously, master and slave device uses the homology clock usually; Way in the prior art is, crystal oscillator output reference clock is to main device, after the phase-locked reference clock of main device, exports system's processing clock of this device and from the reference clock of device; After phase-locked to the reference clock of main device output from device, export the processing clock of this device.Main device generates the SPI clock according to system's processing clock of this device, from processing clock reception, transmission, the deal with data of device according to this device.Yet the present inventor finds, there is defective in the method, is mainly that main device outputs to from the driving force of the reference clock of device inadequate, might produce the loss of data phenomenon.
Therefore, adopt the stronger crystal oscillator of driving force simultaneously as described main device and reference clock from device in the present invention.Main device is exported the processing clock of this device according to described reference clock, according to the described SPI clock of processing clock generation of this device; Describedly generate processing clock from device according to described reference clock, and use described processing clock to carry out the transmission of data, receive and processing.Like this, both can guarantee that the processing clock in main device was consistent with the phase place of processing clock from device, be convenient to synchronous; Can guarantee again to output to from the driving force of the reference clock of device enough, prevent the loss of data phenomenon.
The above-mentioned a kind of concrete inner structure from device as shown in Figure 7, comprising: command reception module 701, data transmission blocks 702, data reception module 703.
Command reception module 701 is used for the SPI clock according to described main device output, according to SPI data transmission sequential, receives described read/write flag, SA, Len; And if determine that described read/write flag is the value of reading to indicate, send the data transmitted signals to data transmission blocks 702; If determine that described read/write flag is to write the value of sign, send data reception signal to data reception module 703; And after the described read/write data length L en of reception is complete, send commencing signal; This commencing signal both can send to data transmission blocks 702, also can send to data reception module 703, depended on the circumstances; Generally speaking, in the situation that determine that described read/write flag is the value of reading to indicate, command reception module 701 sends to data transmission blocks 702 with commencing signal; In the situation that determine that described read/write flag is to write the value of sign, command reception module 701 sends to data reception module 703 with commencing signal.
If data transmission blocks 702 is used for receiving the data transmitted signal that command reception module 701 sends, after receiving described commencing signal, according to SPI data transmission sequential, the first address that this locality is stored is that data SA, the Len byte send to described main device;
If data reception module 703 is used for receiving the data reception signal that command reception module 701 sends, after receiving described commencing signal, according to SPI data transmission sequential, the data that receive the Len byte of described main device transmission store in the local storage space that first address is SA.
In the technical scheme that the embodiment of the present invention provides, due to existing SPI data frame structure is improved, SPI Frame after improvement can send the Len byte continuously in frame data, transmit in the Len frame data and needn't the data of Len byte be placed on respectively as prior art, greatly improved transfer efficiency, that is improved communication efficiency, improved on the whole the speed of data transmission.
And the present invention also provides a kind of SPI communication mode of single work pattern for single work application scenario, can save the hardware resource of master and slave device, the pin resource of especially master and slave device.
Further, use same crystal oscillator to provide reference clock for master and slave device in the present invention, both can guarantee that the processing clock in main device is consistent with the phase place of processing clock from device, be convenient to synchronously; Can guarantee again to output to from the driving force of the reference clock of device enough, prevent the loss of data phenomenon.
One of ordinary skill in the art will appreciate that all or part of step that realizes in above-described embodiment method is to come the relevant hardware of instruction to complete by program, this program can be stored in a computer read/write memory medium, as: ROM/RAM, magnetic disc, CD etc.
The above is only the preferred embodiment of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. data transmission method based on SPI data transmission sequential comprises:
The SPI clock of main device output effective status, and send the read/write flag of 1 byte, the start address SA of 2 bytes, and the read/write data length L en of 2 bytes;
From the SPI clock of device according to described main device output, according to SPI data transmission sequential, receive described read/write flag, SA, Len;
Described from device according to SPI data transmission sequential, according to described read/write flag, sending first address to described main device is data SA, the Len byte, or stores into the local storage space that first address is SA from the data that described main device receives the Len byte.
2. the method for claim 1, wherein, described according to described read/write flag, sending first address to described main device is data SA, the Len byte, or stores into the local storage space that first address is SA from the data that described main device receives the Len byte and specifically comprise:
If described is the value of reading to indicate from the definite read/write flag that receives of device, after receiving read/write data length L en, according to SPI data transmission sequential, the first address that this locality is stored is that data SA, the Len byte send to described main device;
If described is to write the value of sign from the definite read/write flag that receives of device, after receiving read/write data length L en, according to SPI data transmission sequential, the data that receive the Len byte of described main device transmission store in the local storage space that first address is SA.
3. method as claimed in claim 2, wherein, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte are all by same data line transmission; Perhaps,
If described read/write flag is the value of reading to indicate, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte enters from going out the transmission of MISO data line by the master; If described read/write flag is to write the value of sign, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte goes out from entering the transmission of MOSI data line by the master.
4. the data transmission system based on SPI data transmission sequential, is characterized in that, comprising:
Main device is used for the SPI clock of output effective status, and sends the read/write flag of 1 byte, the start address SA of 2 bytes, and the read/write data length L en of 2 bytes;
From device, be used for the SPI clock according to described main device output, according to SPI data transmission sequential, receive described read/write flag, SA, Len; And according to SPI data transmission sequential, according to described read/write flag, sending first address to described main device is data SA, the Len byte, or stores into the local storage space that first address is SA from the data of described main device reception Len byte.
5. system as claimed in claim 4 wherein, describedly specifically comprises from device:
The command reception module is used for the SPI clock according to described main device output, according to SPI data transmission sequential, receives described read/write flag, SA, Len; And if determine that described read/write flag is the value of reading to indicate, sends the data transmitted signal; If determine that described read/write flag is to write the value of sign, send data reception signal; And after the described read/write data length L en of reception is complete, send commencing signal;
Data transmission blocks, if be used for receiving the data transmitted signal that described command reception module sends, after receiving described commencing signal, according to SPI data transmission sequential, the first address that this locality is stored is that data SA, the Len byte send to described main device;
Data reception module, if be used for receiving the data reception signal that described command reception module sends, after receiving described commencing signal, according to SPI data transmission sequential, the data that receive the Len byte of described main device transmission store in the local storage space that first address is SA.
6. system as claimed in claim 5, wherein, described main device and from being connected with clock line and a data lines between device; And
Described SPI clock transmits by described clock line, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte are all by this data line transmission.
7. system as claimed in claim 5, wherein, described main device and from being connected with clock line between device, mainly entering from going out the MISO data line, and mainly go out from entering the MOSI data line; And
Described SPI clock is by described clock line transmission;
If described read/write flag is the value of reading to indicate, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte is by described MISO data line transmission;
If described read/write flag is to write the value of sign, the read/write data length L en of the start address SA of the read/write flag of described 1 byte, 2 bytes, 2 bytes, and the data of described Len byte is by described MOSI data line transmission.
8. described system as arbitrary in claim 4-7, wherein, by same crystal oscillator as described main device and reference clock from device;
Described main device is according to the described SPI clock of described reference clock output; Describedly generate processing clock from device according to described reference clock, and use described processing clock to carry out the transmission of data, receive and processing.
9. system as claimed in claim 8, is characterized in that, described main device is single-chip microcomputer, and described is logical device from device.
10. system as claimed in claim 9, wherein, described logical device also is used for by MDIO interface and main-machine communication.
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| CN201310019727XA Pending CN103092806A (en) | 2013-01-18 | 2013-01-18 | Data transmission method and data transmission system based on serial peripheral interface (SPI) data transmission timing sequences |
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| CN109327284A (en) * | 2018-11-27 | 2019-02-12 | 联想(北京)有限公司 | Data transmission method, device and electronic equipment |
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| CN108009107B (en) * | 2017-07-20 | 2019-11-05 | 北京车和家信息技术有限责任公司 | Method, apparatus, storage medium and the system of data transmission |
| CN111061671A (en) * | 2019-12-13 | 2020-04-24 | 上海灵动微电子股份有限公司 | SPI transmission control method, sending equipment and receiving equipment |
| CN112445741A (en) * | 2019-09-03 | 2021-03-05 | 舜宇光学（浙江）研究院有限公司 | Data transmission method and system based on SPI protocol |
| CN112597095A (en) * | 2020-12-14 | 2021-04-02 | 珠海格力电器股份有限公司 | Communication control method and device, electronic equipment and computer readable storage medium |
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| CN112597095A (en) * | 2020-12-14 | 2021-04-02 | 珠海格力电器股份有限公司 | Communication control method and device, electronic equipment and computer readable storage medium |
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