CN202871257U - GPIO module based on DMA and capable of updating LED display screen - Google Patents

GPIO module based on DMA and capable of updating LED display screen Download PDF

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Publication number
CN202871257U
CN202871257U CN2012205191783U CN201220519178U CN202871257U CN 202871257 U CN202871257 U CN 202871257U CN 2012205191783 U CN2012205191783 U CN 2012205191783U CN 201220519178 U CN201220519178 U CN 201220519178U CN 202871257 U CN202871257 U CN 202871257U
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China
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module
led
control
control module
signal
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CN2012205191783U
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孙进军
周毅
奚谷枫
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DONGGUAN RUNFENG ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd
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DONGGUAN RUNFENG ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd
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Abstract

The utility model provides a GPIO module based on a DMA and capable of updating an LED display screen. The GPIO module based on the DMA and capable of updating the LED display screen comprises a control register module, an FIFO module, an LED_ABCD control module, an LED_OEN control module, an LED_STB control module, an LED_CLKS control module, a data output control module, and an IObank selection module. According to the utility model, a fast transmission channel from a memory to an IO pin is provided for data, and an ample bandwidth condition is provided for the LED display screen to a certain extent. The LED_CLKS control module provides a clock synchronizing with the data and a plurality of same-frequency and different-phase clocks, and these same-frequency and different-phase clocks provide a condition for expanding the LED display screen in the height direction. All control signals for the LED display screen are automatically generated by hardware, and the complexity of late development is greatly simplified. According to the utility model, the above characteristics are integrated, and the products of the utility model have the advantages of less peripheral circuit, simple design, strong screen updating ability, etc.

Description

A kind of GPIO module that can brush LED display based on DMA
Technical field
The utility model relates to LED display brush screen technology, relates in particular to the brush screen technology that is applicable to high bandwidth, large-sized LED display.
Background technology
The develop rapidly of LED display technology, the display screen color is popularized to full-color from single, double look, and displaying contents is converted into video by the literal picture and shows in real time, and the refresh capability of LED display is had higher requirement.In the control card of traditional LED display, often need to add that FPGA carries out the brush screen operation of big data quantity.Like this can be higher at production cost, and implement also more complicated.
The utility model content
The purpose of this utility model is to provide a kind of GPIO module that can brush LED display based on DMA, is well positioned to meet the brush screen requirement of LED display, and has reduced complicacy and the production cost of product design.
The technical solution of the utility model is as follows:
A kind of GPIO module that can brush LED display based on DMA comprises following structure:
The control register module links to each other with the CPU module, is used for control store instruction and status data;
Fifo module links to each other with the data output control module with dma module, is used for the buffering of data;
The LED_ABCD control module selects module to link to each other with control register module, LED_STB control module, LED_CLKS control module and IObank, is used for the sequential of the row selection signal of control LED display interface;
The LED_OEN control module selects module to link to each other with control register module, LED_STB control module, LED_CLKS control module and IObank, is used for the sequential of the enable signal of control LED display interface;
The LED_STB control module selects module to link to each other with control register module, LED_ABCD control module, LED_OEN control module, LED_CLKS control module and IObank, is used for the sequential of the data latch signal of control LED display interface;
The LED_CLKS control module selects module to link to each other with control register module, LED_ABCD control module, LED_OEN control module, LED_STB control module and IObank, is used for the sequential of each clock signal of control LED display interface;
The data output control module selects module to link to each other with control register module, fifo module and IObank, is used for form and the bit wide of control output data;
IObank selects module, link to each other with control register module, LED_ABCD control module, LED_OEN control module, LED_STB control module, LED_CLKS control module, data output control module and LED display module, be used for the control signal of LED display, clock signal and data are exported at different IO bank respectively.
Its further technical scheme is: described LED_ABCD control module inside has the counting module of increasing progressively and shift module, the LED_CLKS signal that the LED_CLKS control module is sent here is counted, produced row selection signal by increasing progressively count mode and shift mode respectively; What data configure first every row has, and automatically to the data counting, delegation counts when expiring by MUX auto-changing row selection signal; The LED_STB signal controlling of being sent here by the LED_STB control module increases progressively the clear operation of counting module and shift module; And reception is from the control of the control signal of control register module.
Its further technical scheme is: described LED_OEN control module inside has counter, the LED_CLKS signal that the LED_CLKS control module is sent here is counted, by comparer the value of counter and the value in the control register module are compared the level state that decides LED_OEN; The clear operation of the LED_STB signal controlling counter of being sent here by the LED_STB control module; And reception is from the control of the control signal of control register module.
Its further technical scheme is: described LED_STB control module inside has counter, the LED_CLKS signal that the LED_CLKS control module is sent here is counted, by comparer the value of counter and the value in the control register module are compared the level state that decides LED_STB; And reception is from the control of the control signal of control register module.
Its further technical scheme is: described LED_CLKS control module inside has counter and comparer, system clock is produced the LED_DATA_CLK signal by counter and comparer, and by frequency divider the LED_DATA_CLK signal frequency split is obtained the LED_CLKS signal; And reception is from the control of the control signal of control register module.
In the technique scheme:
Described CPU refers to Central Processing Unit, central processing unit.
Described DMA refers to Direct Memory Access, direct memory access.
Described FIFO refers to First Input First Output, First Input First Output.
Described GPIO refers to General Purpose Input Output, universal input/output.
Useful technique effect of the present utility model is:
(1) the utility model provides the high-speed data channel of an internal memory to chip pin, dma module takes out data and then directly write in the fifo module from internal memory, output to IObank after the data output control module takes out data and then according to relevant configuration data processed and select module from fifo module, very large brush screen bandwidth can be provided like this.
(2) LED_CLKS control module of the present utility model is for generation of a plurality of same frequencys but the clock of out of phase, and the polarity of these clocks can be regulated, and the length of significant level also can be regulated, and is in order to adapt to different LED display like this.The data of output can be upgraded in each phase place, and each phase place can a corresponding clock the effective edge edge, the clock that so just can guarantee each out of phase can both sample different data on their effective edge edge, as: the LED_CLKS control module produces altogether 3 with the out of phase clock of frequency, such clock period just is divided into 3 phase places, each phase place has Data Update, the corresponding clock edge of the data of each phase place, so just data are distributed in 3 clock zones, accordingly just the width of data line 3 times have been expanded, if be originally 32bit, just become 96bit after the expansion.Utilize this method, just can in height expand LED display, remedied on the LED display length and can not expand oversize problem.
(3) the utility model comprises LED_ABCD control module, LED_OEN control module, LED_STB control module, can produce automatically according to configuration the number control signal of LED display interface.The LED_ABCD control module can produce the row selection signal of LED display.The LED_OEN control module is for generation of enable signal, and its polarity is adjustable, is used for applicable different display screen; The width of its significant level can be regulated, and is used for regulating the brightness of LED display.The LED_STB control module is used for the data that LED display latchs output for generation of data latch signal.These signals are all produced automatically by hardware, have reduced to a great extent the complexity of design, make to utilize product of the present utility model to be simple and easy to use.
(4) IObank of the present utility model selects module can select control signal, clock and the data that will export at last, output on any bank of IO pin, make like this utilize product of the present utility model to use can be very flexible, the problem of having avoided pin multiplexing to cause.
(5) can select in the data output control module of the present utility model that data among the FIFO are divided into several fractions sends successively, as: data are 32bit in the fifo module, and the data output control module can select once to export a 32bit like this; Perhaps at twice, export 16bit at every turn; Perhaps divide four times, export 8bit at every turn.So also improved the dirigibility that this utility model is used.
(6) LED_CLKS control module of the present utility model also provides one and data with clock signal frequently, i.e. corresponding valid data of clock edge, the condition that this provides for other brush screen pattern of later on expansion.
Description of drawings
Fig. 1 is structured flowchart of the present utility model.
Fig. 2 is the structured flowchart of LED_ABCD control module.
Fig. 3 is the structured flowchart of LED_OEN control module.
Fig. 4 is the structured flowchart of LED_STB control module.
Fig. 5 is the structured flowchart of LED_CLKS control module.
Embodiment
Below in conjunction with accompanying drawing, by embodiment the utility model is specifically described.
As shown in Figure 1, the utility model selects module 8 to consist of by control register module 1, fifo module 2, LED_ABCD control module 3, LED_OEN control module 4, LED_STB control module 5, LED_CLKS control module 6, data output control module 7 and IObank.
The below is elaborated to each several part:
Control register module 1, select module 8 to link to each other with CPU module 10, LED_ABCD control module 3, LED_OEN control module 4, LED_STB control module 5, LED_CLKS control module 6, data output control module 7 and IObank, be used for accepting and storing the instruction that CPU module 10 is sent, then control the operator scheme of other connected modules according to relevant instruction.
Fifo module 2 links to each other with dma module 11, data output control module 7.After dma module 11 is activated, also have living space if fifo module 2 is inner, just can send request signals to dma module 11, dma module 11 receives behind the request signal just data writing in the fifo module 2, and then returns an answer signal to fifo module 2.Fifo module 2 is mainly used in the temporary effect of data, is used for the speed of coupling CPU and IO pin.Be 32bit with the FIFO width design in the present embodiment, depth design is 16.
LED_ABCD control module 3 selects module 8 to link to each other with control register module 1, LED_STB control module 5, LED_CLKS control module 6 and IObank, is used for the row selection signal of control LED display.Inner structure as shown in Figure 2, this inside modules has one to increase progressively counting module 13 and a shift module 14, the LED_CLKS signal is counted, two kinds of mode producing row selection signals are arranged: a kind of is to increase progressively count mode, can select 1,1/2,1/4,1/8 and 1/16 scan pattern; A kind of is shift mode, can select 1,1/2,1/3 and 1/4 scan pattern.Configure first in this example every row what data are arranged, LED_ABCD control module 3 can be counted data automatically, by MUX 15 auto-changing row selection signals, the LED_STB signal was used for the clear operation that control increases progressively counting module 13 and shift module 14 when then delegation's meter was full.LED_CLKS signal among Fig. 2 is from LED_CLKS control module 6, and the LED_STB signal is from LED_STB control module 5, and all the other control signals are from control register module 1.
LED_OEN control module 4, select module 8 to link to each other with control register module 1, LED_STB control module 5, LED_CLKS control module 6 and IObank, the enable signal that is used for the control LED display, this signal can be controlled the brightness of LED display, its significant level width can be regulated, and is used for the brightness of control LED display; Its polarity also can configure, and is used for adapting to different LED display.Inner structure as shown in Figure 3, this inside modules has a counter 16, the LED_CLKS signal is counted, then comparer 17 compares the level state that decides LED_OEN with the value of counter 16 and the value in the control register module 1, and the LED_STB signal is used for the clear operation of control counter 16.LED_CLKS signal among Fig. 3 is from LED_CLKS control module 6, and the LED_STB signal is from LED_STB control module 5, and all the other control signals are from control register module 1.
LED_STB control module 5, select module 8 to link to each other with control register module 1, LED_ABCD control module 3, LED_OEN control module 4, LED_CLKS control module 6 and IObank, the data latch signal that is used for the control LED display produces an effective edge at this signal and shows along data are latched into LED display after data line is sent completely.Inner structure as shown in Figure 4, this inside modules has a counter 18, and the LED_CLKS signal is counted, then comparer 19 compares the level state that decides LED_STB with the value of counter 18 and the value in the control register module 1.LED_CLKS signal among Fig. 4 is from LED_CLKS control module 6, and all the other control signals are from control register module 1.
LED_CLKS control module 6, select module 8 to link to each other with control register module 1, LED_ABCD control module 3, LED_OEN control module 4, LED_STB control module 5 and IObank, for generation of one and synchronous clock signal and a plurality of same frequently out of phase clock signal of data.LED_CLKS control module 6 can be supported 1～8 with the out of phase clock of frequency in the present embodiment, and concrete clock number can be passed through register configuration.If the number of clock is configured to 3, the speed of then exporting data is 3 times of clock rate, and each clock period is divided into 3 phase places, and each phase place has the effective edge edge of a clock, so just data bus time-sharing multiplex to three clock zone of 32bit.If there are three LED display the outside, each LED display is with different clocks, but 3 LED display are all used the same group of data line, utilize like this out of phase of clock, can show respectively different contents on LED display.The inner structure of this module produces the LED_DATA_CLK signal by counter 20 and comparer 21 first as shown in Figure 5, then obtains the LED_CLKS signal by 22 pairs of LED_DATA_CLK signal frequency splits of frequency divider.Clock signal of system among Fig. 5 is produced by outer CPU, and control signal is from control register module 1.
Data output control module 7 selects module 8 to link to each other with control register module 1, fifo module 2 and IObank, for the bit wide of controlling the output data and speed etc.The data of FIFO inside are 32bit in the present embodiment, can be configured to 8bit, 16bit or 32bit output in data output control module 7.When being configured to 8bit, data output control module 7 is got 32bit data from fifo module 2, then divides to send to IObank selection module 8 for 4 times, can accomplish like this data in the internal memory are operated by byte, uses more flexible.
IObank selects module 8, links to each other with control register module 1, LED_ABCD control module 3, LED_OEN control module 4, LED_STB control module 5, LED_CLKS control module 6, data output control module 7 and LED display module 12.Be used for the control signal of LED display, clock signal and data are exported at different IO bank respectively, one has 20 IObank in the present embodiment, and each bank has 8 IO; The control signal of LED display, clock signal and data can be assigned on any one bank, more favourable to doing later on product solution like this, the situation of having avoided IO pin multiplexing in some cases to cause some functions normally not use.
Above-described control register module 1, fifo module 2, LED_ABCD control module 3, LED_OEN control module 4, LED_STB control module 5, LED_CLKS control module 6, data output control module 7 and IObank select module 8 to consist of together the utility model, i.e. GPIO module 9 among Fig. 1.
Basic composition module/the unit that forms above-mentioned each circuit module in the utility model is general module/unit.CPU module 10 among Fig. 1, dma module 11 and LED display module 12 are general module, only for signal, do not belong to the utility model.
The bus bandwidth of CPU module 10 and dma module 11 all is 32bit among the utility model embodiment, before 9 work of GPIO module, needs CPU module 10 to write relevant configuration information to control register module 1, is used for controlling the mode of operation of GPIO module 9.
After dma module 11 starts, when the request signal that detects fifo module 2, just data writing in the fifo module 2.When in detecting fifo module 2, data being arranged, data output control module 7 just can take out data successively from FIFO, then select module 8 output data according to configuration requirement to IObank, IObank selects module 8 to select different IO bank output data and control signal.
The topmost characteristics of the utility model are that LED_CLKS control module 6 can produce several with the out of phase clock of frequency, and these clocks also output on the IO pin, and the effective edge of the clock of each phase place is along corresponding different valid data.And the number of same frequency out of phase clock of output also can be configured according to actual conditions, can improve to a great extent like this dirigibility of realization, with the design of the different size that adapts to the peripheral LED display screen.
Above-described only is preferred implementation of the present utility model, and the utility model is not limited to above embodiment.Be appreciated that those skilled in the art under the prerequisite that does not break away from spirit of the present utility model and design, can make other improvement and variation.

Claims (5)

1. the GPIO module that can brush LED display based on DMA is characterized in that comprising following structure:
Control register module (1) links to each other with CPU module (10), is used for control store instruction and status data;
Fifo module (2) links to each other with data output control module (7) with dma module (11), is used for the buffering of data;
LED_ABCD control module (3) selects module (8) to link to each other with control register module (1), LED_STB control module (5), LED_CLKS control module (6) and IObank, is used for the sequential of the row selection signal of control LED display interface;
LED_OEN control module (4) selects module (8) to link to each other with control register module (1), LED_STB control module (5), LED_CLKS control module (6) and IObank, is used for the sequential of the enable signal of control LED display interface;
LED_STB control module (5), select module (8) to link to each other with control register module (1), LED_ABCD control module (3), LED_OEN control module (4), LED_CLKS control module (6) and IObank, be used for the sequential of the data latch signal of control LED display interface;
LED_CLKS control module (6), select module (8) to link to each other with control register module (1), LED_ABCD control module (3), LED_OEN control module (4), LED_STB control module (5) and IObank, be used for the sequential of each clock signal of control LED display interface;
Data output control module (7) selects module (8) to link to each other with control register module (1), fifo module (2) and IObank, is used for form and the bit wide of control output data;
IObank selects module (8), link to each other with control register module (1), LED_ABCD control module (3), LED_OEN control module (4), LED_STB control module (5), LED_CLKS control module (6), data output control module (7) and LED display module (12), be used for the control signal of LED display, clock signal and data are exported at different IO bank respectively.
2. the described GPIO module that can brush LED display based on DMA according to claim 1, it is characterized in that: described LED_ABCD control module (3) inside has the counting module of increasing progressively (13) and shift module (14), the LED_CLKS signal that LED_CLKS control module (6) is sent here is counted, produced row selection signal by increasing progressively count mode and shift mode respectively; What data configure first every row has, and automatically to the data counting, delegation counts when expiring by MUX (15) auto-changing row selection signal; The LED_STB signal controlling of being sent here by LED_STB control module (5) increases progressively the clear operation of counting module (13) and shift module (14); And reception is from the control of the control signal of control register module (1).
3. the described GPIO module that can brush LED display based on DMA according to claim 1, it is characterized in that: described LED_OEN control module (4) inside has counter (16), the LED_CLKS signal that LED_CLKS control module (6) is sent here is counted, by comparer (17) value of counter (16) and the value in the control register module (1) are compared the level state that decides LED_OEN; The clear operation of the LED_STB signal controlling counter (16) of being sent here by LED_STB control module (5); And reception is from the control of the control signal of control register module (1).
4. the described GPIO module that can brush LED display based on DMA according to claim 1, it is characterized in that: described LED_STB control module (5) inside has counter (18), the LED_CLKS signal that LED_CLKS control module (6) is sent here is counted, by comparer (19) value of counter (18) and the value in the control register module (1) are compared the level state that decides LED_STB; And reception is from the control of the control signal of control register module (1).
5. the described GPIO module that can brush LED display based on DMA according to claim 1, it is characterized in that: described LED_CLKS control module (6) inside has counter (20) and comparer (21), system clock is produced the LED_DATA_CLK signal by counter (20) and comparer (21), and by frequency divider (22) the LED_DATA_CLK signal frequency split is obtained the LED_CLKS signal; And reception is from the control of the control signal of control register module (1).
CN2012205191783U 2012-10-11 2012-10-11 GPIO module based on DMA and capable of updating LED display screen Withdrawn - After Issue CN202871257U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102902648A (en) * 2012-10-11 2013-01-30 东莞润风电子科技有限公司 Direct memory access (DMA)-based general purpose input output (GPIO) module capable of refreshing light-emitting diode (LED) display screen
CN112579495A (en) * 2020-12-25 2021-03-30 上海东软载波微电子有限公司 GPIO controller

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102902648A (en) * 2012-10-11 2013-01-30 东莞润风电子科技有限公司 Direct memory access (DMA)-based general purpose input output (GPIO) module capable of refreshing light-emitting diode (LED) display screen
CN102902648B (en) * 2012-10-11 2015-01-28 东莞润风电子科技有限公司 Direct memory access (DMA)-based general purpose input output (GPIO) module capable of refreshing light-emitting diode (LED) display screen
CN112579495A (en) * 2020-12-25 2021-03-30 上海东软载波微电子有限公司 GPIO controller
CN112579495B (en) * 2020-12-25 2024-01-30 上海东软载波微电子有限公司 GPIO controller

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Granted publication date: 20130410

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