CN112579495A

CN112579495A - GPIO controller

Info

Publication number: CN112579495A
Application number: CN202011574134.6A
Authority: CN
Inventors: 陈诚; 陈光胜
Original assignee: Shanghai Eastsoft Microelectronics Co ltd
Current assignee: Shanghai Eastsoft Microelectronics Co ltd
Priority date: 2020-12-25
Filing date: 2020-12-25
Publication date: 2021-03-30
Anticipated expiration: 2040-12-25
Also published as: CN112579495B

Abstract

A GPIO controller comprising: the FIFO module is suitable for being written by a CPU or a DMA, temporarily storing GPIO output data and outputting state information to the grouping unit; a DMA request unit; the grouping unit is suitable for reading the temporarily stored GPIO output data from the FIFO module after receiving the non-empty state information of the FIFO module, grouping the read data according to the configuration information, and sending the grouped GPIO output data to the output unit; a specific waveform generator; a control unit adapted to be written by the CPU for initialization settings and to provide configuration information to the grouping unit and the clock generator. The invention can write data into the FIFO module through the DMA, and the GPIO output data is placed in the FIFO module, namely the GPIO output waveform can be free from the intervention of the CPU, thereby greatly reducing the operation of the CPU for generating the waveform, reducing the using amount of a memory, reducing the bus access frequency, flexibly realizing the high-speed output of various waveforms, supporting various communication protocols and having less cost influence.

Description

GPIO controller

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a GPIO controller.

Background

Embedded systems, refer to devices used to control, monitor, or assist in the operation of machines and equipment. The embedded system is a complex of software and hardware, can also cover auxiliary devices such as electronic components, machinery and the like, integrates application software of the system with the hardware of the system, and has the characteristics of small software code, high automation, high response speed and the like.

In embedded system applications, an MCU (Micro Controller Unit, also called a "single chip microcomputer" or a "single chip microcomputer") is required to provide multiple interfaces for communication with other modules, including UART (Universal Asynchronous Receiver/Transmitter), SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit), GPIO (General-Purpose Input/Output Interface), etc.

The GPIO has the advantages of small package, low cost, low power consumption and the like, but can be only used for simple and low-speed level receiving and sending, and hardware does not support a specific communication protocol but controls the GPIO to send a specific waveform through a CPU.

In the prior art, the output function of GPIO in a microcontroller chip MCU is single, and the transmission speed of software control is limited. Some application scenes have higher requirements on the timing sequence, parallelism and speed of GPIO transmitting waveforms, and the GPIO analog operation realized by a CPU in the prior art has low efficiency and low speed.

A scheme capable of realizing GPIO high-efficiency output is needed.

Disclosure of Invention

The technical problem solved by the invention is as follows: how to effectively communicate with other modules through the GPIO interface by the MCU.

In order to solve the above technical problem, an embodiment of the present invention provides a GPIO controller, including: the device comprises an FIFO module, a DMA request unit, a grouping unit, a specific waveform generator and a control unit; wherein:

the FIFO module is suitable for being written by a CPU or a DMA, temporarily storing GPIO output data and outputting state information to the grouping unit;

a DMA request unit adapted to send data to the FIFO module to request a data transfer;

the grouping unit is suitable for reading the temporarily stored GPIO output data from the FIFO module after receiving the non-empty state information of the FIFO module, grouping the read data according to the configuration information, and sending the grouped GPIO output data to the output unit;

the specific waveform generator is suitable for calculating according to the set waveform related parameters and sending the calculated waveform vector to the grouping module;

a control unit adapted to be written by the CPU for initialization settings and to provide configuration information to the grouping unit and the clock generator.

Optionally, the method further includes: and the interface unit is suitable for serving as an interface between the GPIO controller and the system bus, the GPIO controller serves as a slave device of the system bus, and the master device of the system bus can set the control unit in the GPIO controller and write data into the FIFO module in the GPIO controller through the interface unit.

Optionally, the method further includes: and the clock generator is suitable for responding to the enabling of the control unit and outputting a specific transmitting clock TXCLK to the output unit according to the output frequency requirement given by the control unit.

Optionally, the method further includes: and the output unit is suitable for outputting the GPIO output data grouped by the grouping unit to IO according to the clock TXCLK output by the clock generator.

Optionally, the data bit width of the FIFO module is 8 bits, 16 bits, or 32 bits, and the data depth is 1 level, 2 levels, or 4 levels.

Optionally, the status information output by the FIFO module includes empty, non-empty and not full; the state information is not null and is suitable for the grouping unit to prompt the grouping unit that the data which can be grouped is available for sending; the status information is not full and is suitable for being sent to the DMA request unit to prompt the DMA request unit to newly transmit a group of data to the FIFO module.

Optionally, the state information is provided for the CPU to query in real time.

Optionally, the DMA request unit is adapted to send data to the FIFO module to request data transmission when the FIFO module is not full, until the FIFO module is full.

Optionally, the grouping unit may be configured to support a plurality of output modes, where the plurality of output modes include: a basic mode, a transposed mode, a complementary mode, and a repeated mode.

Optionally, the waveform-related parameters include an initial phase, a frequency, an amplitude, and an output bit number, and the specific waveform generator is a sine wave generator, and is adapted to calculate each vector value of the waveform vector according to the set initial phase, frequency, amplitude, and output bit number, and send the vector value to the grouping module.

Optionally, the initialization setting includes setting the number of IO to be output, the output frequency, and the enable control, and the CPU writes a configuration register in the control unit through a system bus and an interface unit of the GPIO controller to implement the initialization setting.

Optionally, the grouping the read data according to the configuration information includes: and grouping the read data according to the number of the IO to be output given by the control unit, wherein each IO corresponds to a group of bits.

Optionally, the data read by the grouping unit is grouped according to the number of IO to be output, and then output according to the clock TXCLK output by the clock generator, where each IO can set a rising edge or a falling edge of the TXCLK for output.

Optionally, the system bus is an AHB advanced high performance bus.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

a GPIO controller comprising: the FIFO module is suitable for being written by a CPU or a DMA, temporarily storing GPIO output data and outputting state information to the grouping unit; a DMA request unit adapted to send data to the FIFO module to request a data transfer; the grouping unit is suitable for reading the temporarily stored GPIO output data from the FIFO module after receiving the non-empty state information of the FIFO module, grouping the read data according to the configuration information, and sending the grouped GPIO output data to the output unit; the specific waveform generator is suitable for calculating according to the set waveform related parameters and sending the calculated waveform vector to the grouping module; the control unit is suitable for being written by the CPU to carry out initialization setting, and provides configuration information for the grouping unit and the clock generator, so that data can be written into the FIFO module through the DMA, GPIO output data are placed in the FIFO module, namely GPIO output waveforms can be controlled through the DMA in the whole process without CPU intervention, the operation of the CPU for generating the waveforms is greatly reduced, the use amount of a memory is reduced, the bus access frequency is reduced, high-speed output of various waveforms can be flexibly realized, various communication protocols are supported, and meanwhile, the cost influence is small.

Further, the grouping unit can be configured to support a plurality of output modes, including: the basic mode, the transposition mode, the complementary mode and the repetition mode can set the repeated output times of the data segment, and the data transmission times are saved.

Furthermore, the data read by the grouping unit are grouped according to the number of the IO to be output, and then are output according to the clock TXCLK output by the clock generator, each IO can set the rising edge or the falling edge of the TXCLK to output, the IO output waveform is smooth and continuous, the duty ratio is accurate, and the application is flexible.

Drawings

FIG. 1 is a schematic diagram of system integration according to an embodiment of the present invention;

FIG. 2 is a block diagram of a GPIO controller according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a FIFO module data packet according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of complementary waveform output and repetitive output according to an embodiment of the present invention;

FIG. 5 is a block diagram of a specific waveform generator in an embodiment of the present invention.

Detailed Description

As can be seen from the analysis of the background art, in the application of the embedded system, the MCU is required to provide multiple interfaces to communicate with other modules, where the GPIO has the advantages of small package, low cost, low power consumption, etc., but it can only be used for simple and low-speed level reception and transmission, and the hardware does not support a specific communication protocol, but controls the GPIO to transmit a specific waveform through the CPU.

Aiming at the defects in the prior art, the invention aims to realize the high-efficiency communication between the MCU and other modules through the GPIO interface in the application of the embedded system. Specifically, the present invention provides a GPIO controller, including: the FIFO module is suitable for being written by a CPU or a DMA, temporarily storing GPIO output data and outputting state information to the grouping unit; a DMA request unit adapted to send data to the FIFO module to request a data transfer; the grouping unit is suitable for reading the temporarily stored GPIO output data from the FIFO module after receiving the non-empty state information of the FIFO module, grouping the read data according to the configuration information, and sending the grouped GPIO output data to the output unit; the specific waveform generator is suitable for calculating according to the set waveform related parameters and sending the calculated waveform vector to the grouping module; the control unit is suitable for being written by the CPU to carry out initialization setting, and provides configuration information for the grouping unit and the clock generator, so that data can be written into the FIFO module through the DMA, GPIO output data are placed in the FIFO module, namely GPIO output waveforms can be controlled through the DMA in the whole process without CPU intervention, the operation of the CPU for generating the waveforms is greatly reduced, the use amount of a memory is reduced, the bus access frequency is reduced, high-speed output of various waveforms can be flexibly realized, various communication protocols are supported, and meanwhile, the cost influence is small.

In order that those skilled in the art will better understand and realize the present invention, the following detailed description is given by way of specific embodiments with reference to the accompanying drawings.

Example one

As described below, embodiments of the present invention provide a GPIO controller.

Regarding the application of the GPIO controller provided in this embodiment in a system, refer to a system integration diagram shown in fig. 1. The GPIO controller is connected with a system bus (in the figure, an AHB advanced high performance bus is taken as an example), the CPU and the DMA can access the GPIO controller and a memory (such as an SRAM) through the system bus, and the memory can store the waveform data to be output by IO.

In practical application, the program can store the waveform data in the memory in advance, the CPU or the DMA can read the data in the memory and write the data into the FIFO module of the GPIO controller, and the GPIO controller groups the data received by the FIFO module according to a specific format and transmits the grouped data to the IO by the dedicated transmission clock TXCLK.

Regarding the structure of the GPIO controller provided in this embodiment, referring to the block diagram of the GPIO controller structure shown in fig. 2, the GPIO controller includes: the device comprises an FIFO module, a DMA request unit, a grouping unit, a specific waveform generator and a control unit; the functions of the components are explained in detail below:

the GPIO controller comprises a FIFO module, which is suitable for being written by a CPU or a DMA (through a system bus interface), temporarily storing GPIO output data and outputting state information to the grouping unit;

in some embodiments, the data bit width of the FIFO module may be 8 bits, 16 bits or 32 bits, and the data depth may be 1 stage, 2 stages or 4 stages, and the data bit width and the data depth may be set according to the actual application requirement.

Regarding the status information output by the FIFO module to the grouping unit, in some embodiments, the status information output by the FIFO module includes empty, non-empty, and not full;

the state information is not null and is suitable for the grouping unit to prompt the grouping unit that the data which can be grouped is available for sending; the status information is not full and is suitable for being sent to the DMA request unit to prompt the DMA request unit to newly transmit a group of data to the FIFO module.

In some embodiments, the status information may be queried by the CPU in real time.

The GPIO controller comprises a DMA request unit, a data transmission unit and a data transmission unit, wherein the DMA request unit is suitable for sending data to the FIFO module to request one-time data transmission;

in some embodiments, the DMA request unit is further adapted to send data to the FIFO module to request a data transfer when the FIFO module is not full until the FIFO module is full.

The GPIO controller comprises a grouping unit, a first input/output (GPIO) output unit and a second input/output (GPIO) output unit, wherein the grouping unit is suitable for reading temporarily stored GPIO output data from an FIFO module after receiving non-empty state information of the FIFO module, grouping the read data according to configuration information and sending the grouped GPIO output data to the output unit;

in some embodiments, the data read by the grouping unit is grouped according to the number of IO to be output (wherein each GPIO corresponds to a group of bits; during the whole group of bit stream output, if the FIFO is still not empty, a new data is read and grouped to ensure the continuity of the IO output bit stream), and then according to the clock TXCLK output by the clock generator, each IO can set the TXCLK rising edge or falling edge for output.

The above description of the technical solution shows that: in this embodiment, the data read by the grouping unit is grouped according to the number of IO to be output, and then output according to the clock TXCLK output from the clock generator, each IO can set the rising edge or falling edge of the TXCLK for output, and the IO output has smooth and continuous waveform, accurate duty ratio, and flexible application.

In some embodiments, the grouping the read data according to the configuration information includes: and grouping the read data according to the number of the IO to be output given by the control unit, wherein each IO corresponds to a group of bits.

In some embodiments, the grouping unit is configurable to support a plurality of output modes, including: a basic mode, a transposed mode, a complementary mode, and a repeated mode.

With respect to the above-mentioned various output modes, in some embodiments, specifically:

basic mode: and 4 to-be-output packets GPIO are provided, the bit width of the FIFO data is 32 bits, the 32 bits of data are divided into 4 groups, the bit number k of each group is 8, wherein:

[7:0] corresponds to the control GPIO 0;

[15:8] corresponding to control GPIO 1;

[23:16] corresponding to control GPIO 2;

[31:24] corresponds to the control GPIO 3.

Transposition mode: and 4 to-be-output packets GPIO are provided, the bit width of the FIFO data is 32 bits, the 32 bits of data are divided into 4 groups, the number k of bits in each group is 8(i is 0-7), wherein:

[0+4 × i ] corresponds to the control GPIO 0;

[1+4 × i ] corresponds to the control GPIO 1;

[2+4 × i ] corresponds to the control GPIO 2;

[3+4 × i ] corresponds to the control GPIO 3.

Complementary mode: on the basis of the basic mode or the transposed mode, if an output IO is newly defined to be the complement of the IO defined in the above definition, the IO outputs the inverted waveform of the IO defined in the above.

Repeating the mode: the number of repetitions of a certain IO in an output data segment may be defined.

The above description of the technical solution shows that: in this embodiment, the grouping unit may be configured to support a plurality of output modes, where the plurality of output modes include: the basic mode, the transposition mode, the complementary mode and the repetition mode can set the repeated output times of the data segment, and the data transmission times are saved.

The GPIO controller comprises a specific waveform generator, is suitable for calculating according to the set waveform related parameters and sending the calculated waveform vector to the grouping module;

in some embodiments, the waveform-related parameters include an initial phase, a frequency, an amplitude, and a number of output bits, and the specific waveform generator is a sine wave generator adapted to calculate each vector value of the waveform vector according to the set initial phase, frequency, amplitude, and number of output bits, and send to the grouping module.

For example, the sine wave generator calculates each (set of) vector values according to the set initial phase, frequency, amplitude and number of output bits, and sends them to the grouping module (configured as a transposed mode in this case).

In other embodiments, the specific waveform generator may also be a triangle generator or other waveform generator, which is not limited in this respect.

The GPIO controller includes a control unit adapted to be written by the CPU (over the system bus) for initialization setting (initialization setting before enabling the GPIO output function) and to provide configuration information to the grouping unit and the clock generator.

Regarding the initialization setting, in some embodiments, the initialization setting includes setting the number of IO to be output, the output frequency, and the enable control, and the CPU writes the configuration register in the control unit through the system bus and the interface unit of the GPIO controller to implement the initialization setting.

In some embodiments, the system bus may be an AHB advanced high performance bus.

On this basis, the GPIO controller may further include the following optional components. In particular, the method comprises the following steps of,

in some embodiments, the GPIO controller may further include: and the interface unit is suitable for serving as an interface between the GPIO controller and the system bus, the GPIO controller serves as a slave device of the system bus, and the master device of the system bus can set the control unit in the GPIO controller and write data into the FIFO module in the GPIO controller through the interface unit.

In some embodiments, the GPIO controller may further comprise: and the clock generator is suitable for responding to the enabling of the control unit and outputting a specific transmitting clock TXCLK to the output unit according to the output frequency requirement given by the control unit.

In some embodiments, the GPIO controller may further include: and the output unit is suitable for outputting the GPIO output data grouped by the grouping unit to IO (the IO serves as the output end of the GPIO controller provided by the embodiment) according to the clock TXCLK output by the clock generator.

The above description of the technical solution shows that: in this embodiment, the GPIO controller includes: the FIFO module is suitable for being written by a CPU or a DMA, temporarily storing GPIO output data and outputting state information to the grouping unit; a DMA request unit adapted to send data to the FIFO module to request a data transfer; the grouping unit is suitable for reading the temporarily stored GPIO output data from the FIFO module after receiving the non-empty state information of the FIFO module, grouping the read data according to the configuration information, and sending the grouped GPIO output data to the output unit; the specific waveform generator is suitable for calculating according to the set waveform related parameters and sending the calculated waveform vector to the grouping module; the control unit is suitable for being written by the CPU to carry out initialization setting, and provides configuration information for the grouping unit and the clock generator, so that data can be written into the FIFO module through the DMA, GPIO output data are placed in the FIFO module, namely GPIO output waveforms can be controlled through the DMA in the whole process without CPU intervention, the operation of the CPU for generating the waveforms is greatly reduced, the use amount of a memory is reduced, the bus access frequency is reduced, high-speed output of various waveforms can be flexibly realized, various communication protocols are supported, and meanwhile, the cost influence is small.

On this basis, the working process/mode of the GPIO controller provided in this embodiment in practical application is further described as follows:

in contrast, in the prior art, after the GPIO in the MCU is configured to output, software can write data to a dedicated output register to control the output level of the IO, which results in low efficiency, low speed and CPU resource consumption in some applications.

By adopting the GPIO controller provided in this embodiment, as described above, data can be written into the FIFO module through the DMA, and GPIO output data is placed in the FIFO module, that is, GPIO output waveforms can be controlled by the DMA without intervention of the CPU (i.e., the GPIO output waveforms can be controlled by the DMA in the whole process), which greatly reduces the operation of the CPU for generating waveforms, reduces the memory usage, reduces the bus access frequency, can flexibly implement high-speed output of various waveforms, supports various communication protocols, and has little cost impact.

Specifically, the working process/mode of the GPIO controller provided in this embodiment in practical application is as follows (the structure of the GPIO controller is merely an example, and the present invention is not limited thereto):

(refer to fig. 1) the GPIO controller is placed on the high-speed bus of the SOC, such as the AHB advanced high performance bus in the AMBA.

(refer to fig. 2) the GPIO controller has a built-in FIFO module that may be 8-bit, 16-bit or 32-bit data wide and 1, 2 or 4 levels deep.

(refer to fig. 3) the data bit width n of the FIFO module may be divided into a plurality of groups according to the mode configuration (basic mode or transposed mode) and the number m of IO, if the number of IO to be output is 4, and the bit width of the FIFO module is 32 bits, the 32 bits of data are divided into 4 groups, the number k of bits in each group is 8, and if the mode is the basic mode, the corresponding relationship is as follows:

[7:0] corresponds to the control GPIO 0;

[15:8] corresponding to control GPIO 1;

[23:16] corresponding to control GPIO 2;

[31:24] corresponds to the control GPIO 3.

If the mode is the transpose mode, the corresponding relationship is as follows:

[0+4 × i ] corresponds to the control GPIO 0;

[1+4 × i ] corresponds to the control GPIO 1;

[2+4 × i ] corresponds to the control GPIO 2;

[3+4 × i ] corresponds to the control GPIO 3.

If the number of IO to be output cannot be evenly divided by the bit width of the FIFO data, for example, 7 GPIOs, the bit width of the FIFO data divided by the number of IO to be output is selected for each group of bit number k, that is, k is an integer of n/m, 32/7 is rounded to 4, and the basic mode correspondence relationship is as follows:

[3:0] corresponds to the control GPIO 0;

[7:4] corresponding control GPIO 1;

[11:8] corresponding to control GPIO 2;

[15:12] corresponding control GPIO 3;

[19:16] corresponding to the control GPIO 4;

[23:20] corresponding control GPIO 5;

[27:24] corresponds to the control GPIO 6.

The transposed pattern correspondence is as follows:

[0+7 × i ] corresponds to the control GPIO 0;

[1+7 × i ] corresponds to the control GPIO 1;

[2+7 × i ] corresponds to the control GPIO 2;

[3+7 × i ] corresponds to the control GPIO 3;

[4+7 × i ] corresponds to the control GPIO 4;

[5+7 × i ] corresponds to the control GPIO 5;

[6+7 × i ] corresponds to the control GPIO 6.

The GPIO controller supports a DMA interface control function, when the system starts the GPIO output function, a DMA transmission request can be generated when the FIFO module is not full, and the DMA responds to the request and transmits output waveform data preset on the SRAM to the FIFO module.

The output of the GPIO controller can be controlled by directly writing the FIFO module through the CPU, and the waveform data can also be transmitted through the assistance of DMA (the whole process can be controlled through the DMA).

The FIFO controller may transmit the DATA in the FIFO module to an output register dedicated to GPIO, where the number of times each DATA can be transmitted is k bits per group, and continuing with the above example, that is, 4 IO to be output, the bit width of the FIFO DATA is 32 bits, each 32-bit DATA is divided into 4 groups, each group outputs 8-bit DATA through 8 clocks, that is, GPIO [3:0], and the basic mode corresponds to the following output relationship:

the 1 st clock output { DATA [24], DATA [16], DATA [8], DATA [0] };

the 2 nd clock output { DATA [24+1], DATA [16+1], DATA [8+1], DATA [0+1] };

the 3 rd clock output { DATA [24+2], DATA [16+2], DATA [8+2], DATA [0+2] };

the 4 th clock output { DATA [24+3], DATA [16+3], DATA [8+3], DATA [0+3] };

the 5 th clock output { DATA [24+4], DATA [16+4], DATA [8+4], DATA [0+4] };

the 6 th clock output { DATA [24+5], DATA [16+5], DATA [8+5], DATA [0+5] };

the 7 th clock output { DATA [24+6], DATA [16+6], DATA [8+6], DATA [0+6] };

the 8 th clock output { DATA [24+7], DATA [16+7], DATA [8+7], DATA [0+7 }.

The output relationship of the transposition mode is as follows:

the 1 st clock output { DATA [3:0] };

the 2 nd clock output { DATA [7:4] };

the 3 rd clock output { DATA [11:8] };

the 4 th clock output { DATA [15:12] };

the 5 th clock output { DATA [19:16] };

the 6 th clock output { DATA [23:20] };

the 7 th clock output { DATA [27:24] };

the 8 th clock output { DATA [31:28 }.

On this basis, a complementary waveform (i.e., an inverted waveform) of the group output IO may be additionally designated as (several) IO outputs. When the IO to be output during configuration can be divided into a group IO and a complementary IO, where the group IO is output according to the above-mentioned manner, and the complementary IO outputs a complementary inverted waveform according to a designated group IO, for example, a designated GPIO5 outputs a complementary GPIO2, then the GPIO5 outputs the following (refer to fig. 4, in which the complementary waveform output is implemented by hardware, but the present invention is not limited thereto):

basic mode: -DATA [16], -DATA [17], -DATA.

Transposition mode: -DATA [2], -DATA [6],..,. DATA [30 ].

The number of times that each IO is to repeatedly output a data segment may be set as required, and continuing with the above example as an example, if the GPIO2 is set to repeatedly output 3 times, the following sequential output cases are sequentially output (continuing with reference to fig. 4, where the repeated output is implemented by hardware, but the present invention is not limited thereto):

basic mode: DATA [16], DATA [17],.

Transposition mode: DATA [2], DATA [6],. turn..

FIFO data is output to a special output register of the GPIO and controlled by a special transmission clock TXCLK, and the clock corresponds to the output speed of the GPIO; the frequency of the transmission clock TXCLK can be configured by the CPU through software, and is usually divided by the system clock, that is, a corresponding frequency dividing register is configured to divide the frequency to output. Each IO may be set to output on either a rising or falling edge of TXCLK.

Providing a specific waveform generator (refer to fig. 5, wherein the generation of the specific waveform is realized by hardware, but the present invention is not limited thereto), such as a sine wave generator (in another embodiment, it may also be a triangular wave generator), configuring the system with sine wave initial phase, frequency, amplitude and output bit number (the output bit number corresponds to the number of output IO), the sine wave generator providing each (group of) vector value calculated to the grouping module (configured as a transposed mode at this time), and the grouping module redistributing the IO to be output for output.

If the outputs are 10-bit precision vectors V0[9:0], V1[9:0], V2[9:0]. the corresponding 32-bit DATA combination is DATA [31:0] ═ {2' b00, V2[9:0], V1[9:0], V0[9:0] } (redundant high 2 bits are invalid and set to 0), the grouping module acquires DATA and then processes and sends the DATA.

Those skilled in the art will understand that, in the methods of the embodiments, all or part of the steps can be performed by hardware associated with program instructions, and the program can be stored in a computer-readable storage medium, which can include: ROM, RAM, magnetic or optical disks, and the like.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A GPIO controller comprising: the device comprises an FIFO module, a DMA request unit, a grouping unit, a specific waveform generator and a control unit; wherein:

2. The GPIO controller of claim 1, further comprising: and the interface unit is suitable for serving as an interface between the GPIO controller and the system bus, the GPIO controller serves as a slave device of the system bus, and the master device of the system bus can set the control unit in the GPIO controller and write data into the FIFO module in the GPIO controller through the interface unit.

3. The GPIO controller of claim 1, further comprising: and the clock generator is suitable for responding to the enabling of the control unit and outputting a specific transmitting clock TXCLK to the output unit according to the output frequency requirement given by the control unit.

4. The GPIO controller of claim 1, further comprising: and the output unit is suitable for outputting the GPIO output data grouped by the grouping unit to IO according to the clock TXCLK output by the clock generator.

5. The GPIO controller of claim 1, wherein the FIFO module has a data bit width of 8 bits, 16 bits, or 32 bits and a data depth of 1, 2, or 4 levels.

6. The GPIO controller of claim 1 wherein the status information output by the FIFO module includes empty, non-empty, and not full; the state information is not null and is suitable for the grouping unit to prompt the grouping unit that the data which can be grouped is available for sending; the status information is not full and is suitable for being sent to the DMA request unit to prompt the DMA request unit to newly transmit a group of data to the FIFO module.

7. The GPIO controller of claim 6, wherein the status information is for real-time querying by a CPU.

8. The GPIO controller of claim 1, wherein the DMA request unit is adapted to send data to the FIFO module to request one data transfer when the FIFO module is not full until the FIFO module is full.

9. The GPIO controller of claim 1, wherein the grouping unit is configurable to support a plurality of output modes, the plurality of output modes including: a basic mode, a transposed mode, a complementary mode, and a repeated mode.

10. The GPIO controller of claim 1, wherein the waveform-related parameters include an initial phase, a frequency, an amplitude, and a number of output bits, and wherein the particular waveform generator is a sine wave generator adapted to compute and send each vector value of a waveform vector to the grouping module based on the set initial phase, frequency, amplitude, and number of output bits.

11. The GPIO controller of claim 1, wherein the initialization setting includes setting a number of IO to be output, an output frequency, and an enable control, the CPU writing to a configuration register in the control unit through the system bus and an interface unit of the GPIO controller to implement the initialization setting.

12. The GPIO controller of claim 1, wherein the grouping of the read data according to the configuration information comprises: and grouping the read data according to the number of the IO to be output given by the control unit, wherein each IO corresponds to a group of bits.

13. The GPIO controller of claim 12, wherein the data read by the grouping unit is grouped according to the number of IO pairs to be output and then output according to a clock TXCLK output by a clock generator, each IO capable of setting a TXCLK rising edge or falling edge output.

14. The GPIO controller of claim 1, wherein the system bus is an AHB advanced high performance bus.