CN113986810B

CN113986810B - System and method for improving I2C communication performance

Info

Publication number: CN113986810B
Application number: CN202111609459.8A
Authority: CN
Inventors: 韩会莲; 张敏
Original assignee: Shenzhen Betterlife Electronic Science And Technology Co ltd
Current assignee: Shenzhen Betterlife Electronic Science And Technology Co ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-03-11
Anticipated expiration: 2041-12-27
Also published as: CN113986810A

Abstract

The invention discloses a system and a method for improving I2C communication performance, relates to the technical field of microelectronic communication control, and solves the technical problem that the filtering performance cannot be dynamically improved in I2C communication in the prior art. The invention comprises an I2C input/output port, a filtering module, a shift register, an access memory and an MCU which are connected in sequence, wherein the filtering clock period number of the filtering module is n, and the calculation formula is as follows:

. Wherein the content of the first and second substances,

in order to sample the clock frequency of the clock,

is the I2C clock frequency. The invention also provides a method for improving the communication performance of the I2C. The invention improves the anti-interference performance of I2C communication, reduces the interruption number of the MCU, improves the interruption processing efficiency and further improves the I2C communication performance.

Description

System and method for improving I2C communication performance

Technical Field

The invention relates to the technical field of microelectronic communication control, in particular to a system and a method for improving I2C communication performance.

Background

An I2C bus (Inter-Integrated Circuit), which is a simple, bi-directional, two-wire, synchronous serial bus designed by PHILIPS corporation in the 80 s. The I2C bus is a multi-directional control bus where multiple devices (slaves) can be simultaneously mounted on a bus controlled by a master, and each device connected to the bus communicates with the other devices via unique addresses. With the third industrial revolution, mankind has gradually entered a new era of digitization. In consumer electronics, telecommunications and industrial electronics, I2C is widely used in the field of microelectronic communication control. For example, analog-to-digital/digital-to-analog Converters (AD/DA Converters), LED controllers (LED controllers), DIP switches (DIP switches), etc. can be controlled by the I2C bus, which has the advantages of fewer pins, easy implementation, etc.

In a conventional I2C slave (I2C slave) system, the I2C data buffer is typically 1byte data. Therefore interrupts are frequently reported to the MCU and the data is processed 1byte at a time. Fig. 1 is a block diagram of a conventional I2C slave system implementation. The SDA is a bidirectional data line, and the system is divided into an input data line sdai (SDA input) and an output data line sdao (SDA output). scl is the I2C clock, which is the input to the system. After synchronization and debouncing processing of a narrow-band filter (spike filter), an internal signal is generated; I2C start flag signal I2c _ start, end flag signal I2c _ stop, I2C master read/write signal I2c _ read, and data line bit _ data, for a frame. When the I2C slave system receives data, the data is shifted by rx _ shifter, and the obtained data is temporarily stored in rx _ buffer. The MCU is informed to fetch data through rx _ flag. The data buffer in conventional systems is typically 1 byte. When the I2C slave system transmits data, the MCU is informed by tx _ flag that the data to be transmitted is ready. Data to be transmitted is temporarily stored in tx _ buffer. And then transmitted to sdao through the tx _ shifter shift register.

However, the main drawbacks of the above systems are: in the conventional I2C slave system, the value of the filtering clock period number (spike filter number) is fixed, that is, the filtering performance is fixed, and when the I2C frequency is changed, the filtering performance cannot be dynamically improved. In different integrated circuit (ic) systems, the number of filtering clock cycles needs to be adjusted, and the narrowband filter needs to be changed accordingly.

Disclosure of Invention

The invention aims to provide a system and a method for improving I2C communication performance, so as to solve the technical problem that the filtering performance cannot be dynamically improved when the I2C frequency is changed in the prior art. The technical effects that can be produced by the preferred technical scheme in the technical schemes provided by the invention are described in detail in the following.

In order to achieve the purpose, the invention provides the following technical scheme:

the invention provides a system for improving I2C communication performance, which comprises an I2C input/output port, a filtering module, a shift register, an access memory and an MCU (microprogrammed control unit) which are connected in sequence; the filtering clock period number of the filtering module is n, and the calculation formula is as follows:

n=f_clk/（2×f_scl）-1；

wherein f is_clkTo sample the clock frequency, f_sclIs the I2C clock frequency.

Preferably, the access memory is bidirectionally connected with the MCU.

Preferably, the access memory is a FIFO memory or a RAM memory.

Preferably, the I2C input/output ports include an SDA input port for transmitting input data, an SCL input port for transmitting an input clock signal, and an SDA output port for transmitting output data.

Preferably, the filtering module includes a first filtering module and a second filtering module; the first filtering module is unidirectionally connected with the SDA input port and is used for carrying out synchronization and de-jitter processing on data input by an SDA data line; the second filtering module is connected with the SCL input port in a one-way mode and used for carrying out synchronization and jitter removal processing on clock data input by an SCL clock line.

Preferably, the shift register comprises a receiving shift register and a sending shift register; the receiving shift register is unidirectionally connected with the first filtering module and the access memory; the sending shift register is unidirectionally connected with the second filtering module, the SDA output port and the access memory.

Preferably, the system for improving the communication performance of the I2C further comprises an I2C slave operation module connected with the MCU; the I2C slave operation module is used for sending a data writing or reading instruction to the MCU.

The invention also provides a method for improving the communication performance of the I2C, which comprises the system for improving the communication performance of the I2C, the I2C slave operation module connected with the MCU, and the following steps of writing data into the access memory;

s10, the I2C slave operation module initiates data transmission;

s11, the filtering module respectively carries out filtering processing on input data of an input port of an I2C input/output port and transmits the input data subjected to filtering processing to the shift register;

s12, the shift register receives the input data after filtering processing and transfers the input data to the access memory by bytes;

s13, whether the byte number of the access memory reaches the maximum limit; if yes, go to step S14; otherwise, go to step S16;

s14, the access memory receives the interrupt information and reports the MCU;

s15, the MCU receives the interrupt information, extracts the written input data from the access memory in batch, and clears the interrupt;

s16, receiving and writing the input data by the access memory according to bytes; after the writing is finished, the MCU extracts the written input data from the access memory in batch; returning to step S10, the next data write is executed.

Further, the method for improving the I2C communication performance further comprises the following steps of reading data from the MCU;

s20, the I2C slave operation module reports data transmission interruption to the MCU;

s21, the MCU receives the interrupt information, writes the output data into the access memory, and clears the sending interrupt after the writing is finished;

s22, the access memory sends the written output data to the shift register and continues to execute written data;

s23, the shift register sends the received output data to the output port of the I2C input/output port in bit.

The implementation of one of the technical schemes of the invention has the following advantages or beneficial effects:

the value of the filtering clock period number of the filtering module is calculated in real time according to the sampling clock frequency and the I2C frequency, and the value can be flexibly and dynamically configured through the MCU, so that the filtering performance is dynamically improved; meanwhile, an access memory is additionally arranged between the shift register and the MCU, so that the interruption number of the MCU is reduced, and the processing number of one-time interruption data is increased. The invention improves the anti-interference performance of I2C communication, reduces the interruption number of the MCU, improves the interruption processing efficiency and further improves the I2C communication performance.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic diagram of a conventional I2C slave system according to the present invention;

FIG. 2 is a schematic diagram of a system for improving I2C communication performance according to the present invention;

FIG. 3 is a schematic diagram illustrating the derivation of the optimal number of filtering clock cycles for a system for improving I2C communication performance;

FIG. 4 is a schematic diagram of the filtering module of the system for improving the performance of I2C communication according to the present invention;

FIG. 5 is a flow chart of the writing of input data for a method of improving I2C communication performance in accordance with the present invention;

FIG. 6 is a flow chart of the reading of output data for a method of improving I2C communication performance in accordance with the present invention;

in the figure: 1. I2C input/output port; 10. an SDA input port; 11. an SCL input port; 12. an SDA output port; 2. a filtering module; 20. a first filtering module; 21. a second filtering module; 3. a shift register; 30. receiving a shift register; 31. a transmission shift register; 4. accessing a memory; 5. and (6) an MCU.

Detailed Description

In order that the objects, aspects and advantages of the present invention will become more apparent, various exemplary embodiments will be described below with reference to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various exemplary embodiments in which the invention may be practiced. The same numbers in different drawings identify the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. It is to be understood that they are merely examples of processes, methods, apparatus, etc. consistent with certain aspects of the present disclosure as detailed in the appended claims, and that other embodiments may be used or structural and functional modifications may be made to the embodiments set forth herein without departing from the scope and spirit of the present disclosure.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," and the like are used in the orientations and positional relationships illustrated in the accompanying drawings for the purpose of facilitating the description of the present invention and simplifying the description, and do not indicate or imply that the elements so referred to must have a particular orientation, be constructed in a particular orientation, and be operated. The terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "plurality" means two or more. The terms "coupled" and "connected" are to be construed broadly and may include, for example, a fixed connection, a removable connection, a unitary connection, a mechanical connection, an electrical connection, a communicative connection, a direct connection, an indirect connection via intermediate media, and may include, but are not limited to, a connection between two elements or an interactive relationship between two elements. The term "and/or" includes any and all combinations of one or more of the associated listed items. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In order to explain the technical solution of the present invention, the following description is made by way of specific examples, which only show the relevant portions of the embodiments of the present invention.

The first embodiment is as follows:

as shown in fig. 2, the present invention provides a system for improving I2C communication performance, which includes an I2C I/o port 1, a filtering module 2, a shift register 3, an access memory 4, and an MCU 5, which are connected in sequence. Specifically, the filtering clock period number of the filtering module 2 is n, and the calculation formula is as follows:

n=f_clk/（2×f_scl）-1 （1）。

wherein f is_clkTo sample the clock frequency, f_sclIs the I2C clock frequency.

It should be noted that the I2C bus of the present embodiment is composed of a data line SDA and a clock line SCL, and the I2C bus is connected to an ic (integrated circuit) pin through a PCB trace. In the conventional I2C slave system, the value of the filtering clock period number is fixed, i.e. the filtering performance is fixed, and the filtering performance cannot be dynamically improved when the I2C frequency is changed. Therefore, the invention provides a method for dynamically adjusting the anti-interference performance of an I2C slave system and provides a calculation formula, namely formula (1). The value n of the number of filtering clock cycles of the filtering module 2 is calculated in real time according to the sampling clock frequency and the I2C frequency, and can be flexibly and dynamically configured by the MCU 5.

Preferably, to save resources of the system, the value range of n is: n is more than or equal to 4 and less than or equal to 8. Specifically, an IC typically has only one fixed frequency clock (hereinafter referred to as the sampling clock frequency) for synchronizing the I2C signal. Since the clock frequencies used by different ICs to process I2C may vary, the value of the number of filtering clock cycles of filtering module 2 needs to be dynamically adjusted.

As shown in fig. 3, the present embodiment further describes the above calculation formula and the determination of the preferred range of the filtering clock period number by taking the simplest algorithm of beat filtering the signal as an example. Generally, other effective filtering algorithms are adopted, the larger the filtering clock period value is, the better the filtering effect is, the stronger the anti-interference performance is, and the larger the hardware resource consumption is. The frequency of the I2C is fixed, and as the sampling clock frequency decreases, the filtering clock period value is smaller, so that the optimal filtering clock period number n needs to be determined by formula (1) in combination with the hardware resource condition. Specifically, I2C is fixed in frequency, with sampling clock periods clk0, clk1, clk2, clk3, clk4, respectively. clk0, clk1 are co-frequent, clk2, clk3 are co-frequent. Where clk0/clk1 frequency is greater than clk2/clk3 frequency and clk2/clk3 frequency is greater than clk4 frequency. The sampling clock and I2C are asynchronous signals. As shown in (1) and (2) of fig. 3, within a half scl clock period, there are 6 sampling clock periods. It usually takes 4 clock cycles to assert the I2C communication start end flag. It is certain that the filter clock period is 4 at this time. As shown in (3) and (4) of fig. 3, the sampling frequency is lowered, and there are 5 filtering clock cycles within a half scl clock cycle. A filter clock period of 4 would suffice. As shown in (5) of fig. 3, the sampling frequency is lowered, and there are 4 filtering clock cycles within a half scl clock cycle, in which case a scl signal of 4 clock cycles cannot be acquired. In a word, within a half scl period, subtracting 1 from the number of sampling periods to obtain the number of filtering clock periods, and in order to save resources, the interval of the optimal filtering clock period number (the filtering clock period is adjusted to be an integer) is as follows: n ∈ [4, 8], the specific calculation is shown in Table 1.

TABLE 1 dynamic adjustment table for filtering clock period number calculation and optimal value

NO	I2C clock frequency (KHz)	Sampling clock frequency (MHz)	Number of filtering clock cycles	Filtering clock period integer
					1	100	36	179	8
2	100	2	9	8
					3	100	1.8	8	8
4	100	1.7	7.5	7
					5	100	1.48	6.4	6
6	100	1.3	5.5	5
					7	100	1	4	4
8	200	36	89	8
					9	200	2.88	6.2	6
10	200	2.32	4.8	4

Another problem that the present invention also solves is that: in the conventional I2C slave system, the depth of a data buffer between a hardware data receiving module and the MCU 5 is generally 1byte, which is frequent in interruption, limited in the number of data processing operations per interruption, and low in efficiency. Therefore, the access memory 4 is additionally arranged between the hardware data receiving module and the MCU 5, so that the interruption number of the MCU 5 is reduced, and the one-time interruption data processing number is increased. And the performance of I2C communication is greatly improved. Of course, the MCU 5 may also be configured for other modules, such as SPI.

Further, the access memory 4 is a FIFO memory or a RAM memory, preferably a FIFO memory, and the access memory 4 is bidirectionally connected to the MCU 5. A FIFO memory is added in both the receiving direction and the transmitting direction of the system, and the FIFO memory depth is set to be 0-1024 bytes so as to be configurable. The depth of the FIFO memory can be adjusted according to different application scene requirements. Since I2C is half-duplex, only data can be received or transmitted at the same time, only one FIFO memory needs to be added.

Further, the I2C input-output port 1 includes an SDA input port 10 for transferring input data, an SCL input port 11 for transferring an input clock signal, and an SDA output port 12 for transferring output data. The filtering module 2 comprises a first filtering module 20 and a second filtering module 21, wherein the first filtering module 20 is unidirectionally connected with the SDA input port 10 and is used for performing synchronization and de-jitter processing on data input by an SDA data line; the second filtering module 21 is unidirectionally connected to the SCL input port 11, and is configured to perform synchronization and debounce processing on the clock data input by the SDA clock line. The shift register 3 includes a receiving shift register 30 and a sending shift register 31, the receiving shift register 30 is unidirectionally connected with the first filtering module 20 and the access memory 4, and the sending shift register 31 is unidirectionally connected with the second filtering module 21, the SDA output port 12 and the access memory 4.

The system for improving I2C communication performance of this embodiment further includes an I2C slave operation module (not illustrated in the figure) connected to the MCU 5, and the I2C slave operation module (for example, a control module in the I2C slave system) is configured to send a write or read data command to the MCU 5.

As shown in fig. 4, it should be further described that the I2C bus is interfered to generate glitches, and the system clock of the IC and the SCL/SDA belong to asynchronous signals, first, the IC needs to perform a synchronous circuit process on the SCL/SDA, and in this process, the filtering module 2 needs to perform a synchronization and de-jitter process to perform the next data processing. In the present embodiment, the filtering module 2 is a narrow-band filter (spike filter). The simplest implementation is to perform 5-beat filtering processing on the signal, that is, the number of filtering clock cycles of the narrow-band filter is 5. There is a glitch on the scl clock line as shown that is less than the sampling clock period, which is filtered after spike filter processing.

Example two:

as shown in fig. 5-6, the present invention further provides a method for improving I2C communication performance, including the steps of the system for improving I2C communication performance described in the first embodiment, the I2C slave operation module connected to the MCU 5, and writing data to the access memory 4 as follows;

s10, I2C initiates data transmission from the slave operation module. Before this step is performed, the MCU 5 further needs to calculate the number of filtering clock cycles of the filtering module 2 according to the sampling clock frequency and the I2C clock frequency mentioned above and the formula (1), and finally dynamically adjust the number of filtering clock cycles according to table 1. Specifically, if the calculated filtering clock period number is more than or equal to 8, the filtering clock period number is adjusted to 8; if the value is less than 8 and greater than or equal to 7, the value is adjusted to 7; if the value is less than 7 and greater than or equal to 6, the value is adjusted to 6; if the content is less than 6 and greater than or equal to 5, the content is adjusted to 5; if the average molecular weight is less than 5 and not less than 4, the value is adjusted to 4. In general, the condition that the number of filtering clock cycles is less than 4 is not used for judging to obtain an i2c _ start/i2c _ stop signal, so the condition is not considered;

s11 and the filtering module 2 respectively perform filtering processing on the input data of the input port of the I2C I/o port 1, and transmit the filtered input data to the shift register 3. Specifically, the first filtering module 20 (narrow-band filter) performs synchronization and debouncing processing on the data input from the SDA input port 10, and transmits the data to the receiving shift register 30 after the synchronization and debouncing processing is completed; the second filtering module 21 (narrow-band filter) performs synchronization and debounce processing on the clock data input by the SCL input port 11, and transmits the data to the transmission shift register 31 after the synchronization and debounce processing is completed;

s12, the shift register 3 receives the input data after the filtering process, and transfers the input data to the access memory 4 by byte;

s13, whether the byte number of the access memory 4 reaches the maximum limit; if yes, go to step S14; otherwise, step S16 is executed. Further, when the number of bytes stored in the FIFO memory reaches 2/3 or 3/4 of the total number of bytes that can be stored, the byte value of the access memory 4 reaches the maximum limit;

s14, the access memory 4 receives the interrupt signal and reports the interrupt signal to the MCU 5;

s15, the MCU 5 receives the interrupt information, extracts the written input data from the access memory 4 in batch, and clears the interrupt. The MCU 5 receives interrupt information and comprises two aspects, namely, reading data from the FIFO memory and clearing the interrupt;

s16, receiving and writing the input data by byte in the access memory 4; after the writing is finished, the MCU 5 extracts the written input data from the access memory 4 in batch; returning to step S10, the next data write is executed. After the access memory 4 is completely written, the data stored in the access memory 4 needs to be completely extracted from the access memory 4 in batches by the MCU 5.

The method for improving the communication performance of the I2C in the embodiment further comprises the following steps of reading data from the MCU 5;

s20, I2C slave operation module reports data transmission interruption to MCU 5;

s21, the MCU 5 receives the transmission interrupt information, writes the output data to the access memory 4, and clears the transmission interrupt.

S22, the access memory 4 sends the written output data to the shift register 3, and continues to execute the written data. Specifically, the FIFO memory transmits the written output data to the transmission shift register 31 of the shift register 3, and after the transmission is completed, the FIFO memory continues to execute the suspended data writing step, receives the input data from the reception shift register 30, and writes the corresponding data;

s23, shift register 3 sends the received output data to the output port of I2C I/o port 1 in bits. Specifically, the transmission shift register 31 of the shift register 3 transmits the received output data to the SDA output port 12 of the I2C input-output port 1 in bits.

In summary, in this embodiment, the value of the filtering clock cycle number of the filtering module is calculated in real time according to the sampling clock frequency and the I2C frequency, and the value can be flexibly and dynamically configured by the MCU, so as to dynamically improve the filtering performance; meanwhile, an access memory is additionally arranged between the shift register and the MCU, so that the interruption number of the MCU is reduced, and the processing number of one-time interruption data is increased. The system and the distribution thereof improve the anti-interference performance of I2C communication, reduce the interruption number of the MCU, improve the interruption processing efficiency and further improve the I2C communication performance.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A system for improving I2C communication performance is characterized by comprising an I2C input/output port (1), a filtering module (2), a shift register (3), an access memory (4) and an MCU (5) which are connected in sequence;

the filtering clock period number of the filtering module (2) is n, and the calculation formula is as follows:

n=f_clk/（2×f_scl）-1；

wherein f is_clkTo sample the clock frequency, f_sclIs the I2C clock frequency.

2. The system for improving I2C communication performance of claim 1, wherein the access memory is bidirectionally coupled to the MCU.

3. The system for improving I2C communication performance of claim 1, wherein the access memory (4) is a FIFO memory or a RAM memory.

4. The system for improving I2C communication performance according to claim 1, wherein the I2C input-output port (1) includes an SDA input port (10) for transmitting input data, an SCL input port (11) for transmitting an input clock signal, and an SDA output port (12) for transmitting output data.

5. The system for improving I2C communication performance according to claim 4, wherein the filtering module (2) comprises a first filtering module (20), a second filtering module (21);

the first filtering module (20) is unidirectionally connected with the SDA input port (10) and is used for carrying out synchronization and de-jitter processing on data input by an SDA data line;

the second filtering module (21) is unidirectionally connected with the SCL input port (11) and is used for carrying out synchronization and jitter removal processing on clock data input by an SCL clock line.

6. The system for improving I2C communication performance according to claim 5, wherein the shift register (3) comprises a receiving shift register (30), a transmitting shift register (31);

the receiving shift register (30) is unidirectionally connected with the first filtering module (20) and the access memory (4);

the sending shift register (31) is unidirectionally connected with the second filtering module (21), the SDA output port (12) and the access memory (4).

7. The system for improving I2C communication performance of claim 1, further comprising an I2C slave operation module connected with the MCU (5);

the I2C slave operation module is used for sending a data writing or reading instruction to the MCU (5).

8. A method for improving I2C communication performance, comprising the system for improving I2C communication performance of any claim 1-7, an I2C slave operation module connected to the MCU (5), and the step of writing data to the access memory (4) as follows;

s10, the I2C slave operation module initiates data transmission;

s11, the filtering module (2) respectively carries out filtering processing on input data of an input port of an I2C input/output port (1), and transmits the input data subjected to filtering processing to the shift register (3);

s12, the shift register (3) receives the input data processed by filtering and transmits the input data to the access memory (4) in bytes;

s13, whether the byte number of the access memory (4) reaches the maximum limit; if yes, go to step S14; otherwise, go to step S16;

s14, the access memory (4) receives the interrupt information and reports the interrupt information to the MCU (5);

s15, the MCU (5) receives the interrupt information, extracts the written input data from the access memory (4) in batch, and clears the interrupt;

s16, receiving and writing the input data by bytes by the access memory (4); after the writing is finished, the MCU (5) extracts the written input data from the access memory (4) in batch; returning to step S10, the next data write is executed.

9. The method for improving I2C communication performance according to claim 8, further comprising the steps of reading data from the MCU (5);

s20, the I2C slave operation module reports data transmission interruption to the MCU (5);

s21, the MCU (5) writes output data into the access memory (4) after receiving the interrupt information, and clears the sending interrupt after the writing is finished;

s22, the access memory (4) sends the written output data to the shift register (3) and continues to execute the written data;

s23, the shift register (3) sends the received output data to the output port of the I2C input/output port (1) in bits.