CN212647461U

CN212647461U - Synchronous or asynchronous serial communication control circuit based on PCI bus

Info

Publication number: CN212647461U
Application number: CN202021376858.5U
Authority: CN
Inventors: 高金超; 霍兴华
Original assignee: Tianjin Qisuo Precision Electromechanical Technology Co ltd
Current assignee: Tianjin Qisuo Precision Electromechanical Technology Co ltd
Priority date: 2020-07-14
Filing date: 2020-07-14
Publication date: 2021-03-02
Anticipated expiration: 2030-07-14

Abstract

The utility model relates to a synchronous or asynchronous serial communication control circuit based on PCI bus, through configuration FPGA internal register, divide internal into PCI bus IP nuclear, synchronous HDLC controller and asynchronous UART controller, use the PCI bus to link to each other PCI bus IP nuclear and CPCI simultaneously, use synchronous HDLC controller of external interface connection and CPCI, use asynchronous UART controller of external interface connection and CPCI, it can improve the integrated level of system to connect the PCI bus through PCI bus IP nuclear, and use PCI interface chip in saving the traditional approach, realize synchronous HDLC agreement and general asynchronous serial port agreement through FPGA is inside simultaneously, configuration internal register realizes synchronous or asynchronous serial communication function, and use serial control chip in saving the traditional approach. The utility model discloses whole functions are realized at FPGA inside to all communication interfaces all are the IP core, and the FIFO degree of depth can dispose in a flexible way.

Description

Synchronous or asynchronous serial communication control circuit based on PCI bus

Technical Field

The utility model belongs to equipment communication field, especially a synchronous or asynchronous serial communication control circuit based on PCI bus.

Background

Compact Peripheral Component Interconnect (CPCI), also called Compact PCI in chinese, is a bus interface standard proposed by the international association of Industrial Computer manufacturers (PCI Industrial Computer manufacturers' groups, PICMG for short) in 1994. Is a high performance industrial bus standardized by the PCI electrical specification. The CPU and peripherals of the CPCI are the same as the standard PCI, and the CPCI system uses the same chips, firewalls and related software as the traditional PCI system.

PCI is a local bus introduced by Intel corporation in 1991. Structurally, the PCI is a primary bus inserted between the CPU and the original system bus, and specifically, a bridge circuit manages this layer and implements an interface between the upper and lower layers to coordinate data transfer. The manager provides signal buffering to support 10 kinds of peripheral equipment and maintain high performance in high clock frequency, and provides connection interface for display card, sound card, network card, MODEM and other equipment with work frequency of 33MHz/66 MHz.

PCI is an abbreviation for Peripheral Component Interconnect (PCI), which is the most widely used interface in personal computers today, and almost all motherboard products have such slots. PCI slots are also the types of the main board with the most number of slots, on the current popular desktop main board, the main board of an ATX structure is generally provided with 5-6 PCI slots, and a smaller MATX main board is also provided with 2-3 PCI slots, so that the application universality is seen.

A PCI bus is a local bus that is not tied to a particular processor. The manager provides signal buffering to enable it to support 10 peripherals and to maintain high performance at high clock frequencies. The PCI bus also supports bus mastering, which allows smart devices to take bus control when needed to speed up data transfers.

The traditional synchronous or asynchronous serial communication method based on the PCI Bus is realized by adopting a PCI bridge chip, an FPGA chip, a synchronous serial port control chip and a synchronous or asynchronous serial port control chip, wherein the PCI bridge chip realizes the conversion from the PCI Bus to a Local Bus, and the FPGA chip realizes the analysis of the PCI protocol and controls the synchronous or asynchronous serial port control chip, so that the whole realization method is complex, the cost is high, and the flexibility is poor.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art's not enough, provide a synchronous or asynchronous serial communication control circuit based on PCI bus, solve the problem that the circuit is complicated, with high costs and the flexibility is poor that current control circuit exists.

The utility model provides a its technical problem take following technical scheme to realize:

a synchronous or asynchronous serial communication control circuit based on PCI bus includes: the device comprises a PCI bus IP core, a synchronous HDLC controller and an asynchronous UART controller, wherein the PCI bus IP core is connected with the CPCI through a PCI bus, the PCI bus IP core is respectively connected with the synchronous HDLC controller and the asynchronous UART controller, the synchronous HDLC controller is connected with the CPCI through an RS422/RS232 interface, and the asynchronous UART controller is connected with the CPCI through an RS422 interface.

And the PCI bus IP core comprises a parameter configuration register, a PCI address register, a PCI target register, a PCI data register, a parity check generator, a local address register, a local target register and a local data register, wherein the PCI address register and the PCI data register are connected with the CPCI through a PCI data bus and a PCI address bus, the PCI target register is controlled by a PCI control signal, the local address register is connected with the local bus through the local address bus, the local data register is connected with the local bus through the local data bus, and the local target register is controlled by the local control signal.

And the synchronous HDLC controller comprises a transmitter, a controller and a receiver, and the controller, the transmitter and the receiver are connected in sequence.

And the asynchronous UART controller comprises a transmitter, a baud rate generator and a receiver, and the transmitter, the baud rate generator and the receiver are connected in sequence.

And the PCI bus IP core, the synchronous HDLC controller and the asynchronous UART controller are realized through the FPGA.

The utility model has the advantages that: the utility model discloses a dispose the inside register of FPGA, divide inside into PCI bus IP nuclear, synchronous HDLC controller and asynchronous UART controller, use the PCI bus to link to each other PCI bus IP nuclear with CPCI simultaneously, use synchronous HDLC controller of external interface connection and CPCI, use asynchronous UART controller of external interface connection and CPCI, it can improve the integrated level of system to connect the PCI bus through PCI bus IP nuclear, and use PCI interface chip in saving the conventional method, simultaneously through inside synchronous HDLC agreement and the asynchronous serial port agreement of realizing of FPGA, dispose the inside register and realize synchronous or asynchronous serial communication function, and save and use serial control chip in the conventional method, and all communication interfaces all are the IP nuclear, the FIFO degree of depth can be disposed in a flexible way.

Drawings

Fig. 1 is a circuit block diagram of the present invention;

FIG. 2 is a circuit diagram of the PCI bus IP core of the present invention;

FIG. 3 is a block diagram of a synchronous HDLC controller interface of the present invention;

fig. 4 is a transmission flow chart of the present invention.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

A synchronous or asynchronous serial communication control circuit based on a PCI bus is shown in figure 1 and comprises a PCI bus IP core, a synchronous HDLC controller and an asynchronous UART controller, wherein the PCI bus IP core is connected with a CPCI pin J1 and a pin J2 through the PCI bus and receives a PCI bus command, the PCI bus IP core is connected with the synchronous HDLC controller and sends or receives HDLC frames, the PCI bus IP core is connected with the asynchronous UART controller and sends or receives serial data, the synchronous HDLC controller is connected with the CPCI through an RS422/RS232 interface, and the asynchronous UART controller is connected with the CPCI through an RS422 interface.

The PCI bus IP core, the synchronous HDLC controller and the asynchronous UART controller are configured through the FPGA, and the external serial port transceiver completes the functions of data receiving and transmitting, level conversion, electrostatic protection and photoelectric isolation.

As shown in FIG. 2, the PCI bus IP core includes a parameter configuration register, a PCI address register, a PCI target register, a PCI data register, a parity and its generator, a local address register, a local target register, and a local data register. The PCI address register and the PCI data register are connected with the CPCI through a PCI data bus and a PCI address bus, the PCI target register is controlled by a PCI control signal, the local address register is connected with the local bus through a local address bus, the local data register is connected with the local bus through the local data bus, and the local target register is controlled by the local control signal.

The PCI bus IP core obtains the transmission command and the address of read-write data from the CPCI bus side, then makes a reaction to the operation command, transmits the reaction to the local logic, and maps the data address transmitted by the CPCI bus into an address which can be identified by the local logic. When the local side bus is ready, the PCI bus IP core receives a response signal made by the local logic, and executes corresponding time sequence according to different read-write commands in a master-slave mode.

As shown in fig. 3, the synchronized HDLC controller includes a transmitter, a controller, and a receiver. The controller is divided into control, data buffer, zero insertion, zero deletion and zone bit modules according to specific function module division. The HDLC frame receiving and transmitting functions of the transmitter and the receiver are controlled by configuring each control signal of the master control module through configuration of the control signal and the register during connection of each module.

The asynchronous UART controller includes a transmitter, a baud rate generator, and a receiver. The transmitter converts the parallel data to be transmitted into a data frame in accordance with an asynchronous serial communication protocol for serial output; the receiver receives the serial signal and converts the data in the frame into a parallel format; the baud rate generator generates a local clock signal much higher than the baud rate to sample the input signal to ensure synchronization of the receiver and transmitter.

As shown in fig. 4, the transmission flow diagram is shown, where the PCI bus IP core acts as a slave device, triggering the slave mode control logic to perform a slave mode transmission. The internal register configuration is completely compatible with a commercial chip UART controller, the multi-channel data transmission configuration is completed, meanwhile, the sending and receiving data are effectively cached, and the communication with an upper computer is realized in an interrupt mode. The PCI bus logic adopts a 33MHz bus for communication, and the communication baud rate of the synchronous HDLC controller and the asynchronous UART controller can be configured and is up to 512 Kbps; the problem of cross-clock domain communication between PCI bus data and a synchronous HDLC controller and an asynchronous UART controller is solved by adopting 12 groups of 256-by-8-bit deep FIFOs to perform data caching on each channel.

It should be emphasized that the embodiments described herein are illustrative and not restrictive, and thus the present invention includes but is not limited to the embodiments described in the detailed description, as well as other embodiments derived from the technical solutions of the present invention by those skilled in the art, which also belong to the scope of the present invention.

Claims

1. A synchronous or asynchronous serial communication control circuit based on PCI bus is characterized by comprising: the device comprises a PCI bus IP core, a synchronous HDLC controller and an asynchronous UART controller, wherein the PCI bus IP core is connected with the CPCI through a PCI bus, the PCI bus IP core is respectively connected with the synchronous HDLC controller and the asynchronous UART controller, the synchronous HDLC controller is connected with the CPCI through an RS422/RS232 interface, and the asynchronous UART controller is connected with the CPCI through an RS422 interface.

2. The synchronous or asynchronous serial communication control circuit based on PCI bus as claimed in claim 1, wherein: the PCI bus IP core comprises a parameter configuration register, a PCI address register, a PCI target register, a PCI data register, a parity check generator, a local address register, a local target register and a local data register, wherein the PCI address register, the PCI data register and the CPCI are connected through a PCI data bus and a PCI address bus, the PCI target register is controlled by a PCI control signal, the local address register is connected with the local bus through the local address bus, the local data register is connected with the local bus through the local data bus, and the local target register is controlled by the local control signal.

3. The synchronous or asynchronous serial communication control circuit based on PCI bus as claimed in claim 1, wherein: the synchronous HDLC controller comprises a transmitter, a controller and a receiver, wherein the controller, the transmitter and the receiver are connected in sequence.

4. The synchronous or asynchronous serial communication control circuit based on PCI bus as claimed in claim 1, wherein: the asynchronous UART controller comprises a transmitter, a baud rate generator and a receiver, wherein the transmitter, the baud rate generator and the receiver are connected in sequence.

5. The synchronous or asynchronous serial communication control circuit based on PCI bus as claimed in claim 1, wherein: the PCI bus IP core, the synchronous HDLC controller and the asynchronous UART controller are realized through an FPGA.