CN114143296B - HDLC universal IP soft core - Google Patents
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- 238000012544 monitoring process Methods 0.000 claims abstract description 24
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 238000013461 design Methods 0.000 claims abstract description 15
- 238000004891 communication Methods 0.000 claims abstract description 7
- 238000009432 framing Methods 0.000 claims description 11
- 238000013024 troubleshooting Methods 0.000 claims description 8
- 230000006870 function Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- 238000004458 analytical method Methods 0.000 claims description 3
- 238000003032 molecular docking Methods 0.000 claims description 3
- 238000012800 visualization Methods 0.000 claims description 3
- 230000003068 static effect Effects 0.000 abstract description 10
- 230000001360 synchronised effect Effects 0.000 abstract description 5
- 238000012546 transfer Methods 0.000 abstract description 3
- 230000000007 visual effect Effects 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/26—Special purpose or proprietary protocols or architectures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/03—Protocol definition or specification
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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Abstract
The invention relates to an HDLC universal IP soft core, belonging to the embedded field. The IP soft core cooperates with the processor to improve the gating clock with larger clock jitter and offset into clock enabling, so that the dependence of the IP soft core on global clock resources is reduced, and the problem of time sequence instability caused by the gating clock is also reduced; the IP soft core can configure a use mode and a monitoring mode through static transfer parameters, and the requirements of functional diversity and resource rationality are considered; the IP soft core reserved logic layer interface supports a dynamic configuration function of the processor software; the processor software can configure baud rate, interrupt enabling mode, synchronous word number and idle bit number; the communication protocol of the user field can be customized, and the flexibility of the transmission protocol is ensured. The user can successfully transplant the visual interface into the design by simply configuring the visual interface, and meanwhile, the user also provides a data encryption function. The IP soft core has strong universality and is suitable for most models.
Description
Technical Field
The invention belongs to the embedded field, and particularly relates to an HDLC universal IP soft core.
Background
HDLC communication protocol is widely applied to various aircraft on-board embedded computer devices for information transfer between devices.
Because the requirement inputs of all models are different, the hardware designs are different, so that the matched software is also different, special persons are required to be newly allocated for software design each time of new models, additional design cost and economic cost can be caused, the project design period is prolonged, the maturity period of products is prolonged, and the product cost is increased. Because the coding personnel of different products are not necessarily the same, the code styles are very different, the code inheritance is poor, the reuse rate is low, the software engineering management is not facilitated, and the additional time cost and the labor cost can be caused.
Therefore, it is necessary to design a generalized HDLC universal IP soft core, and on the basis of meeting the requirement of speed increasing, a great deal of time and manpower can be solved, and meanwhile, the scientific research production efficiency can be improved, and the subsequent maintenance cost is reduced.
Disclosure of Invention
First, the technical problem to be solved
The technical problem to be solved by the invention is how to provide an HDLC universal IP soft core so as to solve the problems of large code style difference, poor code inheritance, low reuse rate, inconvenience for software engineering management, additional time cost, labor cost and the like in HDLC communication protocol design.
(II) technical scheme
In order to solve the technical problems, the invention provides an HDLC universal IP soft core, which comprises a bus interface, a sending monitoring module, a receiving monitoring module, a logic control module, a sending buffer memory, a receiving buffer memory and an HDLC protocol core;
bus interface: analyzing the use intention of a user and configuring an IP soft core;
a transmission/reception monitoring module: connecting the HDLC protocol core and the bus interface, and enabling the two monitoring modules to be disabled, partially enabled or fully enabled by a user according to the actual use condition of hardware chip resources; the monitoring module monitors an important state machine and a configuration register of the logic control module in the troubleshooting mode to assist a user in troubleshooting;
the logic control module: connecting HDLC protocol core and bus interface, the module has two core state machines for sending and receiving, the two core state machines respectively control the normal operation of two communication links for sending and receiving, maintaining the operation of IP soft core;
transmit/receive buffer: connecting HDLC protocol core and bus interface, the module processes the problem of asynchronous clocks between bus interface and protocol core, and caches the sent/received user data;
HDLC protocol core: the module is a core framing encoding and decoding module of the data link, and realizes framing sending and receiving analysis of HDLC protocol.
Further, the IP soft core is applied to an FPGA or ASIC of an embedded computer in an aircraft.
Further, two types of interfaces are arranged outside the IP soft check, namely a logic layer interface and a physical layer interface; the logic layer interface is connected to the processor and used for dynamically configuring functions; the physical layer interface is used as a protocol external interface to directly output or be converted into other electrical protocol interfaces by matching user hardware.
Further, the logic control module improves the gating clock with larger clock jitter and offset into clock enabling and provides clocks for other modules.
Further, the logic control module also receives dynamic configuration information received by the bus interface, processes the configuration information and provides the configuration information for the HDLC protocol core, so that external processor software can configure the baud rate, the interrupt enabling mode, the synchronous number and the idle bit number.
Further, the IP soft core is subjected to graphic visualization encapsulation, namely, the IP soft core is encapsulated to form a user-friendly operation interface.
Further, while the IP soft core is encapsulated, IEEE-1735V2 encryption is carried out on the data of the IP soft core, and the encryption coverage comprises the whole flow from HDL design entry to BIT stream generation.
Further, the IP soft core provides logical layer interface timing files and example engineering when provided to a user.
Further, when sending data, the user interacts with the bus interface of the IP soft core through the logic layer interface; writing user sending data into a sending buffer memory, and writing dynamic configuration information and a starting sending command into a logic control module; the logic control module controls an internal transmission state machine according to the starting transmission command and transmits the user data in the transmission buffer to the HDLC protocol core according to the protocol core time sequence; and the transmitting module of the HDLC protocol core carries out framing coding and finally outputs the framing coding through a physical layer tx interface.
Further, when receiving data, the user interacts with the bus interface of the IP soft core through the logic layer interface; writing the dynamic configuration information and the start receiving command into a logic control module; the logic control module opens a receiving state machine according to the starting receiving command; and enabling a receiving module of the protocol core; the docking equipment sends the data stream into the HDLC protocol core through the rx interface of the physical layer interface, the receiving module of the protocol core receives and analyzes one frame of data, and the user received data is transmitted to the receiving buffer module; and feeding back the receiving state to the logic control module; the logic control module generates an interrupt according to the receiving state; and the user interacts with the bus interface of the IP soft core through the logic layer interface, and finally, the user receiving data and the user receiving state information are read.
(III) beneficial effects
The invention provides an HDLC universal IP soft core, which has the following beneficial effects:
the IP can be adapted to common environments in the market such as XILINX, and the like, has a user-friendly interface, and is beneficial to user operation and use;
the IP source code can be packaged into a netlist file or encrypted, so that the secondary development or packaging of a user is facilitated.
The IP source code file is universal, the code file is not required to be changed in model demand change, and the self-adaption of the internal module can be realized only through static configuration and dynamic configuration.
The IP can be started through the processor interface when in use, has strong universality and is suitable for most models; no other operations are required.
The IP has an optional monitoring module which can assist the user in troubleshooting, and the monitoring module does not occupy resources if not used.
The IP has been verified by aerospace standard tests, and through flight experiments, the IP meets the speed and temperature conditions of multiple models.
Drawings
FIG. 1 is a schematic diagram of a high-level data link control IP soft core of the present invention;
FIG. 2 is a schematic diagram of configuration IP static parameters;
FIG. 3 is a schematic diagram of generating IP;
FIG. 4 is a schematic illustration of an add-in user engineering;
fig. 5 is a schematic diagram for viewing the use instruction of the HDLC generic IP soft core.
Detailed Description
To make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be given with reference to the accompanying drawings and examples.
The invention relates to a high-level data link control IP soft core transmitted on a synchronous network, which is mainly applied to an FPGA or ASIC of an embedded computer in an aircraft and is a universal IP soft core.
The invention designs an HDLC universal IP soft core which cooperates with a processor to work together, abandons the design thought of generating a gating clock by a D trigger commonly used in the industry, improves the gating clock with larger clock jitter and offset into clock enabling, reduces the dependence of the IP soft core on global clock resources, and simultaneously reduces the problem of unstable time sequence caused by the gating clock; the IP soft core can configure a use mode and a monitoring mode through static transfer parameters, and the requirements of functional diversity and resource rationality are considered; the IP soft core reserved logic layer interface supports a dynamic configuration function of the processor software; the processor software can configure baud rate, interrupt enabling mode, synchronous word number and idle bit number; the communication protocol of the user field can be customized, and the flexibility of the transmission protocol is ensured. The user can successfully migrate to the design by simply configuring the visual interface.
The HDLC universal IP soft core supports graphic visualization packaging, namely, the IP soft core is packaged to form a user-friendly operation interface, and IEEE-1735V2 encryption is carried out on data of the IP soft core while packaging, wherein the encryption coverage comprises the whole flow from HDL design entry to BIT stream generation.
The HDLC universal IP soft core can provide logic layer interface time sequence files and example engineering when being provided for users, can be compatible with common bus types in the market such as EMIF, AXI_Lite and the like, can be directly used by the users, and can customize a third type of example engineering for the users.
The composition of the HDLC generic IP soft core is shown in FIG. 1.
There are two kinds of interfaces outside the IP soft core, namely a logic layer interface and a physical layer interface. The logic layer interface can be nested into the user design or expanded to the processor through simple decoding; for dynamically configuring functions. The physical layer interface is a single-ended output interface, can be used as a protocol external interface for direct output, and can also be converted into other electrical protocol interfaces by matching with user hardware.
The IP soft check is mainly composed of seven parts, namely a bus interface, a sending monitoring module (static configuration), a receiving monitoring module (static configuration), a logic control module, a sending buffer memory (customizable), a receiving buffer memory (customizable) and an HDLC protocol core.
Bus interface: as the only interface supporting the dynamic configuration function, the interface analyzes the use intention of the user and configures the IP soft core.
Transmit/receive monitor module (static configuration): the system comprises 2 optional static configuration modules, namely a sending monitoring module and a receiving monitoring module; connecting the HDLC protocol core and the bus interface, and enabling the two monitoring modules to be disabled, partially enabled or fully enabled by a user according to the actual use condition of hardware chip resources; balancing the rationality of system design resource utilization. The monitoring module can monitor the important state machine and the configuration register of the logic control module in the troubleshooting mode to assist the user in troubleshooting.
The logic control module: the module is used as a core sequential logic control module and is provided with a sending/receiving two core state machines, and the two core state machines respectively control the normal work of the sending/receiving two communication links to maintain the operation of the IP soft core. The logic control module also has the function of generating a clock, the clock is provided for other modules of the IP soft core, the IP soft core cooperates with the processor to work cooperatively, the design thought of generating a gating clock by a D trigger commonly used in the industry is abandoned, the gating clock with larger clock jitter and offset is improved to be enabled by the clock, the dependence of the IP soft core on global clock resources is reduced, and meanwhile, the problem of time sequence instability caused by the gating clock is reduced. The logic control module also receives dynamic configuration information received by the bus interface, processes the configuration information and provides the configuration information for the HDLC protocol core, so that external processor software can configure the baud rate, the interrupt enabling mode, the synchronous number, the idle bit number and the like.
Transmit/receive buffer (customizable): the HDLC protocol core and the bus interface are connected, and the module is used for processing the problem of asynchronous clocks of the bus interface and the protocol core and buffering the sent/received user data.
HDLC protocol core: the module is a core framing encoding and decoding module of the data link, and realizes framing sending and receiving analysis of HDLC protocol.
When transmitting: the user interacts with the bus interface of the IP soft core through the logic layer interface; writing user sending data into a sending buffer memory, and writing dynamic configuration information and a starting sending command into a logic control module; the logic control module controls an internal transmission state machine according to the starting transmission command and transmits the user data in the transmission buffer to the HDLC protocol core according to the protocol core time sequence; and the transmitting module of the HDLC protocol core carries out framing coding and finally outputs the framing coding through a physical layer tx interface (txc, txd, txen).
Upon reception: the user interacts with the bus interface of the IP soft core through the logic layer interface; writing the dynamic configuration information and the start receiving command into a logic control module; the logic control module opens a receiving state machine according to the starting receiving command; and enabling a receiving module of the protocol core; the docking equipment sends the data stream to the HDLC protocol core through an rx interface (rxc, rxd, rxen) of the physical layer interface, a receiving module of the protocol core receives and analyzes one frame of data, and a user received data is transmitted to a receiving buffer module; and feeding back the receiving state to the logic control module; the logic control module generates an interrupt according to the receiving state; and the user interacts with the bus interface of the IP soft core through the logic layer interface, and finally, the user receiving data and the user receiving state information are read.
Example 1: HDLC general IP soft core user friendly configuration interface introduction (XILINXVIAVADO environment example)
The first step: configuring IP static parameters as shown in figure 2;
and a second step of: generating an IP as shown in fig. 3;
and a third step of: add to user engineering as shown in fig. 4;
fourth step: viewing the HDLC generic IP soft core usage specification, as shown in fig. 5, which is contained in the IP subdirectory, the user can view at the GUI interface point right-hand key.
Embodiment 2 IP soft core co-processor dynamic configuration co-operating method (exemplified by dsp+fpga) DSP uses HDLC generic IP soft core method:
tx：
when the DSP is powered on and initialized, registers HDLC_ADDR, HDLC_PERIOD, FLAG_ADDR and HDLC_IER are configured for the HDLC universal IP soft core;
each time a packet number is sent, firstly configuring the number of bytes sent on the TXCOUNT_ADDR address;
fifo_ram_sel=ram, and user data (lower 8 bits of the data line) is written from 1 to 1 in order from address txram_addr;
fifo_ram_sel=fifo, user data (the lower 8 bits of the data line) is written on the address fifo_addr; finally, writing a start sending command on the TXSTART_ADDR address;
receiving a corresponding transmission interrupt, indicating that the transmission is complete.
rx：
When dsp needs to accept, first write START receive command on rx_start address;
when data is transmitted to the dsp, the corresponding receiving interrupt is valid;
after the dsp receives the corresponding interrupt, it reads the receive status word in the address rx_state;
reading the number of bytes of the received packet in address rxcount_addr;
fifo_ram_sel=ram, 1 is sequentially added to address rxbase_addr, and user data (the lower 8 bits of the data line) is read;
fifo_ram_sel=fifo, user data (the lower 8 bits of the data line) is read out on the address fifo_addr; and (3) monitoring:
when the FPGA statically enables the transmit/receive monitor module, the monitor FIFO automatically collects the transmit/receive monitor information of the last packet number.
The monitoring module receives or sends the FIFO to complete the reset by the start receive and start send instructions issued by the DSP.
The dsp may read the transmit monitor module monitor information at the tx_fsm address.
The dsp may read the receive monitor module monitor information at the rx_fsm address.
Example 3: HDLC general IP soft core matched processor performance test (exemplified by DSP+FPGA)
The IP soft core performs 4000-byte loop test on single frame data by matching with DSP6713 of TI company in FPGA of model K7325t of XILINX company, wherein each test is performed for 2 hours, the system clock is below 250Mhz, and no error code is generated.
The advantages of the invention are as follows:
the IP can be adapted to common environments in the market such as XILINX, and the like, has a user-friendly interface, and is beneficial to user operation and use;
the IP source code can be packaged into a netlist file or encrypted, so that the secondary development or packaging of a user is facilitated.
The IP source code file is universal, the code file is not required to be changed in model demand change, and the self-adaption of the internal module can be realized only through static configuration and dynamic configuration.
The IP can be started through the processor interface when in use, has strong universality and is suitable for most models; no other operations are required.
The IP has an optional monitoring module which can assist the user in troubleshooting, and the monitoring module does not occupy resources if not used.
The IP has been verified by aerospace standard tests, and through flight experiments, the IP meets the speed and temperature conditions of multiple models.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (7)
1. The HDLC universal IP soft core is characterized by comprising a bus interface, a sending monitoring module, a receiving monitoring module, a logic control module, a sending buffer, a receiving buffer and an HDLC protocol core;
bus interface: analyzing the use intention of a user and configuring an IP soft core;
a transmission/reception monitoring module: connecting the HDLC protocol core and the bus interface, and enabling the two monitoring modules to be disabled, partially enabled or fully enabled by a user according to the actual use condition of hardware chip resources; the monitoring module monitors an important state machine and a configuration register of the logic control module in the troubleshooting mode to assist a user in troubleshooting;
the logic control module: connecting HDLC protocol core and bus interface, the module has two core state machines for sending and receiving, the two core state machines respectively control the normal operation of two communication links for sending and receiving, maintaining the operation of IP soft core;
transmit/receive buffer: the HDLC protocol core is connected with the bus interface for user customization, and the module processes the problem of asynchronous clocks of the bus interface and the protocol core and caches the sent/received user data;
HDLC protocol core: the module is a core framing encoding and decoding module of a data link, and realizes framing sending and receiving analysis of HDLC protocol;
wherein,
the logic control module improves the gating clock with larger clock jitter and offset into clock enabling and provides clocks for other modules;
when sending data, the user interacts with the bus interface of the IP soft core through the logic layer interface; writing user sending data into a sending buffer memory, and writing dynamic configuration information and a starting sending command into a logic control module; the logic control module controls an internal transmission state machine according to the starting transmission command and transmits the user data in the transmission buffer to the HDLC protocol core according to the protocol core time sequence; the transmitting module of HDLC protocol core carries out framing coding and outputs through physical layer tx interface;
when receiving data, a user interacts with a bus interface of the IP soft core through a logic layer interface; writing the dynamic configuration information and the start receiving command into a logic control module; the logic control module opens a receiving state machine according to the starting receiving command; and enabling a receiving module of the protocol core; the docking equipment sends the data stream into the HDLC protocol core through the rx interface of the physical layer interface, the receiving module of the protocol core receives and analyzes one frame of data, and the user received data is transmitted to the receiving buffer module; and feeding back the receiving state to the logic control module; the logic control module generates an interrupt according to the receiving state; and the user interacts with the bus interface of the IP soft core through the logic layer interface, and finally, the user receiving data and the user receiving state information are read.
2. The HDLC generic IP soft core according to claim 1, applied to an FPGA or ASIC of an aircraft on-board embedded computer.
3. The HDLC universal IP soft core according to claim 1, wherein there are two types of interfaces outside the IP soft core, namely a logical layer interface and a physical layer interface; the logic layer interface is connected to the processor and used for dynamically configuring functions; the physical layer interface is used as a protocol external interface to directly output or be converted into other electrical protocol interfaces by matching user hardware.
4. The HDLC universal IP soft core according to claim 3, further characterized in that the logic control module receives dynamic configuration information received by the bus interface, processes the configuration information and provides the processed configuration information to the HDLC protocol core, so that the external processor software can configure the baud rate, the interrupt enable mode, the number of sync words and the number of idle bits.
5. The HDLC generic IP soft core according to any of claims 3-4, wherein the IP soft core is encapsulated for graphical visualization, i.e. the IP soft core is encapsulated to form a user friendly operation interface.
6. The HDLC generic IP soft core according to claim 5, wherein the data of the IP soft core is encrypted by IEEE-1735V2 while the IP soft core is encapsulated, and the encryption coverage includes the entire flow from the HDL design entry to BIT stream generation.
7. The HDLC generic IP soft core according to any of claims 3-4, which provides logical layer interface timing files and instance engineering when provided to a user.
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