CN110545319A

CN110545319A - design of SoC core system and method for realizing task communication between cores

Info

Publication number: CN110545319A
Application number: CN201910784397.0A
Authority: CN
Inventors: 占颂; 熊烁; 陈天航; 王昌杰; 彭雅倩; 宋宝; 唐小琦; 苏小宇; 陈威
Original assignee: Wuhan Long Intelligent Technology Co Ltd
Current assignee: Wuhan Long Intelligent Technology Co Ltd
Priority date: 2019-08-23
Filing date: 2019-08-23
Publication date: 2019-12-06

Abstract

The invention belongs to the technical field of multi-axis motion control, and discloses a method for designing an SoC (system on chip) core system and realizing task communication between cores, which is used for constructing a dual-core system and completing the transplantation of equipment drive; performing communication based on the shared memory; aiming at different communication tasks, carrying out multi-task communication by utilizing shared information; the system for designing the SoC core system under the MP architecture and realizing the task communication among the cores comprises the following steps: the SoC minimum system is used for completing management and distribution of system shared resources, analyzing the control time sequence, completing communication among units and simultaneously communicating with the platform interface; and the platform interface is used for completing the functions of servo driving, system monitoring and IO control. The multi-axis motion control platform has complete use function, the real-time performance and synchronous control of the system meet the use requirements of motion control, and the multi-axis motion control platform can be used for real-time communication and multi-axis synchronous control of the robot.

Description

Design of SoC core system and method for realizing task communication between cores

Technical Field

The invention belongs to the technical field of multi-axis motion control, and particularly relates to a method for designing an SoC (system on chip) core system and realizing task communication between cores.

Background

Currently, the closest prior art:

With the rapid development of power electronics and control theory, industrial robots are widely applied in the fields of modern integrated manufacturing (CIMS), Flexible Manufacturing (FMS), and automation Factory (FA). Industrial robots are automated equipment that integrate mechanical, electronic, control, computer, sensor, etc. technologies. The motion controller is used as a core control unit, and has important influence on the positioning precision, the response speed and the multi-axis synchronous control of the robot.

The robot system mainly comprises a control center, a driving device, a detection device, an execution element and a corresponding mechanical structure. In the motion control process, a control system transmits a work instruction to the driving device according to a specified task, and then controls the executing mechanism to complete specified motion. In order to adapt to diversified application scenarios, motion controllers are being developed in the directions of multi-axis, integrated, small and modular. On one hand, with the rapid development of the automation industry, the robot is required to occupy less space and be flexibly configured and used in a light-weight and small-sized pipeline operation environment; on the other hand, when the control mode of the industrial ethernet is adopted, a certain time delay exists in the information transmission between the control system and the servo driver, which has a certain influence on the synchronous control and the quick response of the multi-axis control system.

The embedded motion control platform is researched:

The motion controller can be divided into the following three types according to different control cores: a professional motion controller PLC, a PC-based PCI (peripheral Component interconnect) bus motion control card and an embedded motion controller. The embedded motion controller has the characteristics of high integration level, flexible customization, low cost, good applicability and the like, and is widely applied to the field of robot control.

The embedded control platform realizes specific control logic through an integrated circuit chip, and achieves the aims of quick response and high-precision control through the high-speed processing of data and the information communication capacity. With the rapid development of electronic technology, a core processor of a control platform has diversified selection schemes:

The method adopts a singlechip as a core:

The motion control platform adopting the single chip microcomputer is simple in overall structure, small in development difficulty and convenient to realize. The MSP430F449 singlechip is adopted to realize the motion control of the stepping motor. The single chip microcomputer has relatively few internal integrated circuits and limited data processing capacity, and cannot integrate complex peripheral interfaces, so that the method is suitable for application scenes for realizing simple motion control.

The special integrated chip is adopted as a core:

An Application Specific Integrated Circuit (ASIC) can realize a motion control system with certain Specific functional purposes, and the requirements of application scenes specified by users are met. The IRMCF171 special chip is adopted to realize the motion control of the medical centrifuge. The motion controller using ASIC as a core has good reliability and stability, but its versatility and customizability are poor, and it cannot be compatible with various usage scenarios.

An SoC (System on a chip) integrated processor is adopted as a core:

the SoC processor adopted in the industrial field is composed of one or more DSPs/ARM and FPGA. The ARM (advanced RISC machines) processor and the DSP (digital Signal processing) digital Signal processor both have the high-speed processing capability of data and simultaneously provide rich peripheral interface functions. An FPGA (field programmable Gate array) field editable Gate array has a large number of editable Gate circuits, and is convenient to realize diversified functional design. A robot motion control system based on an ARM + FPGA framework is designed. The motion controller based on the SoC has the characteristics of high data processing speed, complete communication mechanism and rich communication interfaces; meanwhile, the FPGA pin resources are rich, the customized function can be realized, the signal transmission delay is small, and the function integration and expansion of the controller are facilitated.

the embedded motion control platform interconnection technology researches the current situation and trend:

the robot control system is required to have not only a data fast processing capability but also a communication method for transmitting information at high speed. Currently, impulse motion control is gradually replaced by bus communication. In a bus-type motion control system, a controller and a driver of the system are physically separated, and an industrial field bus is adopted between the controller and the driver for connection and information communication. Currently, the mainstream industrial field bus protocols include Ethernet/IP, PROFINET, POWERLINK, EtherCAT and SERCOSIII. A plurality of motion control companies in the industry provide motion control products of the industrial bus type.

Meanwhile, with the advent of SoC integrated chips, motion control systems interconnected by board-level buses have become a research hotspot. The motion control system integrates the controller and the driver in the same hardware platform, and the controller and the driver are interconnected and interacted with each other through a board-level bus. The control system of drive-control integration has smaller volume, data communication is completed in the board, and the transmission rate is high, stable and reliable. Meanwhile, the SoC chip uses a unique external clock source, so that the clock consistency of the control platform is ensured, and the real-time performance and the synchronism of the system are improved.

at present, there are three types of on-chip bus standards used on SoC chips, which are: AMBA (advanced Microcontroller Bus architecture) Bus proposed by ARM, Wishbon Bus proposed by Silicore, and Avalon Bus proposed by Altera. The AMBA bus is a high-performance on-chip bus specification, and the standard of the AMBA bus is open and is adopted by 90% of partners of ARM companies. In 2009, Xilinx and ARM company jointly design an AMBA AXI4 bus protocol for high-speed interconnection of ARM chips and FPGAs, and the bus protocol is used in Xilinx new-generation SoC integrated chips. The AMBA AXI4 bus has the following characteristics:

(1) The development efficiency of the user is effectively improved:

The AXI4 protocol completes integration of different types of interfaces, provides a universal series of interfaces for users, reduces development difficulty and saves development time.

(2) More flexible configurations are provided:

The AXI4 protocol can be used for various embedded chips, and the integrated design meets the use requirements in the aspects of performance, power consumption, area and the like.

(3) Providing extensive IP Core (Intellectual Property Core) support:

The XilinxSoC chip integrates a single or multiple high-performance ARM processors and a large-capacity FPGA, and provides numerous third-party IP core support.

The current state and trend of communication technology research among cores of a multi-core processor are as follows:

The single-chip multi-core processor is developed in the embedded field aiming at the bottleneck problem of the single-core processor in the aspects of chip power consumption, integration complexity and the like. The multicore processor may be divided into homogeneous (homogeneous) cores with the same architecture and heterogeneous (heterogeneous) cores with different architectures according to whether the on-chip multicore cores have the same architecture. For example, an ARM + DSP integrated architecture is adopted by Sitara AM6x under the flag of Texas Instruments (TI), so that the high-speed digital signal processing and real-time system carrying capacity is provided; XilinxZynq series and Altera SoC FPGA series products adopt an ARM + FPGA integrated framework, the chip performance is superior, and a user can conveniently carry out customized function design through the FPGA.

When a multi-core chip is adopted for system design, task communication among cores is one of key technologies for realizing system functions and improving performance. The system working structure of the Multi-core processor is divided into a Symmetric Multi-Processing (SMP) architecture and an Asymmetric Multi-Processing (AMP) architecture. When the SMP architecture is adopted, the operating system is responsible for cooperation among the processors to complete task communication among the multiple cores. Under an operating system, there are various methods for realizing the inter-task communication, including semaphore, message mailbox, message queue, pipeline, etc. And data communication is realized among tasks under the operating system through a nameless pipeline.

When the AMP architecture is employed, different systems run on different cores. Task communication among the cores under the AMP framework mainly uses a shared memory as a data transmission medium, and signal triggering is realized through modes such as inter-core interruption and the like, so that information interaction among the cores is completed. The heterogeneous multi-core processor needs to adopt an AMP architecture for system design. The Huadong computational technology research institute adopts ARM + DSP heterogeneous multi-core to complete the transplantation of Linux systems and domestic DSPReWorks systems. The Otsu electronics university first-class schooling adopts an OMAP multi-core processor, designs a semaphore-based data communication method between multiple cores, and ensures the safety and mutual exclusion of data communication.

In summary, the problems of the prior art are as follows:

(1) When the industrial Ethernet control mode is adopted, the information transmission of the control system and the servo driver has time delay, and the synchronous control and the quick response of the multi-axis control system are influenced.

(2) The motion control platform adopting the single chip microcomputer has relatively few internal integrated circuits, limited data processing capacity, and can not integrate complex peripheral interfaces, and only can be suitable for application scenes for realizing simple motion control.

(3) The motion controller adopting the ASIC as the core has poor universality and customizability, and cannot be compatible with various use scenes.

The significance of solving the technical problems is as follows:

The OCM is adopted to reduce the data delay, so that a shorter data communication period can be achieved; and the double-core data is synchronized by adopting an interrupt mode, so that better synchronization performance is obtained. The OCM is adopted to reduce the data delay, so that a shorter data communication period can be achieved; and the double-core data is synchronized by adopting an interrupt mode, so that better synchronization performance is obtained.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a method for designing an SoC core system and realizing task communication between cores.

The invention is realized in such a way that a method for realizing the design of an SoC core system and the inter-core task communication under an AMP architecture comprises the following steps:

Step one, constructing a dual-core system and completing the transplantation of equipment drive; the built dual-core system comprises a Linux real-time system and a servo bare computer system; the Linux is operated in real time by the core of the Linux real-time system, and the bare engine for controlling the direct loading and operation of the application program is carried by the core of the servo bare engine system.

Performing inter-core data communication by adopting an OCM shared memory, and performing access control of an inter-core semaphore to the OCM;

Thirdly, multi-task communication is carried out by utilizing shared information aiming at different communication tasks; and by utilizing mechanisms of periodic data communication and non-periodic data communication, the periodic data adopts an interrupt mode, the message is fixed, the servo side initiates periodic interrupt, the non-periodic data communication variable-length message, and the bare computer side polls and processes the inspection request.

Further, the building of the dual-core system in the first step comprises building a Linux real-time system and building a servo bare engine system.

The Linux real-time system building method comprises the following steps:

1) Xenomai real-time patch installation. And running robot control software on a Linux real-time operating system of the CPU0 to establish a Xenomai real-time motion task.

2) And (5) transplanting a Linux device driver. Based on the design of a key communication interface of the SoC, the external drive is transplanted under a Linux system, so that correct use of system equipment is guaranteed, and external communication of the platform is realized.

The servo bare metal system building comprises:

A servo bare engine system is built by utilizing the CPU1 and used for directly loading and running servo control application programs, and the using number of the CPUs is set to be 1 when the Linux system runs. The CPU0 completes the loading of the CPU1 servo application. The CPU0 completes the wake-up of the CPU 1.

Further, the step one of completing the device-driven migration specifically includes:

(1) When the kernel provides the device driver, the driver in the kernel is directly used.

(2) And designing a driver and transplanting the device which does not provide the driver in the kernel.

further, the step two of performing a communication method based on the shared memory includes management of the shared memory, which specifically includes:

1) When the robot control program starts to run, the Linux system completes OCM access application and initializes the OCM.

2) After the servo system is re-run each time, the Linux system needs to initialize the OCM.

3) And when the running of the robot control program is finished, the Linux system closes the memory mapping and releases the shared memory.

further, the method for performing shared memory-based communication in step two further includes inter-core semaphore communication, which specifically includes:

And using binary internuclear semaphores and restricting the access of the internuclear semaphores according to the communication time sequence of the dual-core task. Before the dual-core task communication starts, the Linux system initializes the semaphore to be 1. In the dual-core task communication stage, carrying out the following steps on the semaphore:

1) The dual-core system has readable/writable right to semaphore, and if the read-write operation occurs simultaneously, the read operation priority is higher than the write operation priority.

2) And in the dual-core system task communication stage, sequential semaphore access of reading by the CPU0, modifying by the CPU0, reading by the CPU1 and modifying by the CPU1 is carried out.

Further, the method for performing shared memory-based communication in step two further includes message mailbox communication, which specifically includes:

1) The fixed-length mailbox communication, the mail data length is fixed, and the system is set to 8/16/32/64 bits according to the use requirement of the communication data.

2) And (4) variable-length mailbox communication, which analyzes the mail content by using a data frame format supporting a read-write command and variable data length.

further, the step three multitask communication method comprises the following steps: non-periodic task communication technology and periodic task communication technology.

the aperiodic task communication technology is used for reading information of a Linux system to a servo system, and specifically comprises the following steps:

1) A data link. And completing a data link of non-periodic communication by adopting a variable-length mailbox, and completing switching of a system communication state by using an internuclear semaphore.

2) non-periodic task implementation based on a polling mechanism. And circularly inquiring the semaphore of non-periodic communication in the servo system by using a communication method based on the servo system polling semaphore, and judging whether the Linux initiates communication according to the semaphore. And if the communication is initiated, the servo system carries out response operation to complete the inter-core communication task.

The periodic task communication technology is used for completing updating of periodic control instructions and feedback of servo motion data, and therefore multi-axis motion control is achieved. The method specifically comprises the following steps:

1) And the data link completes the data link of periodic communication by adopting a mailbox with a fixed length, and completes the switching of the communication state of the system by using the internuclear semaphore.

2) The method is characterized in that a hardware interrupt mechanism is used for realizing periodic tasks, the communication of the periodic tasks between two cores is carried out by adopting FPGA hardware interrupt, and a Linux system and a servo system are both synchronous to the FPGA. And when the FPGA interrupt signal is received, the dual-core system respectively responds, and the data communication between the dual cores is completed by executing the interrupt service program.

Another objective of the present invention is to provide a system for implementing SoC core system design and inter-core task communication under MP architecture, where the system for implementing SoC core system design and inter-core task communication under MP architecture includes:

and the SoC minimum system is used for completing management and distribution of system shared resources, analyzing the control time sequence, completing communication among units and simultaneously communicating with the platform interface.

And the platform interface is used for completing the functions of servo driving, system monitoring and IO control.

Further, the SoC minimum system includes a processor 0, a processor 1, and an FPGA.

The processor 0 is configured to carry a real-time operating system, and the real-time operating system includes: and running robot control software to complete motion planning and instruction generation. And the system communication interface is used for realizing multi-task communication with the servo system and finishing data interaction. And managing SoC peripheral resources, and providing peripheral drive support to realize connection and communication with external equipment.

the processor 1 is used for mounting and operating a servo bare metal system. The servo bare metal system comprises: and operating servo control software for completing the three-loop control. And the system communication interface is used for realizing multi-task communication with the operating system and finishing data interaction. And the management SoC peripheral is used for realizing the connection of the external equipment and the acquisition of signals.

And the FPGA is used for realizing the self-definition of the functional module. The functional module includes: a hardware interrupt generator is designed to provide interrupt signals with fixed periods for the processor 0 and the processor 1, and the interrupt signals are used for realizing multi-task communication between dual-core systems.

The multi-axis driving circuit also comprises a PWM generator, a current sampling and encoder analyzing multi-axis driving module.

the platform interface includes a communication interface and a system interface.

The communication interface includes: and the RS232 serial port is used for controlling system development and test of the platform and later maintenance of the system.

And the USB2.0 interface is used for connecting an external keyboard, a mouse and a USB flash disk device to realize online upgrading of the system.

And the gigabit Ethernet interface is used for connecting the platform with a handheld box or a PC (personal computer) machine to realize upper computer communication.

And the industrial Ethernet interface is used for connecting an external servo driver or industrial camera equipment to realize the expansion of the platform function.

The system interface is used for completing the functions of servo driving, system monitoring and IO control.

Further, the SoC minimum system further includes:

The system comprises a system starting module, a system interruption and clock module, a storage control module and an external nonvolatile storage module.

and the system starting module comprises three starting modes of JTAG, SD card and QSPI Flash. The JTAG mode is used for quickly positioning users and solving the problem of system development. The SD card mode is used for ensuring the quick replacement and the moving of the system file. The QSPI Flash mode is used for platform product design.

And the system interrupt and clock module adopts PL to provide interrupt signals for the SoC dual core. PL is clocked through the clock domain of PS.

And the storage control module is internally integrated with a DDR storage controller in the SoC and provides an external communication interface.

And the external nonvolatile storage module is used for storing the system default parameters and the system starting program of the motion control platform by utilizing QSPI Flash. The eMMC is used for independent storage of the CPU0, the CPU1 and PL files, and dynamic loading and updating of the files are achieved.

In summary, the advantages and positive effects of the invention are:

The multi-axis motion control platform has complete use function, and the real-time performance and synchronous control of the system meet the use requirements of motion control.

In the management of the shared memory, 256K on-chip memories in the SoC chip are used as the shared memory, and the on-chip shared memory OCM can be used for loading and running a system starting file in the starting process of the SoC chip. After the system is started, the data in the OCM is not empty. Therefore, when the OCM is used for task communication, in order to ensure the safety and consistency of data in the OCM, when the robot control program starts to run, the Linux system finishes OCM access application and initializes the OCM. After the servo system is re-run each time, the Linux system needs to initialize the OCM. And when the running of the robot control program is finished, the Linux system closes the memory mapping and releases the shared memory.

In the inter-core semaphore design, binary inter-core semaphores are used, and access to the inter-core semaphores is restricted according to the inter-core task communication timing sequence. Before the dual-core task communication starts, the Linux system initializes the semaphore and sets the semaphore to be 1. In the dual-core task communication stage, the following operations are carried out on the semaphore: the dual-core system has readable/writable right to the semaphore, and if the read-write operation occurs simultaneously, the priority of the read operation is higher than that of the write operation. And in the dual-core system task communication stage, sequential semaphore access of 'reading by the CPU 0-modifying by the CPU 0-reading by the CPU 1-modifying by the CPU 1' is carried out.

In the design of the message mailbox, two mailbox communication modes are designed, namely fixed-length mailbox communication and variable-length mailbox communication. In the fixed-length mailbox communication, the mail data length is fixed, and the system can be set to 8/16/32/64 bits according to the use requirement of the communication data. When the variable-length mailbox is used for communication, the mail content is a communication data frame, and the length of the data frame is not fixed. In order to ensure the correct analysis of the mail, the invention designs and uses a data frame format supporting read-write commands and variable data length.

In the multitask communication, an aperiodic task communication technique and a periodic task communication technique are adopted.

In the aperiodic task communication technology, in the process of controlling the multi-axis motion, the dual-core system aperiodic task communication is mainly used for reading information of a Linux system on a servo system, such as servo parameters.

And designing a data link. Adopting a variable-length mailbox to complete a data link of non-periodic communication, and using an internuclear semaphore to complete switching of a system communication state; non-periodic task implementation based on a polling mechanism. The invention uses a communication method based on the polling semaphore of a servo system, the semaphore of non-periodic communication is circularly inquired in the servo system, and whether Linux initiates communication is judged according to the semaphore; and if the communication is initiated, the servo system carries out response operation to complete the inter-core communication task.

In the periodic task communication technology, during the control process of multi-axis motion, the periodic task communication of a dual-core system is mainly used for completing the updating of periodic control commands and the feedback of servo motion data, so as to realize multi-axis motion control.

And designing a data link, finishing the data link of periodic communication by adopting a mailbox with a fixed length, and finishing the switching of the communication state of the system by using the internuclear semaphore.

Meanwhile, the periodic task based on a hardware interrupt mechanism is realized, and the two-core periodic task communication is carried out by adopting FPGA hardware interrupt, namely, the Linux system and the servo system are both synchronous with the FPGA. When the FPGA interrupt signal arrives, the dual-core system respectively responds, and data communication between the dual cores is completed by executing an interrupt service program.

In the system real-time and synchronous control test, the invention carries out the following steps:

(1) and testing the real-time performance of the communication task.

The real-time performance of system communication specifically requires that the dual cores complete task communication and operation within a specified time. In the real-time test, the Linux system is used for completing the servo enabling, and the dual-core communication period is set to be 1 ms. The servo system enters 100us fixed period current loop control after being enabled. In order to ensure real-time performance, the servo system needs to complete dual-core task communication and interrupt service program execution within 100us, and wait for the interrupt signal of the next period. In the test process, a synchronous signal Sync is set in a servo system, and the signal is externally connected to an IO pin. And when the servo system receives the communication signal of the Linux system in the interrupt service and completes data communication, the Sync signal is set to be at a high level. When the servo system exits the interrupt service routine, the Sync signal is set to a low level. The Sync signal, the servo system 100us interrupt signal and the Linux system 1ms interrupt signal are continuously sampled by an oscilloscope.

In the sampling result, a brown line represents a Sync signal, a green line represents a servo system 100us interrupt signal, and a blue line represents a Linux system 1ms interrupt signal. The interrupt signal of the dual core system is active at the time of the rising edge. At time t1, 2 system interrupts occur in synchronization. At time t2, the servo system completes task communication with the Linux system. At time t3, the servo completes the interrupt service and exits. At time t4, the next 100us cycle of interrupt signals arrives. The servo system interrupt service time is 81.08us (difference between t3 and t 1), and the task communication time for the dual-core system is 18.84us (difference between t2 and t 1). The test result shows that the dual-core system completes task communication and data calculation within the designated time, and the real-time performance of the motion control system meets the use requirement.

(2) and (5) multi-axis synchronous control testing.

The specific requirement of the system synchronous control is to control multiple axes to move synchronously. In the multi-axis synchronous control test, a servo system is enabled through a Linux system, and motion control of a 1ms interpolation period is performed. In order to verify the synchronous control of the multi-axis motion, four paths of PWM motor driving signals generated by the control platform are continuously sampled through an oscilloscope. And (3) sampling results of four paths of U-phase positive-phase signals, wherein a yellow line is a 1-axis signal, a green line is a 2-axis signal, a blue line is a 3-axis signal, and a red line is a 4-axis signal. At times t1 and t3, the U + signal of the four-way PWM is active at the same time, and at times t2 and t4, the U + signal of the four-way PWM is inactive at the same time.

As shown in Table 15, the test of the effective period of each phase signal of U +/U-, V +/V-and W +/W-of the four-way motor PWM is completed, and the time error between the actual effective period and the control period of each signal is calculated. The test result shows that the effective period of each phase signal of the four-way motor PWM fluctuates within 0.1us, the fluctuation proportion is less than 0.1 percent, the motion state of the motor cannot be influenced, and the synchronous control effect of the platform is good.

TABLE 15 PWM signal control period test for four-way motor

Sampling signal	Control period (us)	Actual effective period (us)	Time fluctuation range (us)
				U+	100	100.06	0.06
U-	100	100.03	0.03
				V+	100	100.04	0.04
V-	100	100.07	0.07
				W+	100	99.98	0.02
W-	100	100.02	0.02

in the robot control software online test, the robot control software is operated on the motion control platform to test the connection function with the robot hand-held box. First, after the motion control system is started, the IP address of the motion control platform is set to 192.168.1.113. And after the setting is successful, running the robot control software hrtapp-5.

After the robot control software runs, the motion control platform communicates with the handheld box through the gigabit Ethernet interface. The IP address of the handset is first set to 192.168.1.114 to complete the network connection with the control platform. After the handheld box is normally connected with the motion control platform, enabling a SERVO system through an SERVO ON command, and reading the initial position of the four shafts of the motion platform. The handheld box software reads the initial angles of the four axes consistent with the data from the robot controller software. The test result shows that the robot control software normally runs on the platform, and the platform is connected and communicated with the handheld box.

the invention provides a method for designing an SoC core system under an AMP architecture and realizing task communication among cores, which comprises the following steps: and the heterogeneous cores comprise a core running the real-time linux and another core bare machine.

And performing inter-core data communication by using an OCM shared memory.

Access control of the OCM by the internuclear semaphores.

The periodic data communication and the non-periodic data communication are realized by a mechanism, the periodic data adopts an interrupt mode, the message is fixed, the servo side initiates periodic interrupt and non-periodic data communication variable-length messages, and the bare computer side polls and checks requests and processes the requests.

The present invention adopts a dual-core scheme. Dual cores are facing different applications: the core 1 adopts a Linux system, and has rich software resources, high development efficiency and flexibility; the core 0 adopts a naked core, is concentrated in control, and has high real-time performance and shorter control period; compared with a separate control device, the device has higher cost performance. The invention adopts OCM to simplify the dual-core communication development process and reduce the difficulty. The invention adopts an interrupt mode to synchronize the data of the double cores, thereby obtaining better synchronization performance.

Drawings

Fig. 1 is a flowchart of a design method of an SoC core system under an AMP architecture according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a minimum system functional module of the SoC according to an embodiment of the present invention.

Fig. 3 is a flowchart of an implementation method for SoC core system design and inter-core task communication under an AMP architecture according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a split multi-axis motion control system according to an embodiment of the present invention.

Fig. 5 is a schematic diagram of an integrated multi-axis motion control system according to an embodiment of the present invention.

Fig. 6 is a diagram of an internal interconnection framework of a Zynq 7020SoC system according to an embodiment of the present invention.

Fig. 7 is a general block diagram of an SoC multi-axis motion control platform according to an embodiment of the present invention.

Fig. 8 is a diagram of a dual-core system multitask communication implementation scheme according to an embodiment of the present invention.

Fig. 9 is a block diagram of a SoC minimum hardware system structure according to an embodiment of the present invention.

FIG. 10 is a block diagram of a PL clock management module according to an embodiment of the present invention.

Fig. 11 is a block diagram of an implementation of a system interrupt generator according to an embodiment of the present invention.

FIG. 12 is a diagram illustrating DDR3SDRAM connections according to an embodiment of the invention.

FIG. 13 is a schematic diagram of a QSPI Flash memory connection provided by an embodiment of the present invention.

Fig. 14 is a schematic diagram of an eMMC memory connection according to an embodiment of the present invention.

fig. 15 is a block diagram of the communication structure of the AXI4, AXI4-Lite and AXI4-Stream protocols provided by the embodiment of the present invention.

Fig. 16 is an AXI communication interface connection diagram of PS and PL according to an embodiment of the present invention.

FIG. 17 is an AXI4-Lite interface connection diagram of PS and PL provided by an embodiment of the present invention.

Fig. 18 is a schematic diagram illustrating access to Cache by a dual-core CPU according to an embodiment of the present invention.

Fig. 19 is a timing diagram of communication between processing units of the SoC system according to an embodiment of the present invention.

In the figure: t1, communication time of the CPU1 and the FPGA; t2 communication time between CPU0 and CPU 1; s1, acquiring and calculating time of servo data in the FPGA; s2, CPU1 servo task operation time; s3 the CPU0 controls task operation time.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

When the industrial Ethernet control mode is adopted, the information transmission of the control system and the servo driver has time delay, and the synchronous control and the quick response of the multi-axis control system are influenced. The motion control platform adopting the single chip microcomputer has relatively few internal integrated circuits, limited data processing capacity, and can not integrate complex peripheral interfaces, and only can be suitable for application scenes for realizing simple motion control. The motion controller adopting the ASIC as the core has poor universality and customizability, and cannot be compatible with various use scenes.

Aiming at the problems in the prior art, the invention provides a multi-core SoC-based multi-axis motion control system and a multi-core SoC-based multi-axis motion control method, and the invention is described in detail in combination with the technical scheme.

The design of the SoC core system under the AMP architecture and the realization method of the task communication among the cores provided by the embodiment of the invention comprise the following steps:

And step two, performing inter-core data communication by adopting an OCM shared memory, and performing access control of inter-core semaphores to the OCM.

the first step of building the dual-core system comprises building a Linux real-time system and building a servo bare engine system.

The Linux real-time system building method comprises the following steps:

The servo bare metal system building comprises:

The step one of completing the migration of the device driver specifically comprises the following steps:

Step two, the communication method based on the shared memory comprises the management of the shared memory, which specifically comprises the following steps:

the second step of performing the shared memory-based communication method further includes inter-core semaphore communication, which specifically includes:

step two, the method for performing communication based on the shared memory further comprises message mailbox communication, and specifically comprises the following steps:

The step three multitask communication method comprises the following steps: non-periodic task communication technology and periodic task communication technology.

The embodiment of the invention provides a system for designing an SoC core system under an MP architecture and realizing task communication among cores, which comprises the following steps:

the SoC minimum system includes a processor 0, a processor 1, and an FPGA.

in this embodiment of the present invention, as shown in fig. 1, a method for designing an SoC core system under an AMP architecture provided in the embodiment of the present invention specifically includes:

S101, designing SoC system hardware, including SoC minimum system hardware and functional module design.

s102, exclusive allocation of shared resources of the SoC system; the AXI4-Lite protocol interface is adopted to realize the high-speed interconnection between PS and PL units.

And S103, designing a communication time sequence of the SoC control system, and ensuring the synchronous control requirement of the system.

And S104, designing a circuit of the platform key communication interface.

as shown in fig. 2, the SoC minimum system function module provided in the embodiment of the present invention specifically includes: the system comprises a system starting module, a system interruption and clock module, a storage control module and an external nonvolatile storage module;

The system starting module comprises three starting modes of JTAG, SD card and QSPI Flash; the JTAG mode is used for quickly positioning the user and solving the problem of system development; the SD card mode is used for ensuring the quick replacement and moving of system files and reducing the system development time; the QSPI Flash mode is used for ensuring the quick start and stable operation of the system and is used for the platform product design.

The system interrupt and clock module adopts PL to provide interrupt signals for the SoC dual core; PL is clocked through the clock domain of PS.

The external nonvolatile storage module is used for storing system default parameters and a system starting program of the motion control platform by using QSPI Flash; the eMMC is used for independent storage of the CPU0, the CPU1 and PL files, and dynamic loading and updating of the files are achieved.

Meanwhile, PS and PL are interconnected and communicated through AXI4 high-speed bus. Xilinx provides a PL peripheral memory mapping mechanism, and can map the functional module of PL into the memory space of PS system, thereby realizing the data access of PS system to the PL module.

In the embodiment of the present invention, the SoC system shared resource management method, which adopts a resource exclusive allocation manner to ensure efficient and independent access of the double-check resource, specifically includes: exclusive allocation of Cache, exclusive allocation of memory space, and exclusive allocation of peripheral resources.

in the embodiment of the invention, the time sequence control technology of the SoC system adopts an FPGA hardware interrupt trigger mechanism to ensure the synchronous control of the clock domain of the SoC system; the FPGA hardware interrupt triggering mode is adopted, so that the problem of time deviation of a timing period after the system runs for a long time due to the fact that a plurality of CPUs are adopted to perform timing communication respectively is effectively solved, the time consistency of the periodic task communication of the system is guaranteed, and the stability and the synchronism of system control are improved.

In the embodiment of the present invention, the platform key communication interface technology includes: RS232 serial port communication design, USB multi-path expansion interface design and gigabit Ethernet interface design.

As shown in fig. 3, the method for designing an SoC core system and implementing task communication between cores under an AMP architecture provided in the embodiment of the present invention specifically includes:

S201, building a dual-core system and completing the transplantation of equipment drive.

S202, step two, a communication module design based on the shared memory is carried out.

S203, step three, aiming at the requirements of different communication tasks of the system, a multi-task communication implementation scheme is provided.

the technical solution of the present invention is further described below with reference to the accompanying drawings.

1. And designing the overall architecture of the multi-axis motion control platform.

The invention analyzes the use requirements of the multi-axis motion control platform of the robot, provides a design scheme of the multi-axis motion control platform based on the dual-core SoC, and further completes the overall hardware architecture design of the motion control platform and the task communication strategy design between dual-core systems.

1.1 design analysis of a multi-axis motion control platform.

as shown in fig. 4, the industrial bus type motion control system adopts a separate system structure. The motion control system is composed of an upper computer, a controller, a plurality of servo drivers, a servo motor and the like. The separated motion control system is mainly characterized in that: the master station and the slave station are connected and communicated through a field bus; the multiple slave stations are communicated in series, and the cooperative control of the multiple slave stations is ensured through the synchronous function of a bus protocol.

The invention designs an integrated multi-axis motion control platform based on a multi-core SoC (system on chip), which realizes hardware integration of a controller and a plurality of drivers, and has a structure shown in figure 5. The integrated motion control platform is mainly characterized in that: the on-chip bus is used for realizing high-speed intercommunication of the control system and the driving system, so that the high efficiency and stability of information transmission are ensured; the unified servo control system is used for completing multi-axis servo function control, information among multiple axes can be quickly interacted, and multi-axis synchronous control is effectively guaranteed. The motion control system is connected with the upper computer, completes motion track planning and motion instruction generation, and is in data communication with the servo system; the servo drive system responds to the control system commands and realizes multi-axis synchronous motion through three-ring (position, speed and current) control.

According to the above analysis, the multi-core SoC motion control platform needs to consider the following requirements:

(1) How to efficiently utilize multi-core SoC resources and respectively realize a control system and a high-performance servo drive system of a platform.

(2) How to utilize an on-chip bus interface to realize the high-efficiency communication between a control system and a servo drive system.

(3) How to design the communication time sequence of the SoC system and complete the synchronous processing and synchronous control of multi-axis motion data.

(4) How to utilize SoC peripheral resources to complete platform interface design and realize external communication and expansion functions.

Meanwhile, the dual-system integrated design also needs to consider the following requirements:

(1) how to design a strong real-time operating system to realize the real-time processing of the motion control task.

(2) How to design the servo driving system under the AMP architecture realizes the stable operation of the servo system.

(3) How to design a dual inter-system communication mechanism under the AMP architecture, and realize multi-task communication of the system, including a periodic task for instruction/feedback data interaction and an aperiodic task for data interaction such as system parameters.

1.2SoC motion control platform hardware architecture design.

1.2.1SoC chip model selection.

Based on the use requirement of the integrated motion control platform, a multi-core SoC chip integrating a high-performance processor needs to be selected. Meanwhile, when a chip is selected, the integrity of the chip function, the market application range, the life cycle, the use cost, the chip power consumption and the like need to be evaluated. And according to comprehensive evaluation, selecting Zynq 7020 of Xilinx company as an SoC central processor of the multi-axis motion control platform.

Zynq 7020 is a highly integrated SoC processor chip with the system interconnect structure shown in FIG. 6. Zynq 7020 integrates a dual core ARMCortex-A9MPCore Processing System (PS) and Programmable logic units (PL) up to 85k in a chip. The main characteristics of PS are:

(1) The PS has two Cortex-A9 processor cores, and can be designed into a dual-core system.

(2) Multiple device controllers such as DDR, SDIO, gigabit Ethernet, USB2.0, UART and the like are integrated, the minimum system function of SoC can be realized, and mainstream communication interface design is performed.

(3) the AMBA AXI4 high-speed bus interface is supported in the chip, and high-speed communication among system units can be realized.

(4) 256K On-Chip RAM (On Chip Memory, OCM for short) is integrated, and system shared data can be saved.

(5) Each processor core independently has a level 1Cache (L1 Cache for short) of 32KB and shares a level 2Cache (L2 Cache for short) of 512KB, so that the data access speed of the CPU is improved, and the system performance is further improved.

Meanwhile, the PL adopts a 28nm programmable logic unit, so that low power consumption and low cost of the chip are ensured. Abundant logic units and DSP resources are available to implement a variety of application functions. IO pin selection schemes of 125 to 200 are provided, and IO control can be conveniently realized. Xilinx provides a large amount of third-party IP core module support, is convenient for users to use, and can effectively reduce the development period. Therefore, the Zynq 7020 chip can meet the development requirement of the invention.

1.2.1 platform architecture design and function.

Based on functional requirements, the invention designs a multi-axis motion control platform architecture based on Zynq 7020 dual-core SoC. As shown in fig. 7, the multi-axis motion control platform mainly consists of two parts, namely a SoC minimum system and a platform interface.

the SoC minimum system comprises a processor 0, a processor 1 and an FPGA, and the specific functions of each part are as follows:

(1) Processor 0(CPU0) is loaded with a real-time operating system. The specific functions are as follows: and running robot control software to complete motion planning and instruction generation. And multi-task communication with the servo system is realized through a system communication interface, and data interaction is completed. And managing SoC peripheral resources, providing peripheral drive support and realizing connection and communication with external equipment.

(2) The processor 1(CPU1) is mounted with a servo bare engine system. The specific functions are as follows: and operating servo control software to complete the three-loop control. And multi-task communication with an operating system is realized through a system communication interface, and data interaction is completed. And managing the SoC peripheral to realize the connection of external equipment and the acquisition of signals.

(3) And the FPGA realizes a self-defined function module. The specific functions are as follows: a hardware interrupt generator is designed to provide interrupt signals with fixed periods for the processor 0 and the processor 1, and the interrupt signals are used for realizing multi-task communication between dual-core systems. Meanwhile, the FPGA also comprises a PWM generator, a current sampling module, an encoder analysis module and other multi-axis driving modules.

Meanwhile, the multi-axis motion platform interface is divided into a communication interface and a system interface. Wherein the communication interface mainly comprises: and the RS232 serial port is used for system development and test of the control platform and later maintenance of the system. And the USB2.0 interface is used for connecting external keyboard, mouse, USB flash disk and other equipment, is convenient for user operation and can realize online upgrade of the system. And the gigabit Ethernet interface is used for connecting the platform with a handheld box or a PC (personal computer) machine to realize upper computer communication. And the industrial Ethernet interface is used for connecting external servo drivers or industrial cameras and other equipment to realize platform function expansion. The system interface is used for completing functions of servo driving, system monitoring, IO control and the like.

According to the functional requirements of the SoC platform, the invention mainly develops and designs the following key technologies:

(1) And designing a SoC hardware system, including minimum system design, resource allocation and communication timing design of the SoC.

(2) Platform communication interface technologies are developed and include UART, USB and gigabit ethernet interface designs.

(3) And the AMP dual system design comprises the design and the realization of a real-time operating system and a servo bare engine system.

(4) The design of the technology of the multi-task communication between the double cores comprises the design of a communication module and the design of a multi-task communication mechanism.

1.3 multitask implementation strategy of the dual-core system.

The invention adopts AMP dual-core system design, which is respectively a CPU0 operating system and a CPU1 servo bare computer system, and data interaction is carried out between the systems by adopting an on-chip shared memory OCM.

1.3.1 type selection of embedded operating system.

The CPU0 operating system is mainly used to run robot control software, and needs to complete trajectory planning quickly and issue commands in time to realize multi-axis real-time motion control. Meanwhile, an operating system needs to provide driving support of a universal peripheral, so that the development of a user is facilitated, and the development difficulty is reduced.

Therefore, an operating system suitable for the platform design should have the characteristics of real-time processing capability, good device driving support, easy development, low cost and the like, and meanwhile, the problems of openness, human-computer interface function, reliability and the like of the system are further considered. In the model selection process, the selected system can meet the design requirements, and meanwhile, the purposes of simplifying the development process and reducing the system development difficulty and the use cost are achieved. The currently popular embedded real-time operating systems mainly comprise uC/OS-II, Linux + Xenomai, Wince and VxWorks, and Table 1 is used for comparing and analyzing the four operating systems.

TABLE 1 comparison of four operating systems

Item	uC/OS-II	Linux+Xenomai	Wince	VxWorks
					Cost of use	Free of charge	Free of charge	charges are expensive	charges are expensive
Openness of	Opening of source code	Opening of source code	without power-on	Without power-on
					System real-time	In general	Is stronger	Is stronger	Strong real-time property
System reliability	In general	High strength	High strength	high strength
					Human-machine interface	difficulty in	Is easy to use	Is easy to use	Difficulty in
system customizability	Customizable	customizable	Inconvenient customization	Inconvenient customization

Vxworks and Wince have strong real-time performance, but source codes of the Vxworks and Wince are not open to the outside, so that development difficulty cannot be predicted, the problem of subsequent cross-platform system transplantation can be caused, and the system needs to pay license cost when in use. The mu C/OS-II system is free from open source and can provide the real-time function of the system, but cannot meet the use requirement of a human-computer interface, and is inconvenient for subsequent upgrading of products. The Linux + Xenomai operating system can provide real-time functions after Xenomai is expanded in real time, and has the advantages of software open source, strong portability, capability of providing a human-computer interface and the like. And comprehensively considering, selecting a Linux + Xenomai real-time operation system.

1.3.2 System multitask implementation strategy design.

The invention adopts a communication scheme based on the shared memory OCM to realize the task communication between the dual-core systems of the motion control platform, and the realization process of the task communication is shown in figure 8.

And running robot control software on a Linux real-time operating system of the CPU0 to establish a Xenomai real-time motion task. In multi-axis motion control, two tasks of periodic communication and non-periodic communication are required to be carried out between dual-core systems, and specific communication is realized through a service function. The periodic tasks complete control instruction issuing and feedback reading in a fixed period, and the non-periodic tasks complete operations including servo parameter reading and writing, system command issuing and the like. In the service function, OCM access service is provided through system call to realize data interaction

The CPU1 builds a servo bare engine system for direct loading and running of servo control applications. And providing a task communication function in the application program for task communication between systems. In the task communication function, data access to the shared memory OCM is realized by calling an API (application program interface) provided by Xilinx official.

2. And designing a motion control system hardware platform based on the SoC.

The invention introduces the hardware design of a motion control platform, mainly performs the function design of a SoC minimum system and completes the management and distribution of system shared resources. And analyzing the control time sequence of the SoC system and finishing the communication time sequence design among the units. And simultaneously, carrying out circuit design on the platform communication interface.

2.1SoC minimum system function design.

2.1.1SoC minimum System hardware Module design.

in order to ensure stable operation and normal operation of the platform, SoC minimum system function design needs to be completed. Fig. 9 shows a block diagram of a complete structure of a SoC minimum system, which mainly explains the following key modules in detail: start mode configuration, system interrupt and clock, DDR DRAM, Quad SPI Flash (QSPI Flash for short) and emcc (embedded MultiMedia card).

(1) And designing a system starting mode.

The various starting modes supported by the SoC system are given in the table 2, and three starting modes of JTAG, SD card and QSPI Flash are reserved based on the system upgrading requirements after the development test and platform productization of the SoC dual-core system. The JTAG mode is convenient for users to quickly position and solve the problem of system development. The SD card mode ensures the quick replacement and the moving of the system file and reduces the system development time. The QSPI Flash mode ensures the quick start and stable operation of the system and is used for the platform product design. And a 6-path dial switch is connected to a BOOT pin of the SoC in hardware design, so that the quick switching of the starting mode is realized.

TABLE 2SoC System Start-Up mode configuration

Starting device mode	BOOT_MODE[2..0]
		JTAG	000
NOR Flash	001
		Nand Flash	010
QSPIFlash	100
		SD card	110
Retention	Retention

(2) A system interrupt generator.

In order to ensure the accuracy and the synchronism of the task cycle time of the SoC dual-core system, the PL is adopted to provide an interrupt signal for the SoC dual-core, and a clock is provided for the PL through a clock domain of the PS. As shown in fig. 10, the PL clock is generated by a PLL (Phase-Locked Loop) on the PS side, i.e., an IO PLL, an ARM PLL, and a DDR PLL. The user application program can obtain the PL clock with the target frequency by correspondingly configuring the register of the PL clock management unit. PLCLK0 and PLCLK1 after IO PLL frequency division processing are respectively used as a PL global clock signal and an auxiliary clock signal, and the clock frequencies are respectively 72MHz and 20MHz, so that clock consistency of PS and PL is ensured.

As shown in FIG. 11, the axi _ timer _0 global timer block is implemented in PL, completes the timing task of the specified period in the timer, and generates two-way interrupt signals, which are respectively transmitted to CPU0 and CPU 1. The CPU0 and the CPU1 implement synchronous communication of periodic communication tasks by responding to a hardware interrupt of the PL.

(3) DDR memory design.

The SoC is loaded with a Linux operating system and a servo logic system, so that sufficient RAM memory resources are required to be provided for system development and operation. A256 KB RAM memory is arranged in the Zynq 7020SoC and can be used for running a firmware program which is programmed by a merchant when the chip leaves a factory in the chip starting stage. The SoC is internally integrated with a DDR memory controller, an external communication interface is provided, DDR equipment with 16-bit or 32-bit bus width is supported, and the equipment type supports DDR2, DDR3 and LPDDR 2. Meanwhile, a 64-bit wide AXI4 up interface (DDRI) is provided, and high-speed access to DDR of the double CPUs is guaranteed.

As an upgraded product of DDR2, DDR3 has a higher operating clock frequency while reducing power consumption and data communication delay. In terms of product service performance and chip life cycle, the system memory design is carried out by adopting MT41K128M16HA DDR3 of 2-chip magnesium optical company. As shown in fig. 12, a 512GB memory space with a 32-bit bus width is designed by a bus parallel connection manner, so as to ensure development and use of the system.

(4) An external non-volatile memory design.

During the power failure of the platform, the system needs to have an independent memory to store dual-core system programs and PL programming files, so that the files are prevented from being lost. Therefore, QSPI Flash is used for storing system default parameters and a system starting program of the motion control platform, and the system is quickly started. Meanwhile, the eMMC is used for independently storing the CPU0, the CPU1 and the PL files, dynamic loading and updating of the files are achieved, and operability and rapidness of software upgrading are guaranteed.

QSPI Flash is Flash equipment adopting a four-wire SPI communication protocol, supports four-channel data synchronous transmission, ensures the data communication rate and reduces the use cost. S25FL256S is selected as a QSPI Flash memory, and the capacity of the QSPI Flash memory is 32 MB. As shown in fig. 13, the SoC internally integrates a QSPI Flash controller and an external Flash chip to be interconnected, the communication clock frequency is 100MHz, and chip selection is completed through a CSS. Meanwhile, the QSPI Flash controller provides an AXI4 upward interface, and high-speed access of the double CPUs is guaranteed.

The invention adopts a Linux operating system which is cut and expanded in function, and the size of a root file system of the Linux operating system is 79.8MB, so that a large-capacity memory needs to be selected. eMMC is a highly integrated Flash device that employs a standard MMC interface. The communication rate of the eMMC can reach 52Mbytes, interface pins are few, and the communication rate is guaranteed while the integrated design of the SoC system is facilitated. The storage capacity of the magnesium-light-adopted EMMC chip of the MTFC4GACAJCN model is 4GB, and the use requirement is met. As shown in fig. 14, the SoC internal SD/SDIO controller is interconnected with the external eMMC chip, and the communication clock frequency is 100MHz, thereby realizing fast data transmission.

2.1.2PS and PL on-chip bus interface technologies.

And each functional module in the Zynq 7020SoC chip is used for carrying out on-chip interconnection communication through an AXI4 protocol bus. The AXI4 protocol is a triggered based transport mechanism that enables high bandwidth, high performance, and low latency bus communications. AXI 4.0 specifies three specific interface protocols, AXI4, AXI4-Lite and AXI4-Stream, respectively, and the interface communication is shown in fig. 15.

the AXI4 protocol interface supports burst mode data transmission with variable data length, and is suitable for high-speed communication between a processor and a memory unit. The AXI4-Lite protocol interface has small scale, only supports burst mode data transmission with single data length, and can be used for accessing independent units such as registers or low-speed peripherals. The AXI4-Stream protocol interface supports continuous write operation with variable data length, and can be used for occasions with large-capacity data communication such as PCIe and DMA. In the Zynq 7020SoC chip, 9 AIX4 protocol bus interfaces are integrated on the PS side, as shown in fig. 16. The AXI _ GP interface supports AXI4 and AXI4-Lite protocol. The AXI _ HP interface supports AXI4 and AXI4-Lite protocols for communication scenarios where PL is the master device. The AXI _ ACP interface supports the AXI4-Stream protocol for communication scenarios where the PL is the master.

When a functional module in a PL is accessed by a PS, the PS is the master and the PL is the slave. The PS uses the M _ AXI _ GP0 master interface for data transfer. Meanwhile, the PL functional module is mapped into a 4GB address space of a PS system as a PS peripheral, and the PS performs data access in a register reading and writing mode, so that an AXI4-Lite protocol is adopted on an M _ AXI _ GP0 interface to realize data communication.

Therefore, a one-master-multi-slave connection mode is adopted to realize that the PS communicates with a plurality of PL modules. The M _ AXI _ GP0 interface is used directly in PS and the AXI Interconnect IP provided by xilinx is used in PL to complete the system Interconnect bridge Axi _ connect _ bridge design. Axi _ connect _ bridge provides an AXI4-Lite protocol slave interface and a plurality of AXI4-Lite protocol master interfaces, the width of the interfaces is 32 bits, and the maximum number of the master interfaces is 16. As shown in fig. 17, Axi _ connect _ bridge slave interface is connected to PS, PL module system is connected to AXI4-Lite master interface.

The PS allocates 1GB of address space, ranging from 0x4000_0000 to 0x7FFF _ FFFF, to PL peripherals connected through the M _ AXI _ GP0 interface. The PL allocates to each module, after the servo module design is completed, a device fixed base address and a device addressing range within 1GB of address space, and the servo modules implemented in the PL and their address allocation schemes are listed in table 3. Where axi _ timer _0 is the global timer block of the PL, timer count and system interrupt. axi _ xadv _0 is the bus voltage sampling module of the motion control platform. axi _ uartlite _0 is a serial controller implemented in PL, used to assist in serial functions. axi _ commom _0 is a synchronization signal control module of the multi-axis servo drive. axi _ single _ axis \{ 0,1,2,3} is a driving integrated module of each motion axis, and functions of an encoder, current sampling, PWM generation and the like are realized.

TABLE 3 PL Servo function Module Address Allocation Table

User IP module	Base address	maximum offset address
			axi_timer_0	0x4280_0000	0x4280_FFFF
axi_xadv_0	0x42C0_0000	0x42C0_FFFF
			axi_uartlite_0	0x43C0_0000	0x43C0_FFFF
axi_commom_0	0x43C1_0000	0x43C1_FFFF
			axi_single_axis_0	0x43C3_0000	0x43C3_FFFF
axi_single_axis_1	0x43C4_0000	0x43C4_FFFF
			axi_single_axis_2	0x43C5_0000	0x43C5_FFFF
axi_single_axis_3	0x43C2_0000	0x43C2_FFFF

2.2 SoC system shared resource management method.

based on the AMP dual core system architecture, in order to avoid the system crash or crash problem caused by the simultaneous access of the dual cores to the same resource, the shared resource needs to be reasonably allocated and managed. The invention adopts the allocation mode of exclusive resource to ensure the efficient and independent access of the resources by double check.

2.2.1 Exclusive allocation of Cache.

The Cache buffer is a device for the CPU to access data at high speed, and the dual cores in the SoC respectively have 64KB L1Cache and share 512KB L2 Cache. Zynq 7020 dual Cache access is shown in FIG. 18. When the Cache is used, an operating system needs to adopt a bus monitoring strategy to ensure the consistent state of data in the Cache and data in a memory. Under the AMP architecture, the double check L2Cache has equal access rights, and competing accesses of Cache may occur. When the CPU0 saves the data in a Cache line and the CPU1 updates the Cache line, it will cause the CPU0 to lose the data and vice versa. In order to guarantee the consistency of dual-core data access and the safety of a system and simultaneously consider the efficiency requirements of task scheduling and data processing of a Linux system on a CPU0, an L2-Cache is set to be occupied by a CPU0 independently, and the CPU1 cannot perform illegal access to the L2-Cache.

2.2.2 Exclusive Allocation of memory space.

based on the platform hardware design, the dual-core system has 512MB memory access resources. The DDR memory is used for loading and running of the CPU0 and the CPU1 dual system. In order to avoid illegal access of dual-core systems during operation, 512MB of memory space needs to be reasonably divided, and it is ensured that different CPU systems have independent memory areas. As shown in table 4, considering that the CPU0 runs the Linux system and the user program, 382MB of memory is allocated to the CPU0, and 130MB of memory is allocated to the CPU.

TABLE 4 Dual core System memory Allocation scheme

Starting address	ending address	Memory size	Description of memory functions
				0x00000000	0x000FFFFF	1MB	Servo system start code
0x00100000	0x17EFFFFF	382MB	Linux operating system
				0x17F00000	0x17FFFFFF	1MB	System reservation
0x18000000	0x1FFFFFFF	180MB	servo bare engine system

2.2.3 Exclusive Allocation of peripheral resources.

The SoC system has abundant peripheral equipment and IO interface resources, and the peripheral equipment is allocated to the fixed CPU for use in an exclusive mode. According to the difference of the dual-core CPU implementation functions in the motion control platform, SoC peripheral resources are allocated, as shown in Table 5. The CPU0 has exclusive use of Ethernet, USB, serial port, I2C and general IO peripheral, and is used for external communication of the platform and connection of on-board I2C devices. The CPU1 monopolizes the system ADC devices to perform analog signal acquisition and processing functions.

TABLE 5 SoC peripheral resource Allocation scheme

starting address	Processor CPU0	Processor CPU0
			System Ethernet controller	Monopolizing
System USB controller	Monopolizing
			System serial port controller	Monopolizing
system I2C controller	monopolizing
			System ADC controller		Monopolizing

2.3 SoC system timing control technique.

The SoC system comprises three processing units, namely a CPU0, a CPU1 and an FPGA, and the synchronization performance of multi-axis motion is guaranteed through communication time sequence control among the units. The CPU0 and the CPU1 perform data exchange with a fixed interpolation period (CPU 0-1 communication for short). In the interpolation period, data interaction of a plurality of fixed current loop control periods (CPU 1-FPGA communication for short) is carried out between the CPU1 and the FPGA.

As shown in fig. 19, the present invention adopts an FPGA hardware interrupt trigger mechanism to ensure synchronous control of the SoC system clock domain. The FPGA global timer adopts the same clock source to generate a periodic timer interrupt 0 and an interrupt 1 which are respectively sent to the CPU0 and the CPU 1. The CPU0 and the CPU1 enter an interrupt processing state upon receiving the interrupt signal, and start performing the corresponding cycle communication. By adopting the FPGA hardware interrupt triggering mode, the problem of time offset of the timing period after the system runs for a long time due to the fact that a plurality of CPUs are adopted for timing communication respectively can be effectively avoided, the time consistency of the system period task communication is ensured, and the stability and the synchronism of system control are improved.

State transition of CPU0-1 communication. The CPU0-1 uses the shared memory OCM of the system for communication as a data storage area, and stores the communication status flag and the configuration data, control instruction data, and servo feedback data of each motion axis. In the periodic task communication stage, the CPU0 will complete system self-test and initiate data communication, and the CPU0 mainly completes updating of configuration data and control instructions in the storage area, and reads servo feedback data in the storage area for the next period of trajectory planning. When the CPU0 completes the data storage area access, a communication status flag is set to notify the CPU1 to start the data access. When detecting the notification that the storage area data access is available, the CPU1 reads the configuration data and the control instruction issued by the CPU0 from the data area, and updates the storage area servo feedback data. When the CPU1 completes the data storage area access, the communication status flag is cleared and the data storage area is again in an idle state. When the CPU0 or the CPU1 does not respond in time in the communication stage, the periodic task communication is abnormal, and at the moment, an OCM communication abnormal interrupt is sent to the CPU0 and is processed by the control system in a unified way.

And in the CPU1-FPGA communication stage, the CPU1 completes the access and control of each shaft function module in the FPGA, and the invention adopts a control mode of multi-shaft synchronous acquisition and synchronous processing. In the synchronous control of the CPU1-FPGA communication phase, ta represents the encoder data acquisition and analysis time. tadc represents current sampling and data processing time. tctl represents the servo control algorithm computation time. The servo control modules of all axes in the FPGA all work in the same clock domain, so that synchronous triggering of control signals such as enabling and resetting of all axis function modules is completed through the axi _ commom _0 module in the FPGA, synchronous operation of all axis function modules is guaranteed after the same calculation time, and multi-axis synchronous performance of a control system is effectively guaranteed.

2.4 platform Key communication interface technology.

2.4.1 RS232 serial port communication design.

The invention adopts the RS232 serial port for system test in the platform development process. The SoC chip integrates the UART controller function, the controller provides mutually independent data transceiving channels, each channel is provided with a 64-byte buffer area, and a communication mode of a half/full duplex mode is supported. The MAX3232EIPW chip is used as the PHY chip, so that the conversion between the logic signal level of the UART controller and the RS232 protocol level is realized, the chip is powered by 3.3V voltage, and the power consumption of the chip is reduced. Meanwhile, the electrostatic protection circuit is integrated in the chip, so that the chip can be prevented from being damaged due to electrostatic interference of the interface, and the normal communication function under the industrial complex application scene can be ensured.

2.4.2 USB multiple expansion interface design.

The USB interface is used for connecting external keyboard, mouse, USB flash disk and other equipment, and is convenient for users to operate. Meanwhile, aiming at the problem that the number of SoC Ethernet interfaces is limited, the interfaces are expanded through a USB, and then the hundred-mega Ethernet interface used for the external expansion function of the platform is realized.

The invention adopts a USB2.0 high-speed OTG (on-the-go) controller built in an SoC chip to realize the function of a USB host, and supports the connection of an ULPI (Universal Serial bus Interface) (USB2.0Transceiver Macrocell Interface + low pin Interface). USB3320C-EZK is selected as a USB PHY chip, a high-speed USB2.0 ULPI transceiver is provided, mutual conversion of ULPI interface signals and USB DP/DN differential signals is realized, and the differential signals generated by conversion can be used for external port communication. Meanwhile, the TUBB 4041I chip is selected as the USB multiplexer. In the USB HUB multi-channel expansion design. The USB HUB realizes four-way expansion of the USB2.0 interface, wherein two USB2.0 downlink ports are used as external USB communication interfaces. And the other two USB2.0 downlink ports are connected with a protocol conversion chip to realize protocol conversion between the USB2.0 and the Ethernet and are used for the external extension function of the platform.

The differential signal pair generated by the USB HUB is firstly connected with the ACM2025 common mode inductor in series, then connected with the NUP4301MR6 device in parallel, and finally connected to an external USB interface. The ACM2025 is a common mode interference suppression device, and is connected in series to the differential signal pair line to filter out high-frequency common mode interference signals on the line, thereby ensuring the transmission quality of the signals. The NUP4301MR6 device is an electric protection chip integrated with a low-capacitance diode array, and can realize protection of the USBHUB by conducting an internal diode to perform rapid discharge or power supply during electric transient (such as electrostatic interference). The power supply capacity of an uplink interface of the USB HUB is limited, and in order to ensure that a downlink port for external communication has stable power supply current, an external power supply TPS54383 is used to supply power to the downlink port.

The USB expansion industrial Ethernet interface circuit adopts AX88772B as a communication protocol conversion chip. The AX88772B is internally integrated with a high-speed Ethernet controller for converting USB2.0 and 10/100Mbps protocols, and the mutual conversion between signals is completed, so that the industrial Ethernet bus communication is realized. An external communication port of the industrial Ethernet adopts an RJ45 interface of an integrated network transformer, so that internal and external electrical isolation of the system and the stability of signal transmission are ensured.

2.4.3 gigabit ethernet interface design.

The invention adopts the gigabit Ethernet interface to realize the connection and communication with the upper computer handheld box, thereby ensuring the communication speed. The Zynq-7020SoC chip integrated Gigabit Ethernet controller provides an adapter from a GMII (Gigabit Media Independent interface) interface to an RGMII (reduced Gigabit Media Independent interface) interface. The KSZ9031RNX is selected as a PHY chip, provides link rate self-adaption and full-duplex auto-negotiation functions and provides an RGMII communication interface. The SoC built-in Ethernet controller is interconnected with KSZ9031RNX through an RGMII interface, and KSZ9031RNX is simultaneously interconnected with an RJ45 external communication port.

The RJ45 interface adopts HR915330AE of Shenzhen Hanren, and a network transformer is integrated in the interface, so that the electrical isolation of a platform internal system and an external communication network cable can be completed, and the anti-interference capability of the system is improved. The LED _ LINK signal and the LED _ ACT signal of the PHY chip are connected with the indicator lamp on the RJ45 interface, and can reflect the real-time connection state and the LINK communication speed of the communication LINK.

3. and (3) designing multi-task communication between the SoC dual-core system and the cores.

The invention provides a method for designing an SoC core system under an AMP architecture and realizing task communication between cores. The method comprises the following steps: firstly, the dual-core system is built and the transplantation of the equipment drive is completed. Then, a communication module design based on the shared memory is carried out. And finally, aiming at the requirements of different communication services of the system, a multi-task communication implementation scheme is provided.

3.1 Dual-core system design and implementation.

3.1.1 Linux real-time system building.

(1) Xenomai real-time patch installation.

The Linux operating system does not provide a real-time function, needs to be expanded through Xenomai, and the two are combined to form a double-kernel real-time system. Xenomai adopts an ados (adaptive Domain Environment for Operating System) technology to ensure the hard real-time expansion.

In a dual core architecture using Adeos, Adeos mainly completes the operations of domain scheduling, interruption, domain management, and the like. The priority of the domain is set in the Adeos architecture, and the Xenomai domain is higher than the ordinary Linux domain. Thus, when the system receives an interrupt signal, Adeos assigns the interrupt to Xenomai for processing. And only after the execution of the task in the Xenomai domain is finished, the task in the Linux domain can be continuously executed. By the scheduling method, Adeos ensures the priority of the Xenomai domain, thereby ensuring the real-time processing of the tasks. The invention realizes the construction of a real-time system by using a Linux4.9.0 version kernel and Xenoma 3.0.7.

To ensure proper use of Xenomai, the important Xenomai function entries in the kernel configuration are listed in Table 6.

TABLE 6 Xenomai important configuration options

And after the Linux + Xenomai system is built, verifying whether Xenoma is installed successfully. After Linux booting is complete, the installation state is viewed via the dmesg | grep I-pipe and dmesg | grep Xenomai commands. The system completes the installation of the Xenomai real-time patch.

(2) And (5) transplanting a Linux device driver.

Based on the design of a key communication interface of the SoC, the external drive is transplanted under the Linux system, so that the correct use of system equipment is ensured, and the external communication of the platform is realized. The linux4.9.0 version of the kernel uses a device model of the bus architecture. In the device model of the bus architecture, the devices and drivers of the system are separated and matched using a bus mechanism. The bus equipment model provides a consistent interface for the driving transplantation of the system, simplifies the transplantation process and improves the development efficiency.

The method for carrying out the drive transplantation of the SoC platform communication interface equipment is specifically divided into two methods:

(2) And for the device which does not provide the driver in the kernel, designing a driver for the device and transplanting the device.

first, by looking at the kernel config configuration file, the Linux-4.9.0 kernel provides device driver support for gigabit Ethernet, USB HUB, and UART. Therefore, the method (1) is adopted to carry out the driven transplantation, and the specific steps are as follows: the kernel configuration is opened using the make menuconfig command. The device driver is configured to be statically loaded, and the self-loading function of the driver is realized when the system is started. The compilation of zImage is done using arm-linux-gcc. After the zImage is used for completing system startup, kernel logs are checked through a dmasg command, drivers of the gigabit Ethernet, the USB HUB and the UART are registered, and the equipment can be normally used.

The Linux-4.9.0 kernel does not provide a driver of the AX88772B network card chip, and the USB extended gigabit Ethernet interface cannot be directly used, so the method (2) is adopted to transplant the AX88772B network card driver.

the invention uses AX88772B official driving source code for the purpose of reducing development difficulty and saving development time, and carries out corresponding design according to platform function requirements on the basis of the official driving source code. By way of analysis, when AX88772B is in use, the external memory stores the PHY chip mac (media Access Control address) address written by the user, and driver registration is completed. In order to meet the configuration requirements of system rapidness and diversification, the invention provides an MAC address dynamic setting method based on an AX88772B chip. The specific method comprises the following steps: and pre-storing the user-defined MAC address in the Flash equipment. And in the registration of the driver, if the external memory is not detected, reading the MAC address of the user from the Flash to finish the registration. And modifying the AX88772B driver, and generating a kernel driver module in a Linux environment, so that a user can conveniently and dynamically load the kernel driver module according to the use condition.

ko kernel module is loaded by the system, and the driver allocates MAC addresses to the two AX88772B network cards through flash in the registration process, so that the network card driver is successfully transplanted.

3.1.2 Servo bare engine system construction.

Mounting the servo bare engine system on the CPU1 requires the following three operations: the Linux system sets the number of CPU uses to 1 at run-time. The CPU0 completes the loading of the CPU1 servo application. The CPU0 completes the wake-up of the CPU 1.

In the starting stage of the Linux system, an SMP symmetrical processing mode is used by default, and two CPUs are managed simultaneously to coordinate related work between the CPUs. Therefore, when using the AMP architecture, the Linux system needs to be restricted to only occupy the CPU0, and the CPU1 is reserved for serving the bare metal system. In the Linux starting process, the kernel file performs corresponding configuration on the system according to the environment variable bootargs, and a user can realize the specification of the CPU usage number by modifying the variable bootargs. The generation of the variable bootargs is divided into a direct designation method and a Bootloader generation method. The direct assignment method is to set bootargs in the kernel configuration process, and the method ensures the uniqueness and effectiveness of the bootargs before reconfiguration. The method for generating the Bootloader comprises the steps of setting bootargs in a Bootloader file, and transmitting the Bootloader to a kernel after the Bootloader is executed. The method provides the possibility and the rapidity of modifying bootargs by a user, and is beneficial to the development and the maintenance of software. The invention adopts a Bootloader generation method. And dynamically configuring and storing bootarms in the boot process of the Bootloader, and setting the number of CPUs used by the Linux system to be 1, thereby ensuring the idle state of the CPU 1. The configuration of the values of the environment variables bootargs is shown in table 7.

TABLE 7 Parametric description of bootargs environmental variables

Parameter item	description of the parameters	Parameter value
			console	terminal equipment for setting and using virtual serial port	ttyPS0,115200
root	setting file system storage locations and loading patterns	/dev/mmcblk0p2rw rootwait
			rootfstype	Setting a format of a file system	ext4
mem	Setting system use memory range	382@0x00100000
			maxCPUs	setting the number of processors used by the system	1
clk_ignore_unused	Setting system not to turn off clock of unused peripheral	Default value

After ensuring that CPU1 is in the idle state, CPU0 needs to complete the loading of the servo application CPU1_ APP. The CPU1_ APP loads the application program into the user-specified memory space. Xilinx provides two implementation methods for loading a bare computer program on SoC: the first is to write the CPU1_ APP to memory using a Jtag writer. The method needs to use an external writer, and only can realize single loading of the program, so the method is suitable for the system development and debugging stages. The second method is to use the Xilinx SDK tool to integrate the CPU1_ APP into Bootloader to form a boot. Bin file is executed when the system is started, and CPU1_ APP is automatically found and loaded into a specified memory. The second method does not need a writer and is convenient for loading operation. However, the loading mode of multi-file integration destroys the independence of the servo application program, and is not beneficial to the independent update of subsequent software.

the invention provides an application program loading method based on Bootcmd environment variables. The Bootcmd is an environment variable of the Bootloader, and stores instruction operations executed by the Bootloader after being started. By dynamically setting Bootcmd in the boot stage of the Bootloader, the instruction operation of loading the CPU1_ APP program is added and saved. After the platform is reset, the Bootloader executes the command in Bootcmd, and loads the CPU1_ APP into the specified memory. The method is also suitable for dynamic loading of the FPGA programming file, and independence of the user file is effectively guaranteed.

Under the AMP architecture of Zynq 7020SoC, CPU1 first executes the chip firmware program to sleep after the SoC is powered on. At this time, the CPU1 must be awakened by the CPU 0. Based on the CPU1 wake-up method provided by Xilinx, when the CPU1 servo software is re-run, the dual system needs to be reset, and the use requirement of the motion control system is not met.

Therefore, the present invention proposes a method for independent re-operation of the CPU1 under the SoCAMP architecture. The method comprises the following implementation processes: (1) during a system boot phase, CPU0 completes the loading of CPU1_ APP. (2) After the system is started, the CPU0 writes an instruction that can implement program jump of the CPU1 into the memory at address 0x 0. (3) The reset operation of the CPU1 is performed in the CPU 0. (4) After the CPU1 is restarted, the jump instruction at address 0x0 is executed, the jump is performed to CPU1_ APP load address (5), the CPU1 executes CPU1_ APP, and the servo system rerun is completed.

And finishing the loading and running of the CPU1 program to realize the construction of a servo system.

3.2 inter-core communication module design.

Based on the requirement of multi-task communication between double cores, the invention adopts the shared memory OCM as a communication medium and carries out the following communication module design: the method comprises a management method of a shared memory, an internuclear semaphore design and a message mailbox design.

3.2.1 management method of shared memory.

The shared memory is a physical medium for task communication between the two cores and is used for storing communication data. The invention adopts 256K on-chip memories inside an SoC chip as a shared memory, and the address range of the shared memory in a 4G addressing space is 0xFFFC 0000-0 xFFFFFF. The on-chip shared memory OCM is used for loading and running a system boot file in the boot process of the SoC chip. After the system is started, the data in the OCM is not empty. Therefore, when task communication is performed by using the OCM, in order to ensure the security and consistency of data in the OCM, the following operations need to be performed:

(1) When the robot control program starts to run, the Linux system completes OCM access application and initializes the OCM.

(2) After the servo system is re-run each time, the Linux system needs to initialize the OCM.

(3) And when the running of the robot control program is finished, the Linux system closes the memory mapping and releases the shared memory.

Aiming at the above operations, three interface functions for the Linux system to access the OCM are designed and implemented, which are respectively: system _ Ocm _ Req (), System _ Ocm _ Init (), and System _ Ocm _ Free (), and the function functions are OCM application, OCM initialization, and OCM release in this order.

In the Linux system, a user process cannot directly access a physical memory as a bare computer program. In order to ensure fast access of the user process to the shared Memory, the System _ Ocm _ Req () function completes the application operation of the shared Memory by a Memory Map (MMAP for short). MMAP is a system call under the Linux system whose function is to map a file or other object into the address space of a process. The MMAP is used in the System _ Ocm _ Req () to complete an access request for an OCM physical memory space of 256KB size. After successful application, a System _ Ocm _ Req () function returns a base address pointer, and the user process performs read-write operation on the OCM in a pointer mode.

The System _ Ocm _ Init () function mainly completes status check, read-write check, and erase of the OCM. In the state check, Linux accesses the OCM state register and judges whether the OCM has a communication error or not, and if the OCM has the communication error, the Linux resets the OCM. And if the state is normal, performing read-write verification. In the read-write verification, user test data are written into the OCM, the data in the OCM are read out after the writing is finished, and the consistency of the data before and after the writing and reading is compared. And if the read-write verification is successful, the OCM is erased, so that the communication safety of the dual-core system is ensured. Otherwise, indicating that the OCM check fails, and carrying out corresponding error processing by the Linux system.

When the robot control software is finished running, in order to ensure the safety of the System, the mapping of the OCM in the process space needs to be closed, and the mapping is realized by a System _ Ocm _ Free () function. In System _ Ocm _ Free (), the mapping relationship is released by using a munmap () System call, and the OCM is released. Linux performs ordered access to OCM in the task execution stage.

3.2.2 Internuclear semaphore design.

In order to ensure the mutual exclusion and consistency of the double-core OCM data access, a semaphore design idea is introduced, and the design of the inter-core semaphore is completed according to the use requirement of the dual-core task communication. Semaphores are a protection mechanism for multiple processes (or threads) to avoid shared resources being accessed by different objects simultaneously [44 ]. When the semaphore synchronization mechanism is adopted, a process (or a thread) can acquire a non-negative integer semaphore to represent the access state of the shared resource. A semaphore of non-zero indicates that there is an idle shared resource that the process (or thread) is allowed to access. A semaphore of zero indicates that the shared resource is empty, and the process (or thread) will be in a wait state. If the number of the shared resources is larger than 1, it is called Counting semaphore (Counting semaphore). If the number of shared resources is 1, the semaphore has only two states, 0 or 1, and is called a binary semaphore (binary semaphore).

according to the method, binary internuclear semaphores are designed, and access of the internuclear semaphores is restricted according to a dual-core task communication time sequence. The inter-core semaphore represents the access state of the OCM data area, and is specifically defined as shown in table 8. When the inter-core semaphore is 1, the OCM data area is idle, and task communication can be initiated. When the inter-core semaphore is 0, it indicates that the OCM data is busy and task communication is in progress. If the semaphore appears in other states, the dual-core system is indicated to have communication errors in the task communication process.

TABLE 8 Internuclear semaphore definitions

Before the dual-core task communication starts, the Linux system initializes the semaphore and sets the semaphore to be 1. In the dual-core task communication stage, the following operations are carried out on the semaphore:

(1) the dual-core system has readable/writable right to semaphore, and if the read-write operation occurs simultaneously, the read operation priority is higher than the write operation priority.

(2) And in the dual-core system task communication stage, sequential semaphore access of 'reading by the CPU 0-modifying by the CPU 0-reading by the CPU 1-modifying by the CPU 1' is carried out.

Wherein, (1) the dual-core system can set the semaphore according to the communication state in the task communication process. In the setting of access priority, the reading operation is higher than the writing operation, and when the dual-core system simultaneously carries out the reading and writing operation on the semaphore, the semaphore is ensured to be read first, and the loss of the communication state is avoided. (2) And the access sequence of the dual-core system to the semaphore in the communication process is set. When task communication between the two cores is carried out, communication is initiated by a Linux system, the system reads the semaphore and judges the state of the semaphore at the moment, and the OCM is accessed when the semaphore is 1. When the semaphore is 0, it indicates that task communication is already in progress. After the linux system completes the OCM access, the semaphore is set to 0. The servo system continuously reads the semaphore, and when the semaphore is 1, no communication is generated. When the semaphore is 0, it indicates that communication is in progress, and the servo system starts accessing the OCM. And after the servo system finishes the OCM access, resetting the semaphore to be 1, and indicating that the OCM is in an idle state.

3.2.3 data message mailbox design.

in the task communication stage of the dual-core system, various types of data communication need to be supported, so that data transmission is realized by adopting a message mailbox. The message mailbox is a data communication method between tasks, and has simple design and low system overhead. And the system task packages and processes the communication data and then sends the communication data to the mailbox, and after the mailbox receives the data mail, the mailbox forwards the mail to other tasks according to the mailbox state. Aiming at the use requirement of multi-axis motion control and the characteristic of mailbox communication, the invention designs two mailbox communication modes, namely fixed-length mailbox communication and variable-length mailbox communication.

In the fixed-length mailbox communication, the mail data length is fixed, and the system can be set to 8/16/32/64 bits according to the use requirement of the communication data. When a fixed-length mailbox is adopted for task communication, the mailbox address needs to be set in the dual-core system initialization stage, and the dual-core system is ensured to access the same mailbox.

When the variable-length mailbox is used for communication, the mail content is a communication data frame, and the length of the data frame is not fixed. In order to ensure the correct analysis of the mail, the dual-core system needs to uniformly set the data frames. Therefore, a data frame format supporting read and write commands and variable data length is designed, and the frame structure is shown in table 9. The data of the mail data frame adopts a 32-bit alignment mode, so that the dual-core system can conveniently store and analyze the data frame. Meanwhile, in the initialization stage of the dual-core system, the mailbox address needs to be set, so that the dual-core system can access the same mailbox.

Table 9 communication data frame structure of variable length mailbox

Different interface functions are designed for two mailbox communication modes of fixed length and variable length, namely DRV _ Control () and DRV _ ASYControl (), and the specific function definitions of the functions are shown in tables 10 and 11.

TABLE 10 DRV Control function definitions

TABLE 11DRV _ ASYControl function functional definitions

3.3 aperiodic task communication technique.

In the process of multi-axis motion control, the dual-core system aperiodic task communication is mainly used for reading information of a servo system, such as servo parameters, by a Linux system.

3.3.1 data Link design.

in the non-periodic task communication, communication data of a dual-core system is diversified, and the message length is not fixed. Therefore, the variable-length mailbox is adopted to complete the data link of the non-periodic communication, and the inter-core semaphore is used to complete the switching of the communication state of the system.

During the non-periodic communication, the inter-core semaphore is set to indicate the access state of the OCM. When the inter-core semaphore is 1, it indicates that the OCM is idle and the aperiodic communication is not started or completed. When the inter-core semaphore is 0, it indicates that the OCM is busy and the aperiodic communication is in progress. The dual-core system determines the real-time state of communication through the inter-core semaphore, thereby performing specific operation and finishing state switching. The definition of the variable-length mailbox is completed on the OCM and is used for storing communication data frames. After the communication starts, the Linux system initiates task communication and writes the encapsulated data frame into a mailbox. And the servo system reads the data frame from the mailbox, completes analysis, encapsulates the response data into a new data frame after the response is completed, and rewrites the new data frame into the mailbox.

3.3.2 aperiodic task implementation based on a polling mechanism.

The non-periodic task communication does not occur periodically, so the invention provides a communication method based on the polling semaphore of a servo system. And circularly inquiring the semaphore of non-periodic communication in the servo system, and judging whether the Linux initiates communication according to the semaphore. And if the communication is initiated, the servo system carries out response operation to complete the inter-core communication task.

in the flow of dual-core aperiodic task communication, the specific operation of the Linux system is as follows:

(1) And completing the encapsulation of the target data frame according to the system command.

(2) And reading the inter-core signal quantity, judging whether the communication is in error or overtime, and performing corresponding processing if the communication is in error or overtime.

(3) And writing the target data frame into the mailbox when the communication state is normal.

(4) After the data frame is written, an inter-core semaphore is set, and a servo is informed to respond.

(5) And inquiring the inter-core semaphore to judge whether the servo completes the response.

(6) and after the servo response is successful, reading servo response frame data (7) and finishing the task communication of the Linux system.

The specific operation of the servo system is as follows:

(1) and polling the inter-core semaphore through the while (1) program to judge whether the communication is in error or overtime, and performing corresponding processing if the communication is in error or overtime.

(2) And if the Linux initiates the task communication, reading the destination data frame from the mailbox.

(3) And analyzing the target data frame to complete corresponding instruction operation.

(4) And encapsulating the response data into a data frame and rewriting the data frame into the mailbox.

(5) After the data frame writing is finished, setting an inter-core semaphore and informing the Linux system that the response is finished.

(6) And ending the task communication of the servo system.

3.4 cycle mission communication techniques.

In the multi-axis motion control process, the periodic task communication of the dual-core system is mainly used for completing the updating of periodic control instructions and the feedback of servo motion data, so that the multi-axis motion control is realized.

3.4.1 data link design.

In the periodic task communication, the communication data type of the dual-core system is fixed, and the data volume is small. Therefore, a data link of periodic communication is completed by adopting a mailbox with a fixed length, and the switching of the communication state of the system is completed by using the internuclear semaphore. The periodic communication data is divided into two types of control instructions and feedback data, and unidirectional transmission is carried out between the two cores. In order to improve data transmission efficiency, a sending mailbox area and a receiving mailbox area are respectively arranged. The control instruction of the Linux system is stored in the mailbox area, and the feedback data of the servo system is stored in the mailbox area.

during the periodic communication, the inter-core semaphore is set to indicate the access state of the OCM. When the inter-core semaphore is 1, it indicates that the OCM is idle and the periodic communication is not started or completed. When the inter-core semaphore is 0, it indicates that the OCM is busy and periodic communication is in progress. The dual-core system determines the real-time state of communication through the inter-core semaphore, thereby performing specific operation and finishing state switching. And completing the definition of a sending mailbox area and a receiving mailbox area on the OCM for storing communication data. In each communication cycle, the Linux system reads feedback data from the receiving mailbox area and writes the control instruction generated in the previous cycle into the sending mailbox area. The servo system reads the control instruction from the sending mailbox area and writes the feedback data generated in the previous period into the receiving mailbox area.

3.4.2 are based on a periodic task implementation of a hardware interrupt mechanism.

The dual-core periodic task communication is carried out by adopting FPGA hardware interruption, namely, a Linux system and a servo system are both synchronous with the FPGA. When the FPGA interrupt signal arrives, the dual-core system respectively responds, and data communication between the dual cores is completed by executing the interrupt service program.

In order to ensure real-time performance, the Linux system completes interrupt service through Xenomai, a real-time task thread under a Xenomai domain is firstly established in a user program, and the task realizes the function of circularly waiting for an interrupt signal. When Adeos schedules tasks, the task of Xenomai wait signal is added into the wait queue, and the thread goes to sleep. When the system receives the interrupt signal of the FPGA, the real-time thread of Xenomai is awakened. And after the thread is awakened, executing an interrupt service function to realize periodic task communication.

In the process of dual-core periodic task communication, the specific operation of the Linux system is as follows: (1) and finishing zero clearing of the watchdog and clearing of the interrupt mark, which indicates that the Linux system receives and processes the interrupt. (2) And reading the inter-core signal quantity, judging whether the communication is in error or overtime, and performing corresponding processing if the communication is in error or overtime. (3) And if the communication state is normal, switching the response cache area, and reading response data from the receiving mailbox area. And (4) after reading is finished, switching the instruction cache area, and writing the control instruction to the mailbox area. (5) After the writing is finished, a semaphore is set, and the servo is informed to respond. (6) And finishing the task communication of the Linux system.

The specific operation of the servo system is as follows: (1) and finishing zero clearing of the watchdog and clearing of the interrupt mark, which indicates that the servo system receives and processes the interrupt. (2) Polling the inter-core semaphore, judging whether the communication is in error or overtime, and if so, carrying out corresponding processing. And (3) if the Linux initiates the task communication, switching the instruction cache region, and reading instruction data from the mailbox region. (4) And after the reading is finished, switching the response cache area, and writing the servo response data to the receiving mailbox area. (5) After the writing is finished, the semaphore is set, and the periodic task communication state is recovered to be an idle state. (6) And ending the task communication of the servo system.

The invention is further described with reference to specific examples.

Examples

1. and (5) building a test platform.

And (4) building a test platform of the multi-axis motion control system. The test platform consists of a safety power supply, a multi-axis motion platform prototype (comprising a main control board MC), an upper computer PC, a handheld box and four 80ST-M01330LMB type Huada alternating current servo motors (built-in 17-bit absolute encoders). The sample machine is connected with the four servo motors through the motor power interface and the encoder interface.

The hardware test of the motion control platform mainly comprises the functions of a UART serial port, a USB2.0 and an Ethernet interface. The task communication test of the platform system comprises two parts of function realization and performance. Wherein, the function test checks whether the dual-core periodic task communication and the non-periodic task communication are normally realized. The performance test checks the real-time performance and synchronous control effect of the motion control system. And finally, running the robot control software on the platform and connecting the handheld box to test the running effect of the whole machine.

2. and testing the hardware function of the motion control platform.

2.1UART interface test.

The control platform is connected with the Windows host computer through the UART interface, and serial port test is carried out by using SSCOM3.2 software. The platform UART interface is correctly identified in Windows as COM 25. And opening a serial port in the SSCOM software, and sending a command to the Linux system. And through message window observation, the Linux system correctly receives the command and executes the command. The test result shows that the UART interface of the system has normal function.

2.2 USB interface test.

The platform is provided with two USB2.0 interfaces for respectively carrying out function test on the two interfaces. The system connects the interface USB0 with a mouse and connects the interface USB1 with a USB flash disk. The Linux system correctly identifies the mouse and the usb disk device. And the file of the USB flash disk can be checked through mount command for mounting the USB flash disk. The test result shows that the USB interface of the system has normal function.

And 2.3, testing the function of the network port.

The platform is provided with three network ports for respectively carrying out function test on the platform. After the network card driver loading is completed, the system can identify three ethernet MACs, which are eth0, eth1, and eth2, respectively. Wherein, eth0 is gigabit Ethernet, eth1 and eth2 are USB extended hundred-gigabit Ethernet. Using an ifconfig command to allocate static IP addresses for the three network cards, sequentially: 192.168.1.113, 192.168.1.114, and 192.168.1.115.

After the IP address of the network card is distributed, the network card is connected with a PC through a network port, and a ping command of Linux is used for network communication test. Data loss does not occur in the network communication process, and three Ethernet interfaces of the platform are normal in function.

3. And (5) testing the communication function and the performance of the system task.

3.1 linux + Xenomai System real-time testing.

The Linux and the Xenomai double inner cores provide a real-time function of the system and verify the effect of the system. The test conditions are shown in table 12.

TABLE 12 Xenomai real-time test Environment

experiment platform	Zynq-7020SoC
		Frequency of operation	667MHz
Linux kernel version	Linux-4.9.0
		xenomai version	Xenomai-3.0.7
Time of measurement	300s
		Task cycles	0.25ms、0.5ms、1ms、2ms、4ms

And (3) verifying the real-time effect of the Linux + Xenomai system by using a Latency test tool carried by Xenomai. The Latency tool can perform periodic self-loop task scheduling of a specified mode according to user input parameters, and count corresponding delay time. And (5) carrying out delay test on scheduling among Xenomai tasks in a user mode.

As a result, Xenomai completed the scheduled task normally under different periodic tasks, as shown in Table 13. The average delay of the task scheduling is less than 4us, and the maximum delay is less than 15 us. The result shows that the Linux + Xenomai system has good real-time performance and multi-task real-time processing capability.

TABLE 13 Xenomai real-time test data

Task cycles	Minimum delay time (us)	mean time delay (us)	Maximum delay time (us)
				0.25ms	1.235	3.103	14.072
0.5ms	1.197	3.463	13.427
				1ms	1.235	3.269	13.952
2ms	1.216	3.472	13.819
				4ms	1.207	3.394	13.443

3.2 functional testing of task communication.

(1) and (5) performing non-periodic task communication test between double cores.

In the non-periodic task communication test, the motion control platform is connected with the servo motor to control the motion. After the platform is powered on, the Linux system completes the enabling of the servo system. The Linux reads the motion parameters of the servo system through the non-periodic communication between the double cores and performs printing display through the serial port.

Meanwhile, the platform is connected with an upper computer through a serial port, and STP software operated by the upper computer realizes real-time monitoring on the servo system. And checking the parameter values of the servo system in the STP software, and comparing the parameters to obtain the consistency between the servo parameters read in the Linux system and the observed results in the STP software. The test result shows that the aperiodic task communication of the dual-core system is normal.

(2) And testing the periodic task communication between the double cores.

in the periodic task communication test, the servo enabling is completed through a Linux system, and the communication period is set to be 1 ms. The Linux system performs position instruction sending in three stages, and the position instruction values are accumulated through fixed increment in each period. As shown in table 14, the increment values of the three phases are: positive pulse increment of 0 th to 1000 th cycle, 0 pulse increment of 1000 th to 2000 th cycle and negative pulse increment of 2000 th to 3000 th cycle. And the servo system controls the multi-axis motion according to the position command value. The method comprises the following steps of carrying out position instruction and position tracking sampling through STP software of an upper computer, wherein the unit of sampling data is radian rad, and the conversion relation with the number of instruction pulses is as follows:

The sampled data shows (rad) ═ 1000 x 2 pi pulse command/131072.

TABLE 14 four-axis cyclic motion position command and position tracking

In the four-movement-axis position tracking effect, the position tracking of the four movement axes is continuously carried out in three stages of communication, and the motor runs stably. The position tracking data is shown in table 14, and the tracking effect is good without pulse loss in the four-axis motion process. The test result shows that the servo system correctly receives and executes the position instruction of the Linux system, and the periodic task communication between the two cores is normal.

3.3 testing the real-time performance and synchronous control of the system.

(1) And testing the real-time performance of the communication task.

(2) and (5) multi-axis synchronous control testing.

The specific requirement of the system synchronous control is to control multiple axes to move synchronously. In the multi-axis synchronous control test, a servo system is enabled through a Linux system, and motion control of a 1ms interpolation period is performed. In order to verify the synchronous control of the multi-axis motion, four paths of PWM motor driving signals generated by the control platform are continuously sampled through an oscilloscope.

TABLE 15 PWM signal control period test for four-way motor

4. And (4) performing online test on robot control software.

And running robot control software on the motion control platform to test the connection function with the robot hand-held box. First, after the motion control system is started, the IP address of the motion control platform is set to 192.168.1.113. And after the setting is successful, running the robot control software hrtapp-5.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A method for designing an SoC core system under an AMP architecture and realizing inter-core task communication is characterized in that the method for realizing the design of the SoC core system under the AMP architecture and the inter-core task communication comprises the following steps:

Step one, constructing a dual-core system and completing the transplantation of equipment drive; the built dual-core system comprises a Linux real-time system and a servo bare engine system; the method comprises the following steps that Linux is operated in real time by the core of a Linux real-time system, and a bare engine for controlling direct loading and operation of an application program is carried by the core of a servo bare engine system;

Thirdly, multi-task communication is carried out by utilizing shared information aiming at different communication tasks; and by utilizing mechanisms of periodic data communication and non-periodic data communication, the periodic data adopts an interrupt mode, the message is fixed, the servo side initiates periodic interrupt, the non-periodic data communication length-variable message, and the bare computer side polls and processes the check request.

2. the method for realizing SoC core system design and inter-core task communication under MP architecture according to claim 1, wherein the first step of building a dual core system includes Linux real-time system building and servo bare engine system building;

The Linux real-time system building method comprises the following steps:

1) Installing a Xenomai real-time patch; running robot control software on a Linux real-time operating system of a CPU0 to establish a Xenomai real-time motion task;

2) Driving and transplanting Linux equipment; based on the design of a key communication interface of the SoC, the external drive is transplanted under a Linux system, so that the correct use of system equipment is ensured, and the external communication of a platform is realized;

The servo bare metal system building comprises:

The method comprises the steps that a servo bare engine system is built by utilizing a CPU1 and used for directly loading and running servo control application programs, and the using number of the CPUs is set to be 1 when a Linux system runs; the CPU0 completes the loading of the CPU1 servo application program; the CPU0 completes the wake-up of the CPU 1.

3. The method for implementing SoC core system design and inter-core task communication under MP architecture as claimed in claim 1, wherein said step one of completing device-driven migration specifically includes:

(1) When the kernel provides the device driver, directly using the driver in the kernel;

4. The method for implementing SoC core system design and inter-core task communication under MP architecture as claimed in claim 1, wherein the step two of performing shared memory based communication method includes shared memory management, specifically including:

1) When the robot control program starts to run, the Linux system completes OCM access application and initializes the OCM;

2) After the servo system is re-run each time, the Linux system needs to initialize the OCM;

5. The method for implementing SoC core system design and inter-core task communication under MP architecture as claimed in claim 1, wherein the step two of using OCM shared memory for inter-core data communication specifically includes:

Using binary internuclear semaphores and restricting the access of the internuclear semaphores according to the sequence of task communication between the double cores; before the dual-core task communication starts, initializing the semaphore by the Linux system, and setting the semaphore to be 1; in the dual-core task communication stage, carrying out the following steps on the semaphore:

1) The dual-core system has readable/writable right to the semaphore, and if the read-write operation occurs simultaneously, the read operation priority is higher than the write operation priority;

6. The method for implementing SoC core system design and inter-core task communication under MP architecture as claimed in claim 1, wherein the step two method for shared memory based communication further includes message mailbox communication, specifically including:

1) The fixed-length mailbox communication, the mail data length is fixed, the system is set to 8/16/32/64 bits according to the use requirement of the communication data;

7. the method for implementing SoC core system design and inter-core task communication under MP architecture as claimed in claim 1, wherein said step three method for multitask communication comprises: an aperiodic task communication technique and a periodic task communication technique;

1) A data link; completing a data link of non-periodic communication by adopting a variable-length mailbox, and completing switching of a system communication state by using an internuclear semaphore;

2) Non-periodic task realization based on a polling mechanism; using a communication method based on a servo system polling semaphore to circularly inquire the semaphore of non-periodic communication in the servo system, and judging whether Linux initiates communication according to the semaphore; if the communication is initiated, the servo system carries out response operation to complete the inter-core communication task;

The periodic task communication technology is used for updating a periodic control instruction and feeding back servo motion data so as to realize multi-axis motion control; the method specifically comprises the following steps:

1) The data link completes the data link of periodic communication by adopting a mailbox with a fixed length, and completes the switching of the communication state of the system by using the internuclear semaphore;

2) The method comprises the steps of realizing a periodic task based on a hardware interrupt mechanism, wherein the periodic task communication between two cores is carried out by adopting FPGA hardware interrupt, and a Linux system and a servo system are both synchronous to the FPGA; and when the FPGA interrupt signal is received, the dual-core system respectively responds, and the data communication between the dual cores is completed by executing the interrupt service program.

8. A system for implementing SoC core system design and inter-core task communication under MP architecture according to claim 1, wherein the system for implementing SoC core system design and inter-core task communication under MP architecture comprises:

The SoC minimum system is used for completing management and distribution of system shared resources, analyzing the control time sequence, completing communication among units and simultaneously communicating with the platform interface;

And the platform interface is used for finishing servo driving, system monitoring and IO control.

9. The system for implementing SoC core system design and inter-core task communication under MP architecture of claim 8, wherein SoC minimal system comprises processor 0, processor 1 and FPGA;

the processor 0 is configured to carry a real-time operating system, and the real-time operating system includes: running robot control software to complete motion planning and instruction generation; the system communication interface is used for realizing multi-task communication with the servo system and finishing data interaction; the management system comprises a management system on chip (SoC) peripheral resource, a peripheral driver and a peripheral driver, wherein the management system is used for providing peripheral driver support and realizing connection communication with external equipment;

The processor 1 is used for carrying and operating a servo bare engine system; the servo bare metal system comprises: operating servo control software for completing three-loop control; the system communication interface is used for realizing multi-task communication with an operating system and finishing data interaction; the management SoC peripheral is used for realizing the connection of external equipment and the acquisition of signals;

The FPGA is used for realizing the self-definition of the functional module; the functional module includes: designing a hardware interrupt generator to provide interrupt signals with fixed periods for the processor 0 and the processor 1so as to realize multi-task communication between dual-core systems;

The device also comprises a PWM generator, a current sampling and encoder analysis multi-axis driving module;

the platform interface comprises a communication interface and a system interface;

the communication interface includes: the RS232 serial port is used for controlling system development and test of the platform and later maintenance of the system;

The USB2.0 interface is used for connecting an external keyboard, a mouse and USB flash disk equipment to realize online upgrading of the system;

The gigabit Ethernet interface is used for connecting a platform with a handheld box or a PC (personal computer) to realize upper computer communication;

The industrial Ethernet interface is used for connecting an external servo driver or industrial camera equipment to realize the function expansion of the platform;

10. The system for implementing SoC core system design and inter-core task communication under MP architecture of claim 8, wherein SoC minimal system further comprises:

The system comprises a system starting module, a system interruption and clock module, a storage control module and an external nonvolatile storage module;

The system starting module comprises three starting modes of JTAG, SD card and QSPIFlash; the JTAG mode is used for quickly positioning the user and solving the problem of system development; the SD card mode is used for ensuring the quick replacement and the moving of the system file; the QSPIFlash mode is used for platform product design;

The system interrupt and clock module adopts PL to provide interrupt signals for the SoC dual core; providing a clock to the PL through the clock domain of the PS;

The system comprises a storage control module, a DDR (double data rate) storage controller integrated in the SoC and an external communication interface;